Lines Matching +full:smbus +full:- +full:timeout +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #include "i2c-designware-core.h"
37 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
38 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
41 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
48 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
57 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
63 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
64 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
67 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
69 dev->ss_hcnt = in i2c_dw_set_timings_master()
76 dev->ss_lcnt = in i2c_dw_set_timings_master()
84 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
85 dev->ss_hcnt, dev->ss_lcnt); in i2c_dw_set_timings_master()
92 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { in i2c_dw_set_timings_master()
97 if (dev->fp_hcnt && dev->fp_lcnt) { in i2c_dw_set_timings_master()
98 dev->fs_hcnt = dev->fp_hcnt; in i2c_dw_set_timings_master()
99 dev->fs_lcnt = dev->fp_lcnt; in i2c_dw_set_timings_master()
102 dev->fs_hcnt = in i2c_dw_set_timings_master()
109 dev->fs_lcnt = in i2c_dw_set_timings_master()
123 if (!dev->fs_hcnt || !dev->fs_lcnt) { in i2c_dw_set_timings_master()
125 dev->fs_hcnt = in i2c_dw_set_timings_master()
132 dev->fs_lcnt = in i2c_dw_set_timings_master()
140 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
141 fp_str, dev->fs_hcnt, dev->fs_lcnt); in i2c_dw_set_timings_master()
144 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == in i2c_dw_set_timings_master()
148 dev_err(dev->dev, "High Speed not supported!\n"); in i2c_dw_set_timings_master()
149 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_set_timings_master()
150 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; in i2c_dw_set_timings_master()
151 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_set_timings_master()
152 dev->hs_hcnt = 0; in i2c_dw_set_timings_master()
153 dev->hs_lcnt = 0; in i2c_dw_set_timings_master()
154 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { in i2c_dw_set_timings_master()
160 * If dev->bus_capacitance_pF is greater than or equals in i2c_dw_set_timings_master()
164 if (dev->bus_capacitance_pF >= 400) { in i2c_dw_set_timings_master()
166 t_high = dev->clk_freq_optimized ? 160 : 120; in i2c_dw_set_timings_master()
171 t_low = dev->clk_freq_optimized ? 120 : 160; in i2c_dw_set_timings_master()
175 dev->hs_hcnt = in i2c_dw_set_timings_master()
182 dev->hs_lcnt = in i2c_dw_set_timings_master()
190 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
191 dev->hs_hcnt, dev->hs_lcnt); in i2c_dw_set_timings_master()
198 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); in i2c_dw_set_timings_master()
203 * i2c_dw_init_master() - Initialize the DesignWare I2C master hardware
207 * This function is called during I2C init function, and in case of timeout at
220 /* Disable the adapter */ in i2c_dw_init_master()
224 * Mask SMBus interrupts to block storms from broken in i2c_dw_init_master()
228 regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); in i2c_dw_init_master()
231 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); in i2c_dw_init_master()
232 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); in i2c_dw_init_master()
235 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); in i2c_dw_init_master()
236 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); in i2c_dw_init_master()
239 if (dev->hs_hcnt && dev->hs_lcnt) { in i2c_dw_init_master()
240 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); in i2c_dw_init_master()
241 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); in i2c_dw_init_master()
245 if (dev->sda_hold_time) in i2c_dw_init_master()
246 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); in i2c_dw_init_master()
256 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_init()
260 /* Disable the adapter */ in i2c_dw_xfer_init()
264 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { in i2c_dw_xfer_init()
267 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing in i2c_dw_xfer_init()
275 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, in i2c_dw_xfer_init()
279 * Set the slave (target) address and enable 10-bit addressing mode in i2c_dw_xfer_init()
282 regmap_write(dev->map, DW_IC_TAR, in i2c_dw_xfer_init()
283 msgs[dev->msg_write_idx].addr | ic_tar); in i2c_dw_xfer_init()
292 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); in i2c_dw_xfer_init()
295 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_xfer_init()
318 regmap_read(dev->map, DW_IC_STATUS, &status); in i2c_dw_is_controller_active()
322 return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, in i2c_dw_is_controller_active()
332 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, in i2c_dw_check_stopbit()
336 dev_err(dev->dev, "i2c timeout error %d\n", ret); in i2c_dw_check_stopbit()
369 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); in amd_i2c_dw_xfer_quirk()
371 dev->msgs = msgs; in amd_i2c_dw_xfer_quirk()
372 dev->msgs_num = num_msgs; in amd_i2c_dw_xfer_quirk()
373 dev->msg_write_idx = 0; in amd_i2c_dw_xfer_quirk()
382 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); in amd_i2c_dw_xfer_quirk()
388 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { in amd_i2c_dw_xfer_quirk()
389 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) in amd_i2c_dw_xfer_quirk()
394 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); in amd_i2c_dw_xfer_quirk()
395 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); in amd_i2c_dw_xfer_quirk()
397 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
398 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
409 regmap_read(dev->map, DW_IC_DATA_CMD, &val); in amd_i2c_dw_xfer_quirk()
417 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); in amd_i2c_dw_xfer_quirk()
438 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_msg()
441 u32 addr = msgs[dev->msg_write_idx].addr; in i2c_dw_xfer_msg()
442 u32 buf_len = dev->tx_buf_len; in i2c_dw_xfer_msg()
443 u8 *buf = dev->tx_buf; in i2c_dw_xfer_msg()
449 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { in i2c_dw_xfer_msg()
450 u32 flags = msgs[dev->msg_write_idx].flags; in i2c_dw_xfer_msg()
457 if (msgs[dev->msg_write_idx].addr != addr) { in i2c_dw_xfer_msg()
458 dev_err(dev->dev, in i2c_dw_xfer_msg()
460 dev->msg_err = -EINVAL; in i2c_dw_xfer_msg()
464 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { in i2c_dw_xfer_msg()
466 buf = msgs[dev->msg_write_idx].buf; in i2c_dw_xfer_msg()
467 buf_len = msgs[dev->msg_write_idx].len; in i2c_dw_xfer_msg()
474 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && in i2c_dw_xfer_msg()
475 (dev->msg_write_idx > 0)) in i2c_dw_xfer_msg()
479 regmap_read(dev->map, DW_IC_TXFLR, &flr); in i2c_dw_xfer_msg()
480 tx_limit = dev->tx_fifo_depth - flr; in i2c_dw_xfer_msg()
482 regmap_read(dev->map, DW_IC_RXFLR, &flr); in i2c_dw_xfer_msg()
483 rx_limit = dev->rx_fifo_depth - flr; in i2c_dw_xfer_msg()
496 * i2c-core always sets the buffer length of in i2c_dw_xfer_msg()
501 if (dev->msg_write_idx == dev->msgs_num - 1 && in i2c_dw_xfer_msg()
510 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { in i2c_dw_xfer_msg()
513 if (dev->rx_outstanding >= dev->rx_fifo_depth) in i2c_dw_xfer_msg()
516 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
518 rx_limit--; in i2c_dw_xfer_msg()
519 dev->rx_outstanding++; in i2c_dw_xfer_msg()
521 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
524 tx_limit--; buf_len--; in i2c_dw_xfer_msg()
527 dev->tx_buf = buf; in i2c_dw_xfer_msg()
528 dev->tx_buf_len = buf_len; in i2c_dw_xfer_msg()
533 * transaction here. Also disable the TX_EMPTY IRQ in i2c_dw_xfer_msg()
538 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
543 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
546 dev->status &= ~STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
553 if (dev->msg_write_idx == dev->msgs_num) in i2c_dw_xfer_msg()
556 if (dev->msg_err) in i2c_dw_xfer_msg()
565 struct i2c_msg *msgs = dev->msgs; in i2c_dw_recv_len()
566 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_recv_len()
574 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); in i2c_dw_recv_len()
575 msgs[dev->msg_read_idx].len = len; in i2c_dw_recv_len()
576 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; in i2c_dw_recv_len()
579 * Received buffer length, re-enable TX_EMPTY interrupt in i2c_dw_recv_len()
580 * to resume the SMBUS transaction. in i2c_dw_recv_len()
592 struct i2c_msg *msgs = dev->msgs; in i2c_dw_read()
595 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { in i2c_dw_read()
600 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) in i2c_dw_read()
603 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { in i2c_dw_read()
604 len = msgs[dev->msg_read_idx].len; in i2c_dw_read()
605 buf = msgs[dev->msg_read_idx].buf; in i2c_dw_read()
607 len = dev->rx_buf_len; in i2c_dw_read()
608 buf = dev->rx_buf; in i2c_dw_read()
611 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); in i2c_dw_read()
613 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { in i2c_dw_read()
614 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_read()
616 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); in i2c_dw_read()
635 dev->rx_outstanding--; in i2c_dw_read()
639 dev->status |= STATUS_READ_IN_PROGRESS; in i2c_dw_read()
640 dev->rx_buf_len = len; in i2c_dw_read()
641 dev->rx_buf = buf; in i2c_dw_read()
644 dev->status &= ~STATUS_READ_IN_PROGRESS; in i2c_dw_read()
664 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_read_clear_intrbits()
665 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
667 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
668 stat &= dev->sw_mask; in i2c_dw_read_clear_intrbits()
676 * Instead, use the separately-prepared IC_CLR_* registers. in i2c_dw_read_clear_intrbits()
679 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); in i2c_dw_read_clear_intrbits()
681 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
683 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
685 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); in i2c_dw_read_clear_intrbits()
691 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); in i2c_dw_read_clear_intrbits()
692 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); in i2c_dw_read_clear_intrbits()
695 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); in i2c_dw_read_clear_intrbits()
697 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); in i2c_dw_read_clear_intrbits()
699 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) in i2c_dw_read_clear_intrbits()
700 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); in i2c_dw_read_clear_intrbits()
702 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); in i2c_dw_read_clear_intrbits()
704 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); in i2c_dw_read_clear_intrbits()
712 dev->cmd_err |= DW_IC_ERR_TX_ABRT; in i2c_dw_process_transfer()
713 dev->status &= ~STATUS_MASK; in i2c_dw_process_transfer()
714 dev->rx_outstanding = 0; in i2c_dw_process_transfer()
731 * No need to modify or disable the interrupt mask here. in i2c_dw_process_transfer()
737 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && in i2c_dw_process_transfer()
738 (dev->rx_outstanding == 0)) in i2c_dw_process_transfer()
739 complete(&dev->cmd_complete); in i2c_dw_process_transfer()
740 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { in i2c_dw_process_transfer()
757 regmap_read(dev->map, DW_IC_ENABLE, &enabled); in i2c_dw_isr()
758 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_isr()
761 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0)) in i2c_dw_isr()
763 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); in i2c_dw_isr()
767 if (!(dev->status & STATUS_ACTIVE)) { in i2c_dw_isr()
771 * disable interrupts for suppressing further interrupts if in i2c_dw_isr()
786 unsigned long timeout = dev->adapter.timeout; in i2c_dw_wait_transfer() local
790 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_wait_transfer()
791 ret = wait_for_completion_timeout(&dev->cmd_complete, timeout); in i2c_dw_wait_transfer()
793 timeout += jiffies; in i2c_dw_wait_transfer()
795 ret = try_wait_for_completion(&dev->cmd_complete); in i2c_dw_wait_transfer()
805 } while (time_before(jiffies, timeout)); in i2c_dw_wait_transfer()
808 return ret ? 0 : -ETIMEDOUT; in i2c_dw_wait_transfer()
820 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); in i2c_dw_xfer()
822 pm_runtime_get_sync(dev->dev); in i2c_dw_xfer()
824 switch (dev->flags & MODEL_MASK) { in i2c_dw_xfer()
832 reinit_completion(&dev->cmd_complete); in i2c_dw_xfer()
833 dev->msgs = msgs; in i2c_dw_xfer()
834 dev->msgs_num = num; in i2c_dw_xfer()
835 dev->cmd_err = 0; in i2c_dw_xfer()
836 dev->msg_write_idx = 0; in i2c_dw_xfer()
837 dev->msg_read_idx = 0; in i2c_dw_xfer()
838 dev->msg_err = 0; in i2c_dw_xfer()
839 dev->status = 0; in i2c_dw_xfer()
840 dev->abort_source = 0; in i2c_dw_xfer()
841 dev->rx_outstanding = 0; in i2c_dw_xfer()
857 dev_err(dev->dev, "controller timed out\n"); in i2c_dw_xfer()
859 i2c_recover_bus(&dev->adapter); in i2c_dw_xfer()
867 * if disable IC_ENABLE.ENABLE immediately that can result in in i2c_dw_xfer()
872 dev_err(dev->dev, "controller active\n"); in i2c_dw_xfer()
875 * We must disable the adapter before returning and signaling the end in i2c_dw_xfer()
884 if (dev->msg_err) { in i2c_dw_xfer()
885 ret = dev->msg_err; in i2c_dw_xfer()
890 if (likely(!dev->cmd_err && !dev->status)) { in i2c_dw_xfer()
896 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { in i2c_dw_xfer()
901 if (dev->status) in i2c_dw_xfer()
902 dev_err(dev->dev, in i2c_dw_xfer()
903 "transfer terminated early - interrupt latency too high?\n"); in i2c_dw_xfer()
905 ret = -EIO; in i2c_dw_xfer()
911 pm_runtime_put_autosuspend(dev->dev); in i2c_dw_xfer()
927 struct i2c_timings *t = &dev->timings; in i2c_dw_configure_master()
929 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; in i2c_dw_configure_master()
931 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | in i2c_dw_configure_master()
934 dev->mode = DW_IC_MASTER; in i2c_dw_configure_master()
936 switch (t->bus_freq_hz) { in i2c_dw_configure_master()
938 dev->master_cfg |= DW_IC_CON_SPEED_STD; in i2c_dw_configure_master()
941 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; in i2c_dw_configure_master()
944 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_configure_master()
954 reset_control_assert(dev->rst); in i2c_dw_prepare_recovery()
963 reset_control_deassert(dev->rst); in i2c_dw_unprepare_recovery()
969 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; in i2c_dw_init_recovery_info()
970 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_init_recovery_info()
973 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); in i2c_dw_init_recovery_info()
977 rinfo->scl_gpiod = gpio; in i2c_dw_init_recovery_info()
979 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); in i2c_dw_init_recovery_info()
982 rinfo->sda_gpiod = gpio; in i2c_dw_init_recovery_info()
984 rinfo->pinctrl = devm_pinctrl_get(dev->dev); in i2c_dw_init_recovery_info()
985 if (IS_ERR(rinfo->pinctrl)) { in i2c_dw_init_recovery_info()
986 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) in i2c_dw_init_recovery_info()
987 return PTR_ERR(rinfo->pinctrl); in i2c_dw_init_recovery_info()
989 rinfo->pinctrl = NULL; in i2c_dw_init_recovery_info()
990 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n"); in i2c_dw_init_recovery_info()
991 } else if (!rinfo->pinctrl) { in i2c_dw_init_recovery_info()
992 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n"); in i2c_dw_init_recovery_info()
995 rinfo->recover_bus = i2c_generic_scl_recovery; in i2c_dw_init_recovery_info()
996 rinfo->prepare_recovery = i2c_dw_prepare_recovery; in i2c_dw_init_recovery_info()
997 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; in i2c_dw_init_recovery_info()
998 adap->bus_recovery_info = rinfo; in i2c_dw_init_recovery_info()
1000 dev_info(dev->dev, "running with GPIO recovery mode! scl%s", in i2c_dw_init_recovery_info()
1001 rinfo->sda_gpiod ? ",sda" : ""); in i2c_dw_init_recovery_info()
1008 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_probe_master()
1013 init_completion(&dev->cmd_complete); in i2c_dw_probe_master()
1015 dev->init = i2c_dw_init_master; in i2c_dw_probe_master()
1040 ret = regmap_read(dev->map, DW_IC_CON, &ic_con); in i2c_dw_probe_master()
1046 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL; in i2c_dw_probe_master()
1048 ret = dev->init(dev); in i2c_dw_probe_master()
1052 if (!adap->name[0]) in i2c_dw_probe_master()
1053 scnprintf(adap->name, sizeof(adap->name), in i2c_dw_probe_master()
1055 adap->retries = 3; in i2c_dw_probe_master()
1056 adap->algo = &i2c_dw_algo; in i2c_dw_probe_master()
1057 adap->quirks = &i2c_dw_quirks; in i2c_dw_probe_master()
1058 adap->dev.parent = dev->dev; in i2c_dw_probe_master()
1061 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { in i2c_dw_probe_master()
1074 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_probe_master()
1075 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, in i2c_dw_probe_master()
1076 irq_flags, dev_name(dev->dev), dev); in i2c_dw_probe_master()
1078 return dev_err_probe(dev->dev, ret, in i2c_dw_probe_master()
1080 dev->irq, ret); in i2c_dw_probe_master()
1093 pm_runtime_get_noresume(dev->dev); in i2c_dw_probe_master()
1096 dev_err(dev->dev, "failure adding adapter: %d\n", ret); in i2c_dw_probe_master()
1097 pm_runtime_put_noidle(dev->dev); in i2c_dw_probe_master()