Lines Matching +full:smbus +full:- +full:timeout +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
11 * - The memory bus only supports 32-bit accesses.
12 * - (only EyeQ5) A register must be configured for the I2C speed mode;
35 #define DRIVER_NAME "nmk-i2c"
74 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
75 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
88 /* Baud-rate counter register (BRCR) */
89 #define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */
90 #define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */
132 * struct i2c_vendor_data - per-vendor variations
162 * struct i2c_nmk_client - client specific data
163 * @slave_adr: 7-bit slave address
178 * struct nmk_i2c_dev - private data structure of the controller.
189 * @timeout_usecs: Slave response timeout
195 * @has_32b_bus: controller is on a bus that only supports 32-bit accesses.
241 if (priv->has_32b_bus) in nmk_i2c_readb()
242 return readl(priv->virtbase + reg); in nmk_i2c_readb()
244 return readb(priv->virtbase + reg); in nmk_i2c_readb()
250 if (priv->has_32b_bus) in nmk_i2c_writeb()
251 writel(val, priv->virtbase + reg); in nmk_i2c_writeb()
253 writeb(val, priv->virtbase + reg); in nmk_i2c_writeb()
257 * flush_i2c_fifo() - This function flushes the I2C FIFO
266 ktime_t timeout; in flush_i2c_fifo() local
276 writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR); in flush_i2c_fifo()
279 timeout = ktime_add_us(ktime_get(), priv->timeout_usecs); in flush_i2c_fifo()
281 while (ktime_after(timeout, ktime_get())) { in flush_i2c_fifo()
282 if ((readl(priv->virtbase + I2C_CR) & in flush_i2c_fifo()
288 dev_err(&priv->adev->dev, in flush_i2c_fifo()
292 return -ETIMEDOUT; in flush_i2c_fifo()
296 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
301 writel(0, priv->virtbase + I2C_IMSCR); in disable_all_interrupts()
305 * clear_all_interrupts() - Clear all interrupts of I2C Controller
310 writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR); in clear_all_interrupts()
314 * init_hw() - initialize the I2C hardware
325 /* disable the controller */ in init_hw()
326 i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE); in init_hw()
332 priv->cli.operation = I2C_NO_OPERATION; in init_hw()
345 * load_i2c_mcr_reg() - load the MCR register
354 mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr); in load_i2c_mcr_reg()
357 /* 10-bit address transaction */ in load_i2c_mcr_reg()
366 priv->cli.slave_adr); in load_i2c_mcr_reg()
370 /* 7-bit address transaction */ in load_i2c_mcr_reg()
378 if (priv->cli.operation == I2C_WRITE) in load_i2c_mcr_reg()
384 if (priv->stop) in load_i2c_mcr_reg()
389 mcr |= FIELD_PREP(I2C_MCR_LENGTH, priv->cli.count); in load_i2c_mcr_reg()
395 * setup_i2c_controller() - setup the controller
405 writel(0x0, priv->virtbase + I2C_CR); in setup_i2c_controller()
406 writel(0x0, priv->virtbase + I2C_HSMCR); in setup_i2c_controller()
407 writel(0x0, priv->virtbase + I2C_TFTR); in setup_i2c_controller()
408 writel(0x0, priv->virtbase + I2C_RFTR); in setup_i2c_controller()
409 writel(0x0, priv->virtbase + I2C_DMAR); in setup_i2c_controller()
411 i2c_clk = clk_get_rate(priv->clk); in setup_i2c_controller()
426 switch (priv->sm) { in setup_i2c_controller()
441 dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu); in setup_i2c_controller()
442 writel(FIELD_PREP(I2C_SCR_SLSU, slsu), priv->virtbase + I2C_SCR); in setup_i2c_controller()
449 div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2; in setup_i2c_controller()
461 brcr = DIV_ROUND_UP(i2c_clk, priv->clk_freq * div); in setup_i2c_controller()
463 if (priv->sm == I2C_FREQ_MODE_HIGH_SPEED) in setup_i2c_controller()
469 writel(brcr, priv->virtbase + I2C_BRCR); in setup_i2c_controller()
472 writel(FIELD_PREP(I2C_CR_SM, priv->sm), priv->virtbase + I2C_CR); in setup_i2c_controller()
475 writel(priv->tft, priv->virtbase + I2C_TFTR); in setup_i2c_controller()
476 writel(priv->rft, priv->virtbase + I2C_RFTR); in setup_i2c_controller()
481 if (priv->timeout_usecs < jiffies_to_usecs(1)) { in nmk_i2c_wait_xfer_done()
482 unsigned long timeout_usecs = priv->timeout_usecs; in nmk_i2c_wait_xfer_done()
483 ktime_t timeout = ktime_set(0, timeout_usecs * NSEC_PER_USEC); in nmk_i2c_wait_xfer_done() local
485 wait_event_hrtimeout(priv->xfer_wq, priv->xfer_done, timeout); in nmk_i2c_wait_xfer_done()
487 unsigned long timeout = usecs_to_jiffies(priv->timeout_usecs); in nmk_i2c_wait_xfer_done() local
489 wait_event_timeout(priv->xfer_wq, priv->xfer_done, timeout); in nmk_i2c_wait_xfer_done()
492 return priv->xfer_done; in nmk_i2c_wait_xfer_done()
496 * read_i2c() - Read from I2C client device
501 * master mode. There is a completion timeout. If there is no transfer
502 * before timeout error is returned.
511 writel(mcr, priv->virtbase + I2C_MCR); in read_i2c()
514 writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, in read_i2c()
515 priv->virtbase + I2C_CR); in read_i2c()
518 i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); in read_i2c()
520 init_waitqueue_head(&priv->xfer_wq); in read_i2c()
521 priv->xfer_done = false; in read_i2c()
527 if (priv->stop || !priv->vendor->has_mtdws) in read_i2c()
534 writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, in read_i2c()
535 priv->virtbase + I2C_IMSCR); in read_i2c()
540 status = -ETIMEDOUT; in read_i2c()
549 for (count = (no_bytes - 2); in fill_tx_fifo()
551 (priv->cli.count != 0); in fill_tx_fifo()
552 count--) { in fill_tx_fifo()
554 nmk_i2c_writeb(priv, *priv->cli.buffer, I2C_TFR); in fill_tx_fifo()
555 priv->cli.buffer++; in fill_tx_fifo()
556 priv->cli.count--; in fill_tx_fifo()
557 priv->cli.xfer_bytes++; in fill_tx_fifo()
563 * write_i2c() - Write data to I2C client.
577 writel(mcr, priv->virtbase + I2C_MCR); in write_i2c()
580 writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, in write_i2c()
581 priv->virtbase + I2C_CR); in write_i2c()
584 i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); in write_i2c()
586 init_waitqueue_head(&priv->xfer_wq); in write_i2c()
587 priv->xfer_done = false; in write_i2c()
595 if (priv->cli.count != 0) in write_i2c()
603 if (priv->stop || !priv->vendor->has_mtdws) in write_i2c()
610 writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, in write_i2c()
611 priv->virtbase + I2C_IMSCR); in write_i2c()
617 dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n", in write_i2c()
618 priv->cli.slave_adr); in write_i2c()
619 status = -ETIMEDOUT; in write_i2c()
626 * nmk_i2c_xfer_one() - transmit a single I2C message
636 priv->cli.operation = I2C_READ; in nmk_i2c_xfer_one()
640 priv->cli.operation = I2C_WRITE; in nmk_i2c_xfer_one()
644 if (status || priv->result) { in nmk_i2c_xfer_one()
648 i2c_sr = readl(priv->virtbase + I2C_SR); in nmk_i2c_xfer_one()
651 dev_err(&priv->adev->dev, "%s\n", in nmk_i2c_xfer_one()
659 status = status ? status : priv->result; in nmk_i2c_xfer_one()
666 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
678 * - a no index is coded as '0',
679 * - 2byte big endian index is coded as '3'
681 * This is compatible with generic messages of smbus emulator
685 * msg[0].addr = client->addr;
690 * msg[1].addr = client->addr;
697 * If you want to emulate an SMBUS write transaction put the
708 * To read or write a block of data (multiple bytes) using SMBUS emulation
720 pm_runtime_get_sync(&priv->adev->dev); in nmk_i2c_xfer()
728 priv->cli.slave_adr = msgs[i].addr; in nmk_i2c_xfer()
729 priv->cli.buffer = msgs[i].buf; in nmk_i2c_xfer()
730 priv->cli.count = msgs[i].len; in nmk_i2c_xfer()
731 priv->stop = (i < (num_msgs - 1)) ? 0 : 1; in nmk_i2c_xfer()
732 priv->result = 0; in nmk_i2c_xfer()
742 pm_runtime_put_sync(&priv->adev->dev); in nmk_i2c_xfer()
752 * disable_interrupts() - disable the interrupts
759 writel(readl(priv->virtbase + I2C_IMSCR) & ~irq, in disable_interrupts()
760 priv->virtbase + I2C_IMSCR); in disable_interrupts()
765 * i2c_irq_handler() - interrupt routine
778 struct device *dev = &priv->adev->dev; in i2c_irq_handler()
784 tft = readl(priv->virtbase + I2C_TFTR); in i2c_irq_handler()
785 rft = readl(priv->virtbase + I2C_RFTR); in i2c_irq_handler()
788 misr = readl(priv->virtbase + I2C_MISR); in i2c_irq_handler()
796 if (priv->cli.operation == I2C_READ) { in i2c_irq_handler()
799 * so disable the Transmit FIFO interrupt in i2c_irq_handler()
803 fill_tx_fifo(priv, (MAX_I2C_FIFO_THRESHOLD - tft)); in i2c_irq_handler()
808 if (priv->cli.count == 0) in i2c_irq_handler()
821 for (count = rft; count > 0; count--) { in i2c_irq_handler()
823 *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR); in i2c_irq_handler()
824 priv->cli.buffer++; in i2c_irq_handler()
826 priv->cli.count -= rft; in i2c_irq_handler()
827 priv->cli.xfer_bytes += rft; in i2c_irq_handler()
832 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { in i2c_irq_handler()
833 *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR); in i2c_irq_handler()
834 priv->cli.buffer++; in i2c_irq_handler()
836 priv->cli.count -= MAX_I2C_FIFO_THRESHOLD; in i2c_irq_handler()
837 priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; in i2c_irq_handler()
843 if (priv->cli.operation == I2C_READ) { in i2c_irq_handler()
844 while (!(readl(priv->virtbase + I2C_RISR) in i2c_irq_handler()
846 if (priv->cli.count == 0) in i2c_irq_handler()
848 *priv->cli.buffer = in i2c_irq_handler()
850 priv->cli.buffer++; in i2c_irq_handler()
851 priv->cli.count--; in i2c_irq_handler()
852 priv->cli.xfer_bytes++; in i2c_irq_handler()
859 if (priv->cli.count) { in i2c_irq_handler()
860 priv->result = -EIO; in i2c_irq_handler()
862 priv->cli.count); in i2c_irq_handler()
865 priv->xfer_done = true; in i2c_irq_handler()
866 wake_up(&priv->xfer_wq); in i2c_irq_handler()
873 priv->result = -EIO; in i2c_irq_handler()
876 i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL); in i2c_irq_handler()
877 priv->xfer_done = true; in i2c_irq_handler()
878 wake_up(&priv->xfer_wq); in i2c_irq_handler()
892 sr = readl(priv->virtbase + I2C_SR); in i2c_irq_handler()
893 priv->result = -EIO; in i2c_irq_handler()
897 i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR); in i2c_irq_handler()
898 priv->xfer_done = true; in i2c_irq_handler()
899 wake_up(&priv->xfer_wq); in i2c_irq_handler()
910 priv->result = -EIO; in i2c_irq_handler()
914 priv->xfer_done = true; in i2c_irq_handler()
915 wake_up(&priv->xfer_wq); in i2c_irq_handler()
920 /* unhandled interrupts by this driver - TODO*/ in i2c_irq_handler()
960 clk_disable_unprepare(priv->clk); in nmk_i2c_runtime_suspend()
971 ret = clk_prepare_enable(priv->clk); in nmk_i2c_runtime_resume()
981 clk_disable_unprepare(priv->clk); in nmk_i2c_runtime_resume()
1009 if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq)) in nmk_i2c_of_probe()
1010 priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ; in nmk_i2c_of_probe()
1012 if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) in nmk_i2c_of_probe()
1013 priv->sm = I2C_FREQ_MODE_STANDARD; in nmk_i2c_of_probe()
1014 else if (priv->clk_freq <= I2C_MAX_FAST_MODE_FREQ) in nmk_i2c_of_probe()
1015 priv->sm = I2C_FREQ_MODE_FAST; in nmk_i2c_of_probe()
1016 else if (priv->clk_freq <= I2C_MAX_FAST_MODE_PLUS_FREQ) in nmk_i2c_of_probe()
1017 priv->sm = I2C_FREQ_MODE_FAST_PLUS; in nmk_i2c_of_probe()
1019 priv->sm = I2C_FREQ_MODE_HIGH_SPEED; in nmk_i2c_of_probe()
1020 priv->tft = 1; /* Tx FIFO threshold */ in nmk_i2c_of_probe()
1021 priv->rft = 8; /* Rx FIFO threshold */ in nmk_i2c_of_probe()
1023 /* Slave response timeout */ in nmk_i2c_of_probe()
1024 if (!of_property_read_u32(np, "i2c-transfer-timeout-us", &timeout_usecs)) in nmk_i2c_of_probe()
1025 priv->timeout_usecs = timeout_usecs; in nmk_i2c_of_probe()
1027 priv->timeout_usecs = 200 * USEC_PER_MSEC; in nmk_i2c_of_probe()
1040 struct device *dev = &priv->adev->dev; in nmk_i2c_eyeq5_probe()
1041 struct device_node *np = dev->of_node; in nmk_i2c_eyeq5_probe()
1050 return -ENOENT; in nmk_i2c_eyeq5_probe()
1052 if (priv->clk_freq <= 400000) in nmk_i2c_eyeq5_probe()
1054 else if (priv->clk_freq <= 1000000) in nmk_i2c_eyeq5_probe()
1071 .compatible = "mobileye,eyeq5-i2c",
1075 .compatible = "mobileye,eyeq6h-i2c",
1083 struct i2c_vendor_data *vendor = id->data; in nmk_i2c_probe()
1084 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; in nmk_i2c_probe()
1085 struct device_node *np = adev->dev.of_node; in nmk_i2c_probe()
1087 struct device *dev = &adev->dev; in nmk_i2c_probe()
1099 match_flags = (unsigned long)match->data; in nmk_i2c_probe()
1103 return -ENOMEM; in nmk_i2c_probe()
1105 priv->vendor = vendor; in nmk_i2c_probe()
1106 priv->adev = adev; in nmk_i2c_probe()
1107 priv->has_32b_bus = match_flags & NMK_I2C_EYEQ_FLAG_32B_BUS; in nmk_i2c_probe()
1116 if (priv->tft > max_fifo_threshold) { in nmk_i2c_probe()
1118 priv->tft, max_fifo_threshold); in nmk_i2c_probe()
1119 priv->tft = max_fifo_threshold; in nmk_i2c_probe()
1122 if (priv->rft > max_fifo_threshold) { in nmk_i2c_probe()
1124 priv->rft, max_fifo_threshold); in nmk_i2c_probe()
1125 priv->rft = max_fifo_threshold; in nmk_i2c_probe()
1130 priv->virtbase = devm_ioremap(dev, adev->res.start, in nmk_i2c_probe()
1131 resource_size(&adev->res)); in nmk_i2c_probe()
1132 if (!priv->virtbase) in nmk_i2c_probe()
1133 return -ENOMEM; in nmk_i2c_probe()
1135 priv->irq = adev->irq[0]; in nmk_i2c_probe()
1136 ret = devm_request_irq(dev, priv->irq, i2c_irq_handler, 0, in nmk_i2c_probe()
1140 "cannot claim the irq %d\n", priv->irq); in nmk_i2c_probe()
1142 priv->clk = devm_clk_get_enabled(dev, NULL); in nmk_i2c_probe()
1143 if (IS_ERR(priv->clk)) in nmk_i2c_probe()
1144 return dev_err_probe(dev, PTR_ERR(priv->clk), in nmk_i2c_probe()
1149 adap = &priv->adap; in nmk_i2c_probe()
1150 adap->dev.of_node = np; in nmk_i2c_probe()
1151 adap->dev.parent = dev; in nmk_i2c_probe()
1152 adap->owner = THIS_MODULE; in nmk_i2c_probe()
1153 adap->class = I2C_CLASS_DEPRECATED; in nmk_i2c_probe()
1154 adap->algo = &nmk_i2c_algo; in nmk_i2c_probe()
1155 adap->timeout = usecs_to_jiffies(priv->timeout_usecs); in nmk_i2c_probe()
1156 snprintf(adap->name, sizeof(adap->name), in nmk_i2c_probe()
1157 "Nomadik I2C at %pR", &adev->res); in nmk_i2c_probe()
1163 adap->name, priv->virtbase); in nmk_i2c_probe()
1178 i2c_del_adapter(&priv->adap); in nmk_i2c_remove()
1182 /* disable the controller */ in nmk_i2c_remove()
1183 i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE); in nmk_i2c_remove()