1ad7d142fSJuergen Fitschen /* SPDX-License-Identifier: GPL-2.0 */
2ad7d142fSJuergen Fitschen /*
3ad7d142fSJuergen Fitschen * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
4ad7d142fSJuergen Fitschen *
5ad7d142fSJuergen Fitschen * Copyright (C) 2011 Weinmann Medical GmbH
6ad7d142fSJuergen Fitschen * Author: Nikolaus Voss <n.voss@weinmann.de>
7ad7d142fSJuergen Fitschen *
8ad7d142fSJuergen Fitschen * Evolved from original work by:
9ad7d142fSJuergen Fitschen * Copyright (C) 2004 Rick Bronson
10ad7d142fSJuergen Fitschen * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
11ad7d142fSJuergen Fitschen *
12ad7d142fSJuergen Fitschen * Borrowed heavily from original work by:
13ad7d142fSJuergen Fitschen * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
14ad7d142fSJuergen Fitschen */
15ad7d142fSJuergen Fitschen
16ad7d142fSJuergen Fitschen #include <linux/clk.h>
17ad7d142fSJuergen Fitschen #include <linux/completion.h>
18ad7d142fSJuergen Fitschen #include <linux/dma-mapping.h>
19ad7d142fSJuergen Fitschen #include <linux/dmaengine.h>
20ad7d142fSJuergen Fitschen #include <linux/i2c.h>
21ad7d142fSJuergen Fitschen #include <linux/platform_device.h>
22ad7d142fSJuergen Fitschen
23ad7d142fSJuergen Fitschen #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
24ad7d142fSJuergen Fitschen #define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
25ad7d142fSJuergen Fitschen #define AUTOSUSPEND_TIMEOUT 2000
26ad7d142fSJuergen Fitschen #define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256
27ad7d142fSJuergen Fitschen
28ad7d142fSJuergen Fitschen /* AT91 TWI register definitions */
29ad7d142fSJuergen Fitschen #define AT91_TWI_CR 0x0000 /* Control Register */
30ad7d142fSJuergen Fitschen #define AT91_TWI_START BIT(0) /* Send a Start Condition */
31ad7d142fSJuergen Fitschen #define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
32ad7d142fSJuergen Fitschen #define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
33ad7d142fSJuergen Fitschen #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
34ad7d142fSJuergen Fitschen #define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
35ad7d142fSJuergen Fitschen #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
36ad7d142fSJuergen Fitschen #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
37ad7d142fSJuergen Fitschen #define AT91_TWI_SWRST BIT(7) /* Software Reset */
38*73371d5fSCodrin Ciubotariu #define AT91_TWI_CLEAR BIT(15) /* Bus clear command */
39ad7d142fSJuergen Fitschen #define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
40ad7d142fSJuergen Fitschen #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
41ad7d142fSJuergen Fitschen #define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
42ad7d142fSJuergen Fitschen #define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
43ad7d142fSJuergen Fitschen #define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
44ad7d142fSJuergen Fitschen #define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
45ad7d142fSJuergen Fitschen #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
46ad7d142fSJuergen Fitschen
47ad7d142fSJuergen Fitschen #define AT91_TWI_MMR 0x0004 /* Master Mode Register */
48ad7d142fSJuergen Fitschen #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
49ad7d142fSJuergen Fitschen #define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
50ad7d142fSJuergen Fitschen
519d3ca54bSJuergen Fitschen #define AT91_TWI_SMR 0x0008 /* Slave Mode Register */
529d3ca54bSJuergen Fitschen #define AT91_TWI_SMR_SADR_MAX 0x007f
539d3ca54bSJuergen Fitschen #define AT91_TWI_SMR_SADR(x) (((x) & AT91_TWI_SMR_SADR_MAX) << 16)
549d3ca54bSJuergen Fitschen
55ad7d142fSJuergen Fitschen #define AT91_TWI_IADR 0x000c /* Internal Address Register */
56ad7d142fSJuergen Fitschen
57ad7d142fSJuergen Fitschen #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
58ad7d142fSJuergen Fitschen #define AT91_TWI_CWGR_HOLD_MAX 0x1f
59ad7d142fSJuergen Fitschen #define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
60ad7d142fSJuergen Fitschen
61ad7d142fSJuergen Fitschen #define AT91_TWI_SR 0x0020 /* Status Register */
62ad7d142fSJuergen Fitschen #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
63ad7d142fSJuergen Fitschen #define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
64ad7d142fSJuergen Fitschen #define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
659d3ca54bSJuergen Fitschen #define AT91_TWI_SVREAD BIT(3) /* Slave Read */
669d3ca54bSJuergen Fitschen #define AT91_TWI_SVACC BIT(4) /* Slave Access */
67ad7d142fSJuergen Fitschen #define AT91_TWI_OVRE BIT(6) /* Overrun Error */
68ad7d142fSJuergen Fitschen #define AT91_TWI_UNRE BIT(7) /* Underrun Error */
69ad7d142fSJuergen Fitschen #define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
709d3ca54bSJuergen Fitschen #define AT91_TWI_EOSACC BIT(11) /* End Of Slave Access */
71ad7d142fSJuergen Fitschen #define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
72*73371d5fSCodrin Ciubotariu #define AT91_TWI_SCL BIT(24) /* TWI SCL status */
73*73371d5fSCodrin Ciubotariu #define AT91_TWI_SDA BIT(25) /* TWI SDA status */
74ad7d142fSJuergen Fitschen
75ad7d142fSJuergen Fitschen #define AT91_TWI_INT_MASK \
769d3ca54bSJuergen Fitschen (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \
779d3ca54bSJuergen Fitschen | AT91_TWI_SVACC | AT91_TWI_EOSACC)
78ad7d142fSJuergen Fitschen
79ad7d142fSJuergen Fitschen #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
80ad7d142fSJuergen Fitschen #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
81ad7d142fSJuergen Fitschen #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
82ad7d142fSJuergen Fitschen #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
83ad7d142fSJuergen Fitschen #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
84ad7d142fSJuergen Fitschen
85ad7d142fSJuergen Fitschen #define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
86*73371d5fSCodrin Ciubotariu #define AT91_TWI_ACR_DATAL_MASK GENMASK(15, 0)
87*73371d5fSCodrin Ciubotariu #define AT91_TWI_ACR_DATAL(len) ((len) & AT91_TWI_ACR_DATAL_MASK)
88ad7d142fSJuergen Fitschen #define AT91_TWI_ACR_DIR BIT(8)
89ad7d142fSJuergen Fitschen
902989b459SEugen Hristev #define AT91_TWI_FILTR 0x0044
912989b459SEugen Hristev #define AT91_TWI_FILTR_FILT BIT(0)
92dda96713SEugen Hristev #define AT91_TWI_FILTR_PADFEN BIT(1)
932be357afSEugen Hristev #define AT91_TWI_FILTR_THRES(v) ((v) << 8)
942be357afSEugen Hristev #define AT91_TWI_FILTR_THRES_MAX 7
952be357afSEugen Hristev #define AT91_TWI_FILTR_THRES_MASK GENMASK(10, 8)
962989b459SEugen Hristev
97ad7d142fSJuergen Fitschen #define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
98ad7d142fSJuergen Fitschen #define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
99ad7d142fSJuergen Fitschen #define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
100ad7d142fSJuergen Fitschen #define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
101ad7d142fSJuergen Fitschen #define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
102ad7d142fSJuergen Fitschen #define AT91_TWI_ONE_DATA 0x0
103ad7d142fSJuergen Fitschen #define AT91_TWI_TWO_DATA 0x1
104ad7d142fSJuergen Fitschen #define AT91_TWI_FOUR_DATA 0x2
105ad7d142fSJuergen Fitschen
106ad7d142fSJuergen Fitschen #define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
107ad7d142fSJuergen Fitschen
108ad7d142fSJuergen Fitschen #define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
109ad7d142fSJuergen Fitschen #define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
110ad7d142fSJuergen Fitschen #define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
111ad7d142fSJuergen Fitschen #define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
112ad7d142fSJuergen Fitschen
113ad7d142fSJuergen Fitschen #define AT91_TWI_VER 0x00fc /* Version Register */
114ad7d142fSJuergen Fitschen
115ad7d142fSJuergen Fitschen struct at91_twi_pdata {
116ad7d142fSJuergen Fitschen unsigned clk_max_div;
117ad7d142fSJuergen Fitschen unsigned clk_offset;
118ad7d142fSJuergen Fitschen bool has_unre_flag;
119ad7d142fSJuergen Fitschen bool has_alt_cmd;
120ad7d142fSJuergen Fitschen bool has_hold_field;
1212989b459SEugen Hristev bool has_dig_filtr;
1222be357afSEugen Hristev bool has_adv_dig_filtr;
123dda96713SEugen Hristev bool has_ana_filtr;
124*73371d5fSCodrin Ciubotariu bool has_clear_cmd;
125ad7d142fSJuergen Fitschen };
126ad7d142fSJuergen Fitschen
127ad7d142fSJuergen Fitschen struct at91_twi_dma {
128ad7d142fSJuergen Fitschen struct dma_chan *chan_rx;
129ad7d142fSJuergen Fitschen struct dma_chan *chan_tx;
130ad7d142fSJuergen Fitschen struct scatterlist sg[2];
131ad7d142fSJuergen Fitschen struct dma_async_tx_descriptor *data_desc;
132ad7d142fSJuergen Fitschen enum dma_data_direction direction;
133ad7d142fSJuergen Fitschen bool buf_mapped;
134ad7d142fSJuergen Fitschen bool xfer_in_progress;
135ad7d142fSJuergen Fitschen };
136ad7d142fSJuergen Fitschen
137ad7d142fSJuergen Fitschen struct at91_twi_dev {
138ad7d142fSJuergen Fitschen struct device *dev;
139ad7d142fSJuergen Fitschen void __iomem *base;
140ad7d142fSJuergen Fitschen struct completion cmd_complete;
141ad7d142fSJuergen Fitschen struct clk *clk;
142ad7d142fSJuergen Fitschen u8 *buf;
143ad7d142fSJuergen Fitschen size_t buf_len;
144ad7d142fSJuergen Fitschen struct i2c_msg *msg;
145ad7d142fSJuergen Fitschen int irq;
146ad7d142fSJuergen Fitschen unsigned imr;
147ad7d142fSJuergen Fitschen unsigned transfer_status;
148ad7d142fSJuergen Fitschen struct i2c_adapter adapter;
149ad7d142fSJuergen Fitschen unsigned twi_cwgr_reg;
150ad7d142fSJuergen Fitschen struct at91_twi_pdata *pdata;
151ad7d142fSJuergen Fitschen bool use_dma;
152ad7d142fSJuergen Fitschen bool use_alt_cmd;
153ad7d142fSJuergen Fitschen bool recv_len_abort;
154ad7d142fSJuergen Fitschen u32 fifo_size;
155ad7d142fSJuergen Fitschen struct at91_twi_dma dma;
1569d3ca54bSJuergen Fitschen bool slave_detected;
157d3d3fdccSKamel Bouhara struct i2c_bus_recovery_info rinfo;
1589d3ca54bSJuergen Fitschen #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
1599d3ca54bSJuergen Fitschen unsigned smr;
1609d3ca54bSJuergen Fitschen struct i2c_client *slave;
1619d3ca54bSJuergen Fitschen #endif
1622989b459SEugen Hristev bool enable_dig_filt;
163dda96713SEugen Hristev bool enable_ana_filt;
1642be357afSEugen Hristev u32 filter_width;
165ad7d142fSJuergen Fitschen };
166ad7d142fSJuergen Fitschen
167ad7d142fSJuergen Fitschen unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg);
168ad7d142fSJuergen Fitschen void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val);
169ad7d142fSJuergen Fitschen void at91_disable_twi_interrupts(struct at91_twi_dev *dev);
170ad7d142fSJuergen Fitschen void at91_twi_irq_save(struct at91_twi_dev *dev);
171ad7d142fSJuergen Fitschen void at91_twi_irq_restore(struct at91_twi_dev *dev);
172ad7d142fSJuergen Fitschen void at91_init_twi_bus(struct at91_twi_dev *dev);
173ad7d142fSJuergen Fitschen
174ad7d142fSJuergen Fitschen void at91_init_twi_bus_master(struct at91_twi_dev *dev);
175ad7d142fSJuergen Fitschen int at91_twi_probe_master(struct platform_device *pdev, u32 phy_addr,
176ad7d142fSJuergen Fitschen struct at91_twi_dev *dev);
1779d3ca54bSJuergen Fitschen
1789d3ca54bSJuergen Fitschen #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
1799d3ca54bSJuergen Fitschen void at91_init_twi_bus_slave(struct at91_twi_dev *dev);
1809d3ca54bSJuergen Fitschen int at91_twi_probe_slave(struct platform_device *pdev, u32 phy_addr,
1819d3ca54bSJuergen Fitschen struct at91_twi_dev *dev);
1829d3ca54bSJuergen Fitschen
1839d3ca54bSJuergen Fitschen #else
at91_init_twi_bus_slave(struct at91_twi_dev * dev)1849d3ca54bSJuergen Fitschen static inline void at91_init_twi_bus_slave(struct at91_twi_dev *dev) {}
at91_twi_probe_slave(struct platform_device * pdev,u32 phy_addr,struct at91_twi_dev * dev)1859d3ca54bSJuergen Fitschen static inline int at91_twi_probe_slave(struct platform_device *pdev,
1869d3ca54bSJuergen Fitschen u32 phy_addr, struct at91_twi_dev *dev)
1879d3ca54bSJuergen Fitschen {
1889d3ca54bSJuergen Fitschen return -EINVAL;
1899d3ca54bSJuergen Fitschen }
1909d3ca54bSJuergen Fitschen
1919d3ca54bSJuergen Fitschen #endif
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