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/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10 - Atish Patra <atishp@rivosinc.com>
13 The SBI PMU extension allows supervisor software to configure, start and
15 capabilities of performance analysis tools, such as perf, if the SBI PMU
20 Without the event to counter mappings, the SBI PMU extension cannot be used.
29 For information on the SBI specification see the section "Performance
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/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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/linux/drivers/cpuidle/
H A Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
26 #include <asm/sbi.h>
53 data->available = true; in sbi_set_domain_state()
54 data->state = state; in sbi_set_domain_state()
61 return data->state; in sbi_get_domain_state()
68 data->available = false; in sbi_clear_domain_state()
75 return data->available; in sbi_is_domain_state_available()
96 u32 *states = data->states; in __sbi_enter_domain_idle_state()
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/linux/drivers/clocksource/
H A Dtimer-riscv.c1 // SPDX-License-Identifier: GPL-2.0
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
11 #define pr_fmt(fmt) "riscv-timer: " fmt
22 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <clocksource/timer-riscv.h>
29 #include <asm/sbi.h>
114 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
115 ce->irq = riscv_clock_event_irq; in riscv_timer_starting_cpu()
117 ce->features |= CLOCK_EVT_FEAT_C3STOP; in riscv_timer_starting_cpu()
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/linux/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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/linux/arch/riscv/kernel/
H A Dsbi-ipi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #define pr_fmt(fmt) "riscv: " fmt
14 #include <asm/sbi.h>
72 * via generic IPI-Mux in sbi_ipi_init()
75 "irqchip/sbi-ipi:starting", in sbi_ipi_init()
79 pr_info("providing IPIs using SBI IPI extension\n"); in sbi_ipi_init()
82 * Use the SBI remote fence extension to avoid in sbi_ipi_init()
H A Dparavirt.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #define pr_fmt(fmt) "riscv-pv: " fmt
15 #include <linux/percpu-defs.h>
23 #include <asm/sbi.h>
42 early_param("no-steal-acc", parse_no_stealacc);
50 pr_info("SBI STA extension detected\n"); in has_pv_steal_clock()
66 pr_warn("Failed to disable steal-time shmem"); in sbi_sta_steal_time_set_shmem()
68 pr_warn("Failed to set steal-time shmem"); in sbi_sta_steal_time_set_shmem()
102 sequence = READ_ONCE(st->sequence); in pv_time_steal_clock()
104 steal = READ_ONCE(st->steal); in pv_time_steal_clock()
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H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/sbi.h>
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
37 return -ENODEV; in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
54 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
56 return -ENODEV; in riscv_early_of_processor_hartid()
62 return -ENODEV; in riscv_early_of_processor_hartid()
66 return -ENODEV; in riscv_early_of_processor_hartid()
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H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <asm/sbi.h>
36 * riscv_get_hart_index() - get hart index for interrupt delivery
38 * @logical_index: index within the "interrupts-extended" property
41 * RISC-V uses term "hart index" for its interrupt controllers, for the
46 * These numbers encoded in the optional property "riscv,hart-indexes"
48 * order as in the "interrupts-extended" property. If this property
50 * "interrupts-extended" property.
57 static const char *prop_hart_index = "riscv,hart-indexes"; in riscv_get_hart_index()
104 /* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
27 #include <asm/sbi.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
43 /* Per-cpu ISA extensions. */
49 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
89 return -EPROBE_DEFER; in riscv_ext_f_depends()
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
97 return -EINVAL; in riscv_ext_zicbom_validate()
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H A Dsys_hwprobe.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * are supported by the hardware. See Documentation/arch/riscv/hwprobe.rst for
16 #include <asm/sbi.h>
30 u64 id = -1ULL; in hwprobe_arch_id()
34 if (pair->key != RISCV_HWPROBE_KEY_MVENDORID && in hwprobe_arch_id()
35 pair->key != RISCV_HWPROBE_KEY_MIMPID && in hwprobe_arch_id()
36 pair->key != RISCV_HWPROBE_KEY_MARCHID) in hwprobe_arch_id()
42 switch (pair->key) { in hwprobe_arch_id()
60 * If there's a mismatch for the given set, return -1 in the in hwprobe_arch_id()
64 id = -1ULL; in hwprobe_arch_id()
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/linux/arch/riscv/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
65 # clang >= 17: https://github.com/llvm/llvm-project/commit/62fa708ceb027713b386c7e0efda994f8bdc27e2
236 # -Zsanitizer=shadow-call-stack flag.
246 depends on $(cc-option,-fpatchable-function-entry=8)
250 def_bool $(cc-option,-fsanitize=shadow-call-stack)
251 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444…
252 depends on $(ld-option,--no-relax-gp)
254 # https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6
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H A DKconfig.errata20 non-standard handling on non-coherent operations on Andes cores.
39 The RISCV MIPS P8700 uses a different opcode for PAUSE.
58 bool "Apply SiFive errata CIP-453"
62 This will apply the SiFive CIP-453 errata to add sign extension
69 bool "Apply SiFive errata CIP-1200"
73 This will apply the SiFive CIP-1200 errata to repalce all
91 caches that are non-coherent with respect to peripheral DMAs.
92 It was designed before the Zicbom extension so needs non-standard
99 bool "T-HEAD errata"
102 All T-HEAD errata Kconfig depend on this Kconfig. Disabling
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/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
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/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <asm/sbi.h>
30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
34 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or in flush_icache_all()
35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
48 * Performs an icache flush for the given MM context. RISC-V has no direct
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
65 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
78 if (mm == current->active_mm && local) { in flush_icache_mm()
82 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
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/linux/arch/riscv/include/asm/
H A Dkvm_host.h1 /* SPDX-License-Identifier: GPL-2.0-only */
91 /* G-stage vmid */
94 /* G-stage page table */
251 /* SBI context */
270 /* Firmware feature SBI extension context */
276 /* SBI steal-time accounting */
285 * arrived in guest context. For riscv, any event that arrives while a vCPU is
/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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/linux/drivers/irqchip/
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
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/linux/Documentation/arch/riscv/
H A Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/linux/drivers/tty/serial/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_SERIAL_CORE) += serial_base.o
7 serial_base-y := serial_core.o serial_base_bus.o serial_ctrl.o serial_port.o
9 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
10 obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o
11 obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
16 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
17 obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
18 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
19 obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
19 comment "Non-8250 serial port support"
78 depends on ARM64 || ARM || RISCV
89 bool "Early console using RISC-V SBI"
95 Support for early debug console using RISC-V SBI. This enables
97 with "earlycon=sbi" on the kernel command line. The console is
101 tristate "BCM1xxx on-chip DUART serial support"
107 the BCM1250 and derived System-On-a-Chip (SOC) devices. Note that
113 the module will be called sb1250-duart.
129 bool "AT91 on-chip serial port support"
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/linux/Documentation/virt/kvm/
H A Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
24 - System ioctls: These query and set global attributes which affect the
28 - VM ioctls: These query and set attributes that affect an entire virtual
35 - vcpu ioctls: These query and set attributes that control the operation
43 - device ioctls: These query and set attributes that control the operation
92 facility that allows backward-compatible extensions to the API to be
133 -----------------------
150 -----------------
189 address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt39 Documentation/arch/m68k/kernel-options.rst.
49 PARISC The PA-RISC architecture is enabled.
60 RISCV RISCV architecture is enabled.
64 the Documentation/scsi/ sub-directory.
83 X86-32 X86-32, aka i386 architecture is enabled.
84 X86-64 X86-64 architecture is enabled.
85 X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64)
94 KNL Is a kernel start-up parameter.
114 force -- enable ACPI if default was off
115 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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