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/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10 - Atish Patra <atishp@rivosinc.com>
13 The SBI PMU extension allows supervisor software to configure, start and
15 capabilities of performance analysis tools, such as perf, if the SBI PMU
20 Without the event to counter mappings, the SBI PMU extension cannot be used.
29 For information on the SBI specification see the section "Performance
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/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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/linux/drivers/cpuidle/
H A Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
25 #include <asm/sbi.h>
53 data->available = true; in sbi_set_domain_state()
54 data->state = state; in sbi_set_domain_state()
61 return data->state; in sbi_get_domain_state()
68 data->available = false; in sbi_clear_domain_state()
75 return data->available; in sbi_is_domain_state_available()
96 u32 *states = data->states; in __sbi_enter_domain_idle_state()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
7 obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
8 obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
9 obj-$(CONFIG_DT_IDLE_GENPD) += dt_idle_genpd.o
10 obj-$(CONFIG_ARCH_HAS_CPU_RELAX) += poll_state.o
11 obj-$(CONFIG_HALTPOLL_CPUIDLE) += cpuidle-haltpoll.o
15 obj-$(CONFIG_ARM_MVEBU_V7_CPUIDLE) += cpuidle-mvebu-v7.o
16 obj-$(CONFIG_ARM_BIG_LITTLE_CPUIDLE) += cpuidle-big_little.o
17 obj-$(CONFIG_ARM_CLPS711X_CPUIDLE) += cpuidle-clps711x.o
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/linux/drivers/clocksource/
H A Dtimer-riscv.c1 // SPDX-License-Identifier: GPL-2.0
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
11 #define pr_fmt(fmt) "riscv-timer: " fmt
22 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <clocksource/timer-riscv.h>
29 #include <asm/sbi.h>
114 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
115 ce->irq = riscv_clock_event_irq; in riscv_timer_starting_cpu()
117 ce->features |= CLOCK_EVT_FEAT_C3STOP; in riscv_timer_starting_cpu()
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/linux/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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/linux/include/linux/perf/
H A Driscv_pmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define RISCV_OP_UNSUPP (-EOPNOTSUPP)
24 #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi"
25 #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy"
48 /* A shadow copy of the counter values to avoid clobbering during multiple SBI calls */
/linux/arch/riscv/kernel/
H A Dsbi-ipi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #define pr_fmt(fmt) "riscv: " fmt
14 #include <asm/sbi.h>
72 * via generic IPI-Mux in sbi_ipi_init()
75 "irqchip/sbi-ipi:starting", in sbi_ipi_init()
79 pr_info("providing IPIs using SBI IPI extension\n"); in sbi_ipi_init()
82 * Use the SBI remote fence extension to avoid in sbi_ipi_init()
H A Dparavirt.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #define pr_fmt(fmt) "riscv-pv: " fmt
15 #include <linux/percpu-defs.h>
23 #include <asm/sbi.h>
42 early_param("no-steal-acc", parse_no_stealacc);
50 pr_info("SBI STA extension detected\n"); in has_pv_steal_clock()
66 pr_warn("Failed to disable steal-time shmem"); in sbi_sta_steal_time_set_shmem()
68 pr_warn("Failed to set steal-time shmem"); in sbi_sta_steal_time_set_shmem()
102 sequence = READ_ONCE(st->sequence); in pv_time_steal_clock()
104 steal = READ_ONCE(st->steal); in pv_time_steal_clock()
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H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/sbi.h>
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
37 return -ENODEV; in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
54 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
56 return -ENODEV; in riscv_early_of_processor_hartid()
62 return -ENODEV; in riscv_early_of_processor_hartid()
67 return -ENODEV; in riscv_early_of_processor_hartid()
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H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
27 #include <asm/sbi.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
41 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
87 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
88 return -EINVAL; in riscv_ext_zicbom_validate()
91 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
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/linux/arch/riscv/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
66 # LLD >= 14: https://github.com/llvm/llvm-project/issues/50505
222 # -Zsanitizer=shadow-call-stack flag.
232 depends on $(cc-option,-fpatchable-function-entry=8)
235 def_bool $(cc-option,-fsanitize=shadow-call-stack)
236 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444…
237 depends on $(ld-option,--no-relax-gp)
241 # https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985
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/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
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H A Driscv_pmu_sbi.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
26 #include <asm/sbi.h>
62 PMU_FORMAT_ATTR(event, "config:0-47");
63 PMU_FORMAT_ATTR(firmware, "config:62-63");
90 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
306 0, cmask, 0, edata->event_idx, 0, 0); in pmu_sbi_check_event()
312 edata->event_idx = -ENOENT; in pmu_sbi_check_event()
342 return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false; in pmu_sbi_ctr_is_fw()
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/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <asm/sbi.h>
35 * Performs an icache flush for the given MM context. RISC-V has no direct
39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
52 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
65 if (mm == current->active_mm && local) { in flush_icache_mm()
69 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
91 if (!test_bit(PG_dcache_clean, &folio->flags)) { in flush_icache_pte()
93 set_bit(PG_dcache_clean, &folio->flags); in flush_icache_pte()
136 /* set block-size for cbom and/or cboz extension if available */ in riscv_init_cbo_blocksizes()
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/linux/arch/riscv/include/asm/
H A Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <asm-generic/tlb.h>
19 if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables)
20 flush_tlb_mm(tlb->mm);
22 flush_tlb_mm_range(tlb->m
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/linux/drivers/irqchip/
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
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/linux/Documentation/arch/riscv/
H A Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/linux/arch/riscv/kvm/
H A Dvcpu_pmu.c1 // SPDX-License-Identifier: GPL-2.0
9 #define pr_fmt(fmt) "riscv-kvm-pmu: " fmt
17 #include <asm/sbi.h>
20 #define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs)
39 u64 counter_val_mask = GENMASK(pmc->cinfo.width, 0); in kvm_pmu_get_sample_period()
42 if (!pmc->counter_val) in kvm_pmu_get_sample_period()
45 sample_period = (-pmc->counter_val) & counter_val_mask; in kvm_pmu_get_sample_period()
80 if (pmc->perf_event) { in kvm_pmu_release_perf_event()
81 perf_event_disable(pmc->perf_event); in kvm_pmu_release_perf_event()
82 perf_event_release_kernel(pmc->perf_event); in kvm_pmu_release_perf_event()
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/linux/Documentation/virt/kvm/
H A Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
24 - System ioctls: These query and set global attributes which affect the
28 - VM ioctls: These query and set attributes that affect an entire virtual
35 - vcpu ioctls: These query and set attributes that control the operation
43 - device ioctls: These query and set attributes that control the operation
92 facility that allows backward-compatible extensions to the API to be
133 -----------------------
150 -----------------
189 address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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