1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <asm/sbi.h>
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
36 /* Per-cpu ISA extensions. */
40  * riscv_isa_extension_base() - Get base extension word
56  * __riscv_isa_extension_available() - Check whether given extension
80 		pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");  in riscv_ext_zicbom_validate()
81 		return -EINVAL;  in riscv_ext_zicbom_validate()
84 		pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");  in riscv_ext_zicbom_validate()
85 		return -EINVAL;  in riscv_ext_zicbom_validate()
94 		pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");  in riscv_ext_zicboz_validate()
95 		return -EINVAL;  in riscv_ext_zicboz_validate()
98 		pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");  in riscv_ext_zicboz_validate()
99 		return -EINVAL;  in riscv_ext_zicboz_validate()
110 	return -EPROBE_DEFER;  in riscv_ext_zca_depends()
119 	return -EPROBE_DEFER;  in riscv_ext_zcd_validate()
126 		return -EINVAL;  in riscv_ext_zcf_validate()
132 	return -EPROBE_DEFER;  in riscv_ext_zcf_validate()
240  * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
251  * - C always implies Zca
252  * - C+F implies Zcf (RV32 only)
253  * - C+D implies Zcd
268  * Ordinarily, for in-kernel data structures, this order is unimportant but
274  * 1. All multi-letter extensions must be separated from other extensions by an
278  *    single-letter extensions and before any higher-privileged extensions.
285  * 3. Standard supervisor-level extensions (starting with 'S') must be listed
286  *    after standard unprivileged extensions.  If multiple supervisor-level
289  * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
290  *    after any lower-privileged, standard extensions.  If multiple
291  *    machine-level extensions are listed, they must be ordered
294  * 5. Non-standard extensions (starting with 'X') must be listed after all
295  *    standard extensions. If multiple non-standard extensions are listed, they
391 	if (ext->id != RISCV_ISA_EXT_INVALID)  in riscv_isa_set_ext()
392 		set_bit(ext->id, bitmap);  in riscv_isa_set_ext()
394 	for (int i = 0; i < ext->subset_ext_size; i++) {  in riscv_isa_set_ext()
395 		if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)  in riscv_isa_set_ext()
396 			set_bit(ext->subset_ext_ids[i], bitmap);  in riscv_isa_set_ext()
429 		if (max_loop_count-- < 0) {  in riscv_resolve_isa()
437 			if (ext && ext->validate) {  in riscv_resolve_isa()
438 				ret = ext->validate(ext, resolved_isa);  in riscv_resolve_isa()
439 				if (ret == -EPROBE_DEFER) {  in riscv_resolve_isa()
465 		if ((name_end - name == strlen(ext->name)) &&  in match_isa_ext()
466 		    !strncasecmp(name, ext->name, name_end - name)) {  in match_isa_ext()
492 				pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");  in riscv_parse_isa_string()
495 			 * As multi-letter extensions must be split from other multi-letter  in riscv_parse_isa_string()
496 			 * extensions with an "_", the end of a multi-letter extension will  in riscv_parse_isa_string()
498 			 * multi-letter extension.  in riscv_parse_isa_string()
506 			 * Workaround for invalid single-letter 's' & 'u' (QEMU).  in riscv_parse_isa_string()
509 			 * multi-letter extension in the ISA string begins with  in riscv_parse_isa_string()
512 			if (ext[-1] != '_' && ext[1] == 'u') {  in riscv_parse_isa_string()
523 			 * As multi-letter extensions must be split from other multi-letter  in riscv_parse_isa_string()
524 			 * extensions with an "_", the end of a multi-letter extension will  in riscv_parse_isa_string()
526 			 * multi-letter extension.  in riscv_parse_isa_string()
537 			 * A simple re-increment solves this problem.  in riscv_parse_isa_string()
547 			if (!isdigit(ext_end[-1]))  in riscv_parse_isa_string()
550 			while (isdigit(*--ext_end))  in riscv_parse_isa_string()
553 			if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {  in riscv_parse_isa_string()
558 			while (isdigit(*--ext_end))  in riscv_parse_isa_string()
565 			 * Things are a little easier for single-letter extensions, as they  in riscv_parse_isa_string()
572 			 * If we are already on a non-digit, there is nothing to do. Either  in riscv_parse_isa_string()
573 			 * we have a multi-letter extension's _, or the start of an  in riscv_parse_isa_string()
597 				--isa;  in riscv_parse_isa_string()
610 		 * on meeting a non-alphanumeric character, an extra increment is needed  in riscv_parse_isa_string()
611 		 * where the succeeding extension is a multi-letter prefixed with an "_".  in riscv_parse_isa_string()
655 			rc = of_property_read_string(node, "riscv,isa", &isa);  in riscv_fill_hwcap_from_isa_string()
658 				pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");  in riscv_fill_hwcap_from_isa_string()
664 				pr_warn("Unable to get ISA for the hart - %d\n", cpu);  in riscv_fill_hwcap_from_isa_string()
673 		 * port & dt-bindings were upstreamed, and so can be set  in riscv_fill_hwcap_from_isa_string()
674 		 * unconditionally where `i` is in riscv,isa on DT systems.  in riscv_fill_hwcap_from_isa_string()
685 		 * just the standard V-1.0 but vendors aren't well behaved.  in riscv_fill_hwcap_from_isa_string()
686 		 * Many vendors with T-Head CPU cores which implement the 0.7.1  in riscv_fill_hwcap_from_isa_string()
688 		 * CPU cores with the ratified spec will contain non-zero  in riscv_fill_hwcap_from_isa_string()
696 		riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);  in riscv_fill_hwcap_from_isa_string()
709 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_isa_string()
711 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_isa_string()
726 		for (int j = 0; j < ext_list->ext_data_count; j++) {  in riscv_fill_cpu_vendor_ext()
727 			const struct riscv_isa_ext_data ext = ext_list->ext_data[j];  in riscv_fill_cpu_vendor_ext()
728 			struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu];  in riscv_fill_cpu_vendor_ext()
730 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",  in riscv_fill_cpu_vendor_ext()
740 					set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);  in riscv_fill_cpu_vendor_ext()
742 			set_bit(ext.id, isavendorinfo->isa);  in riscv_fill_cpu_vendor_ext()
759 		if (!ext_list->is_initialized) {  in riscv_fill_vendor_ext_list()
760 			bitmap_copy(ext_list->all_harts_isa_bitmap.isa,  in riscv_fill_vendor_ext_list()
761 				    ext_list->per_hart_isa_bitmap[cpu].isa,  in riscv_fill_vendor_ext_list()
763 			ext_list->is_initialized = true;  in riscv_fill_vendor_ext_list()
765 			bitmap_and(ext_list->all_harts_isa_bitmap.isa,  in riscv_fill_vendor_ext_list()
766 				   ext_list->all_harts_isa_bitmap.isa,  in riscv_fill_vendor_ext_list()
767 				   ext_list->per_hart_isa_bitmap[cpu].isa,  in riscv_fill_vendor_ext_list()
789 		if (!of_property_present(cpu_node, "riscv,isa-extensions")) {  in riscv_fill_hwcap_from_ext_list()
797 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",  in riscv_fill_hwcap_from_ext_list()
798 						     ext->property) < 0)  in riscv_fill_hwcap_from_ext_list()
804 		riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);  in riscv_fill_hwcap_from_ext_list()
819 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_ext_list()
821 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_ext_list()
827 		return -ENOENT;  in riscv_fill_hwcap_from_ext_list()
850 	isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;  in riscv_fill_hwcap()
851 	isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;  in riscv_fill_hwcap()
852 	isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;  in riscv_fill_hwcap()
853 	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;  in riscv_fill_hwcap()
854 	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;  in riscv_fill_hwcap()
855 	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;  in riscv_fill_hwcap()
856 	isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;  in riscv_fill_hwcap()
864 			pr_info("Falling back to deprecated \"riscv,isa\"\n");  in riscv_fill_hwcap()
899 	pr_info("riscv: base ISA extensions %s\n", print_str);  in riscv_fill_hwcap()
905 	pr_info("riscv: ELF capabilities %s\n", print_str);  in riscv_fill_hwcap()
912 	hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));  in riscv_get_elf_hwcap()
930  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
931  * patch site is for an erratum, identified by the 32-bit patch ID. When
933  * further break down patch ID into two 16-bit numbers. The lower 16 bits
937  * patching on a per-site basis will provide non-zero values and implement
972 		id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);  in riscv_cpufeature_patch_func()
973 		vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);  in riscv_cpufeature_patch_func()
988 			if (alt->vendor_id != 0)  in riscv_cpufeature_patch_func()
994 			value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);  in riscv_cpufeature_patch_func()
999 								    id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE))  in riscv_cpufeature_patch_func()
1010 		patch_text_nosync(oldptr, altptr, alt->alt_len);  in riscv_cpufeature_patch_func()
1011 		riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);  in riscv_cpufeature_patch_func()