Lines Matching +full:riscv +full:- +full:sbi

1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10   RISC-V cores include Control Status Registers (CSRs) which are local to
11   each CPU core (HART in RISC-V terminology) and can be read or written by
16   The RISC-V supervisor ISA manual specifies three interrupt sources that are
19   cores.  The timer interrupt comes from an architecturally mandated real-
20   time timer that is controlled via Supervisor Binary Interface (SBI) calls
22   the HLIC, which are routed via the platform-level interrupt controller
25   All RISC-V systems that conform to the supervisor ISA specification are
34   - Palmer Dabbelt <palmer@dabbelt.com>
35   - Paul Walmsley <paul.walmsley@sifive.com>
40       - items:
41           - const: andestech,cpu-intc
42           - const: riscv,cpu-intc
43       - const: riscv,cpu-intc
45   interrupt-controller: true
47   '#interrupt-cells':
50       The interrupt sources are defined by the RISC-V supervisor ISA manual,
53         - Source 1 is the supervisor software interrupt, which can be sent by
54           an SBI call and is reserved for use by software.
55         - Source 5 is the supervisor timer interrupt, which can be configured
56           by SBI calls and implements a one-shot timer.
57         - Source 9 is the supervisor external interrupt, which chains to all
61   - compatible
62   - '#interrupt-cells'
63   - interrupt-controller
68   - |
69     interrupt-controller {
70         #interrupt-cells = <1>;
71         compatible = "riscv,cpu-intc";
72         interrupt-controller;