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/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
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H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
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H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 - $ref: input.yaml#
16 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
17 additional Hall-effect and inductive sensing capabilities.
24 - azoteq,iqs269a
25 - azoteq,iqs269a-00
26 - azoteq,iqs269a-d0
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/linux/drivers/phy/intel/
H A Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
57 unsigned long rate; in intel_emmc_phy_power() local
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
76 quot = DIV_ROUND_CLOSEST(rate, 50000000); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()
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H A Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
98 /* Check for EMMC clock rate*/ in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
109 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
112 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
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/linux/drivers/clk/rockchip/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
21 #include <linux/clk-provider.h>
348 .rate = _rate##U, \
359 .rate = _rate##U, \
368 .rate = _rate##U, \
377 .rate = _rate##U, \
385 * struct rockchip_clk_provider - information about clock provider
388 * @cru_node: device-node of the clock-provider
389 * @grf: regmap of the general-register-files syscon
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/linux/sound/soc/codecs/
H A Dsta350.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system
34 #include <sound/soc-dapm.h>
54 /* Power-up register defaults */
155 "vdd-dig", /* digital supply, 3.3V */
156 "vdd-pll", /* pll supply, 3.3V */
157 "vcc" /* power amp supply, 5V - 26V */
178 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12750, 50, 1);
179 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
180 static const DECLARE_TLV_DB_SCALE(tone_tlv, -1200, 200, 0);
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H A Dsta32x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
34 #include <sound/soc-dapm.h>
54 /* Power-up register defaults */
132 "Vcc" /* power amp spply, 10V - 36V */
153 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
154 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
155 static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
158 "Anti-Clipping", "Dynamic Range Compression" };
169 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
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H A Dak4642.c1 // SPDX-License-Identifier: GPL-2.0
3 // ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
23 #include <linux/clk-provider.h>
85 #define MS (1 << 3) /* master/slave select */ macro
102 #define LOPS (1 << 6) /* Stero Line-out Power Save Mode */
153 * min : 0xFE : -115.0 dB
156 static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
177 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in ak4642_lout_event()
280 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in ak4642_dai_startup()
281 struct snd_soc_component *component = dai->component; in ak4642_dai_startup()
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H A Dcs42l56.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l56.c -- CS42L56 ALSA SoC audio driver
29 #include <sound/soc-dapm.h>
63 { 3, 0x7f }, /* r03 - Power Ctl 1 */
64 { 4, 0xff }, /* r04 - Power Ctl 2 */
65 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
66 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */
67 { 7, 0x00 }, /* r07 - Serial Format */
68 { 8, 0x05 }, /* r08 - Class H Ctl */
69 { 9, 0x0c }, /* r09 - Misc Ctl */
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H A Dda7218.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7218.c - DA7218 ALSA SoC Codec Driver
22 #include <sound/soc-dapm.h>
37 static const DECLARE_TLV_DB_SCALE(da7218_mic_gain_tlv, -600, 600, 0);
38 static const DECLARE_TLV_DB_SCALE(da7218_mixin_gain_tlv, -450, 150, 0);
39 static const DECLARE_TLV_DB_SCALE(da7218_in_dig_gain_tlv, -8325, 75, 0);
40 static const DECLARE_TLV_DB_SCALE(da7218_ags_trigger_tlv, -9000, 600, 0);
42 static const DECLARE_TLV_DB_SCALE(da7218_alc_threshold_tlv, -9450, 150, 0);
47 static const DECLARE_TLV_DB_SCALE(da7218_dmix_gain_tlv, -4200, 150, 0);
50 static const DECLARE_TLV_DB_SCALE(da7218_dgs_trigger_tlv, -9450, 150, 0);
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H A Dtlv320aic3x.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * ---------------------------------------
17 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
18 * | IN1L -> LINE1L
19 * | IN1R -> LINE1R
20 * | IN2L -> LINE2L
21 * | IN2R -> LINE2R
22 * | MIC3L/R -> N/A
25 * ---------------------------------------
89 /* Output Common-Mode Voltage */
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H A Dwcd939x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
26 #include <sound/soc-dapm.h>
31 #include "wcd-clsh-v2.h"
32 #include "wcd-mbhc-v2.h"
217 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
307 int rate; in wcd939x_get_clk_rate() local
311 rate = SWR_CLK_RATE_0P6MHZ; in wcd939x_get_clk_rate()
314 rate = SWR_CLK_RATE_1P2MHZ; in wcd939x_get_clk_rate()
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H A Dcs35l36.c1 // SPDX-License-Identifier: GPL-2.0
3 // cs35l36.c -- CS35L36 ALSA SoC audio driver
27 #include <sound/soc-dapm.h>
446 TLV_DB_MINMAX_ITEM(-10200, 1200));
450 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
463 ucontrol->value.integer.value[0] = cs35l36->ldm_mode_sel; in cs35l36_ldm_sel_get()
475 int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK : in cs35l36_ldm_sel_put()
478 cs35l36->ldm_mode_sel = val; in cs35l36_ldm_sel_put()
480 regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG, in cs35l36_ldm_sel_put()
492 SOC_SINGLE("Amp Gain Zero-Cross Switch", CS35L36_AMP_GAIN_CTRL,
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H A Darizona.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arizona.c - Wolfson Arizona class device shared support
67 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
69 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
71 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
74 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
76 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
78 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
84 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in arizona_spk_ev()
85 struct arizona *arizona = dev_get_drvdata(component->dev->parent); in arizona_spk_ev()
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H A Dwcd938x.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
21 #include <sound/soc-dapm.h>
24 #include "wcd-clsh-v2.h"
25 #include "wcd-mbhc-v2.h"
193 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
194 static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, 0);
295 int rate; in wcd938x_get_clk_rate() local
299 rate = SWR_CLK_RATE_0P6MHZ; in wcd938x_get_clk_rate()
302 rate = SWR_CLK_RATE_1P2MHZ; in wcd938x_get_clk_rate()
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H A Dwm8903.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8903.c -- WM8903 ALSA SoC Audio driver
5 * Copyright 2008-12 Wolfson Microelectronics
6 * Copyright 2011-2012 NVIDIA, Inc.
11 * - TDM mode configuration.
41 { 4, 0x0018 }, /* R4 - Bias Control 0 */
42 { 5, 0x0000 }, /* R5 - VMID Control 0 */
43 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
44 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
45 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
[all …]
H A Dpcm512x.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <sound/soc-dapm.h>
66 regcache_mark_dirty(pcm512x->regmap); \
67 regcache_cache_only(pcm512x->regmap, true); \
230 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; in pcm512x_overclock_pll_get()
245 return -EBUSY; in pcm512x_overclock_pll_put()
248 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; in pcm512x_overclock_pll_put()
258 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; in pcm512x_overclock_dsp_get()
273 return -EBUSY; in pcm512x_overclock_dsp_put()
276 pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; in pcm512x_overclock_dsp_put()
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/linux/drivers/watchdog/
H A Dqcom-wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
49 unsigned long rate; member
56 return wdt->base + wdt->layout[reg]; in wdt_addr()
77 unsigned int bark = wdd->timeout - wdd->pretimeout; in qcom_wdt_start()
81 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); in qcom_wdt_start()
82 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); in qcom_wdt_start()
106 wdd->timeout = timeout; in qcom_wdt_set_timeout()
113 wdd->pretimeout = timeout; in qcom_wdt_set_pretimeout()
125 * Setup BITE_TIME to be 128ms, and enable WDT. in qcom_wdt_restart()
127 timeout = 128 * wdt->rate / 1000; in qcom_wdt_restart()
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H A Dstm32_iwdg.c1 // SPDX-License-Identifier: GPL-2.0
32 #define IWDG_EWCR 0x14 /* Early Wake-up Register */
84 unsigned int rate; member
103 dev_dbg(wdd->parent, "%s\n", __func__); in stm32_iwdg_start()
105 if (!wdd->pretimeout) in stm32_iwdg_start()
106 wdd->pretimeout = 3 * wdd->timeout / 4; in stm32_iwdg_start()
108 tout = clamp_t(unsigned int, wdd->timeout, in stm32_iwdg_start()
109 wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000); in stm32_iwdg_start()
110 ptot = clamp_t(unsigned int, tout - wdd->pretimeout, in stm32_iwdg_start()
111 wdd->min_timeout, tout); in stm32_iwdg_start()
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/linux/sound/soc/stm/
H A Dstm32_sai_sub.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata))
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/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
20 #include <linux/clk-provider.h>
201 .parent_names = (const char *[]){ "TBG-A-P", \
202 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
211 .parent_names = (const char *[]){ "TBG-A-P", \
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/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
/linux/drivers/input/misc/
H A Diqs626a.c1 // SPDX-License-Identifier: GPL-2.0+
8 * inductive keys as well as Hall-effect switches, and one for a trackpad that
227 .name = "event-prox",
233 .name = "event-prox-alt",
240 .name = "event-touch",
246 .name = "event-touch-alt",
253 .name = "event-deep",
259 .name = "event-deep-alt",
367 .name = "ulp-0",
378 .name = "trackpad-3x2",
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