Lines Matching +full:rate +full:- +full:np +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata))
68 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
82 * @id: SAI sub block id corresponding to sub-block A or B
89 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
100 * @set_sai_ck_rate: set SAI kernel clock rate
101 * @put_sai_ck_rate: put SAI kernel clock rate
135 int (*set_sai_ck_rate)(struct stm32_sai_sub_data *sai, unsigned int rate);
201 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_up()
205 ret = regmap_update_bits(sai->regmap, reg, mask, val); in stm32_sai_sub_reg_up()
207 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_up()
218 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_wr()
222 ret = regmap_write_bits(sai->regmap, reg, mask, val); in stm32_sai_sub_reg_wr()
224 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_wr()
234 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_reg_rd()
238 ret = regmap_read(sai->regmap, reg, val); in stm32_sai_sub_reg_rd()
240 clk_disable(sai->pdata->pclk); in stm32_sai_sub_reg_rd()
272 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in snd_pcm_iec958_info()
273 uinfo->count = 1; in snd_pcm_iec958_info()
283 mutex_lock(&sai->ctrl_lock); in snd_pcm_iec958_get()
284 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); in snd_pcm_iec958_get()
285 mutex_unlock(&sai->ctrl_lock); in snd_pcm_iec958_get()
295 mutex_lock(&sai->ctrl_lock); in snd_pcm_iec958_put()
296 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); in snd_pcm_iec958_put()
297 mutex_unlock(&sai->ctrl_lock); in snd_pcm_iec958_put()
325 int version = sai->pdata->conf.version; in stm32_sai_get_clk_div()
330 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); in stm32_sai_get_clk_div()
331 return -EINVAL; in stm32_sai_get_clk_div()
333 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); in stm32_sai_get_clk_div()
336 dev_dbg(&sai->pdev->dev, in stm32_sai_get_clk_div()
337 "Rate not accurate. requested (%ld), actual (%ld)\n", in stm32_sai_get_clk_div()
346 int version = sai->pdata->conf.version; in stm32_sai_set_clk_div()
350 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); in stm32_sai_set_clk_div()
351 return -EINVAL; in stm32_sai_set_clk_div()
358 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); in stm32_sai_set_clk_div()
363 static bool stm32_sai_rate_accurate(unsigned int max_rate, unsigned int rate) in stm32_sai_rate_accurate() argument
368 ratio = DIV_ROUND_CLOSEST(max_rate, rate); in stm32_sai_rate_accurate()
372 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate))); in stm32_sai_rate_accurate()
382 unsigned int rate) in stm32_sai_set_parent_clk() argument
384 struct platform_device *pdev = sai->pdev; in stm32_sai_set_parent_clk()
385 struct clk *parent_clk = sai->pdata->clk_x8k; in stm32_sai_set_parent_clk()
388 if (!(rate % SAI_RATE_11K)) in stm32_sai_set_parent_clk()
389 parent_clk = sai->pdata->clk_x11k; in stm32_sai_set_parent_clk()
391 ret = clk_set_parent(sai->sai_ck, parent_clk); in stm32_sai_set_parent_clk()
393 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", in stm32_sai_set_parent_clk()
394 ret, ret == -EBUSY ? in stm32_sai_set_parent_clk()
402 if (sai->sai_ck_used) { in stm32_sai_put_parent_rate()
403 sai->sai_ck_used = false; in stm32_sai_put_parent_rate()
404 clk_rate_exclusive_put(sai->sai_ck); in stm32_sai_put_parent_rate()
409 unsigned int rate) in stm32_sai_set_parent_rate() argument
411 struct platform_device *pdev = sai->pdev; in stm32_sai_set_parent_rate()
417 * - mclk on or spdif: in stm32_sai_set_parent_rate()
418 * f_sai_ck = MCKDIV * mclk-fs * fs in stm32_sai_set_parent_rate()
419 * Here typical 256 ratio is assumed for mclk-fs in stm32_sai_set_parent_rate()
420 * - mclk off: in stm32_sai_set_parent_rate()
426 if (!(rate % SAI_RATE_11K)) in stm32_sai_set_parent_rate()
431 if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai)) in stm32_sai_set_parent_rate()
432 sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length)); in stm32_sai_set_parent_rate()
435 * Request exclusivity, as the clock is shared by SAI sub-blocks and by in stm32_sai_set_parent_rate()
436 * some SAI instances. This allows to ensure that the rate cannot be in stm32_sai_set_parent_rate()
439 clk_rate_exclusive_get(sai->sai_ck); in stm32_sai_set_parent_rate()
440 sai->sai_ck_used = true; in stm32_sai_set_parent_rate()
443 * Check current kernel clock rate. If it gives the expected accuracy in stm32_sai_set_parent_rate()
446 sai_curr_rate = clk_get_rate(sai->sai_ck); in stm32_sai_set_parent_rate()
451 * Otherwise try to set the maximum rate and check the new actual rate. in stm32_sai_set_parent_rate()
452 * If the new rate does not give the expected accuracy, try to set in stm32_sai_set_parent_rate()
458 /* Check new rate accuracy. Return if ok */ in stm32_sai_set_parent_rate()
459 sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate); in stm32_sai_set_parent_rate()
461 ret = clk_set_rate(sai->sai_ck, sai_ck_rate); in stm32_sai_set_parent_rate()
463 dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s", in stm32_sai_set_parent_rate()
464 ret, ret == -EBUSY ? in stm32_sai_set_parent_rate()
475 } while (sai_ck_rate > rate); in stm32_sai_set_parent_rate()
477 /* No accurate rate found */ in stm32_sai_set_parent_rate()
478 dev_err(&pdev->dev, "Failed to find an accurate rate"); in stm32_sai_set_parent_rate()
483 return -EINVAL; in stm32_sai_set_parent_rate()
486 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, in stm32_sai_mclk_round_rate() argument
490 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_round_rate()
493 div = stm32_sai_get_clk_div(sai, *prate, rate); in stm32_sai_mclk_round_rate()
495 return -EINVAL; in stm32_sai_mclk_round_rate()
497 mclk->freq = *prate / div; in stm32_sai_mclk_round_rate()
499 return mclk->freq; in stm32_sai_mclk_round_rate()
507 return mclk->freq; in stm32_sai_mclk_recalc_rate()
510 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, in stm32_sai_mclk_set_rate() argument
514 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_set_rate()
517 div = stm32_sai_get_clk_div(sai, parent_rate, rate); in stm32_sai_mclk_set_rate()
525 mclk->freq = rate; in stm32_sai_mclk_set_rate()
533 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_enable()
535 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); in stm32_sai_mclk_enable()
544 struct stm32_sai_sub_data *sai = mclk->sai_data; in stm32_sai_mclk_disable()
546 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); in stm32_sai_mclk_disable()
563 struct device *dev = &sai->pdev->dev; in stm32_sai_add_mclk_provider()
564 const char *pname = __clk_get_name(sai->sai_ck); in stm32_sai_add_mclk_provider()
570 return -ENOMEM; in stm32_sai_add_mclk_provider()
575 return -ENOMEM; in stm32_sai_add_mclk_provider()
582 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { in stm32_sai_add_mclk_provider()
588 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); in stm32_sai_add_mclk_provider()
589 mclk->sai_data = sai; in stm32_sai_add_mclk_provider()
590 hw = &mclk->hw; in stm32_sai_add_mclk_provider()
593 ret = devm_clk_hw_register(&sai->pdev->dev, hw); in stm32_sai_add_mclk_provider()
598 sai->sai_mclk = hw->clk; in stm32_sai_add_mclk_provider()
607 struct platform_device *pdev = sai->pdev; in stm32_sai_isr()
621 if (!sai->substream) { in stm32_sai_isr()
622 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); in stm32_sai_isr()
627 dev_err(&pdev->dev, "IRQ %s\n", in stm32_sai_isr()
633 dev_dbg(&pdev->dev, "IRQ mute detected\n"); in stm32_sai_isr()
636 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); in stm32_sai_isr()
641 dev_err(&pdev->dev, "IRQ Codec not ready\n"); in stm32_sai_isr()
644 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); in stm32_sai_isr()
649 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); in stm32_sai_isr()
653 spin_lock(&sai->irq_lock); in stm32_sai_isr()
654 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) in stm32_sai_isr()
655 snd_pcm_stop_xrun(sai->substream); in stm32_sai_isr()
656 spin_unlock(&sai->irq_lock); in stm32_sai_isr()
667 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { in stm32_sai_set_sysclk()
676 /* Release mclk rate only if rate was actually set */ in stm32_sai_set_sysclk()
677 if (sai->mclk_rate) { in stm32_sai_set_sysclk()
678 clk_rate_exclusive_put(sai->sai_mclk); in stm32_sai_set_sysclk()
679 sai->mclk_rate = 0; in stm32_sai_set_sysclk()
682 if (sai->put_sai_ck_rate) in stm32_sai_set_sysclk()
683 sai->put_sai_ck_rate(sai); in stm32_sai_set_sysclk()
689 ret = sai->set_sai_ck_rate(sai, freq); in stm32_sai_set_sysclk()
693 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); in stm32_sai_set_sysclk()
695 dev_err(cpu_dai->dev, in stm32_sai_set_sysclk()
696 ret == -EBUSY ? in stm32_sai_set_sysclk()
698 "Could not set mclk rate\n"); in stm32_sai_set_sysclk()
702 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); in stm32_sai_set_sysclk()
703 sai->mclk_rate = freq; in stm32_sai_set_sysclk()
716 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); in stm32_sai_set_dai_tdm_slot()
720 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", in stm32_sai_set_dai_tdm_slot()
736 SAI_XSLOTR_NBSLOT_SET(slots - 1); in stm32_sai_set_dai_tdm_slot()
741 sai->slot_mask = tx_mask; in stm32_sai_set_dai_tdm_slot()
746 sai->slot_mask = rx_mask; in stm32_sai_set_dai_tdm_slot()
754 sai->slot_width = slot_width; in stm32_sai_set_dai_tdm_slot()
755 sai->slots = slots; in stm32_sai_set_dai_tdm_slot()
767 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); in stm32_sai_set_dai_fmt()
802 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", in stm32_sai_set_dai_fmt()
804 return -EINVAL; in stm32_sai_set_dai_fmt()
827 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", in stm32_sai_set_dai_fmt()
829 return -EINVAL; in stm32_sai_set_dai_fmt()
841 sai->master = false; in stm32_sai_set_dai_fmt()
844 sai->master = true; in stm32_sai_set_dai_fmt()
847 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", in stm32_sai_set_dai_fmt()
849 return -EINVAL; in stm32_sai_set_dai_fmt()
852 /* Set slave mode if sub-block is synchronized with another SAI */ in stm32_sai_set_dai_fmt()
853 if (sai->sync) { in stm32_sai_set_dai_fmt()
854 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); in stm32_sai_set_dai_fmt()
856 sai->master = false; in stm32_sai_set_dai_fmt()
864 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_set_dai_fmt()
868 sai->fmt = fmt; in stm32_sai_set_dai_fmt()
880 spin_lock_irqsave(&sai->irq_lock, flags); in stm32_sai_startup()
881 sai->substream = substream; in stm32_sai_startup()
882 spin_unlock_irqrestore(&sai->irq_lock, flags); in stm32_sai_startup()
885 snd_pcm_hw_constraint_mask64(substream->runtime, in stm32_sai_startup()
888 snd_pcm_hw_constraint_single(substream->runtime, in stm32_sai_startup()
892 ret = clk_prepare_enable(sai->sai_ck); in stm32_sai_startup()
894 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); in stm32_sai_startup()
909 if (sai->master) in stm32_sai_startup()
939 sai->spdif_frm_cnt = 0; in stm32_sai_set_config()
956 dev_err(cpu_dai->dev, "Data format not supported\n"); in stm32_sai_set_config()
957 return -EINVAL; in stm32_sai_set_config()
961 if ((sai->slots == 2) && (params_channels(params) == 1)) in stm32_sai_set_config()
966 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_set_config()
986 sai->slot_width = sai->data_size; in stm32_sai_set_slots()
988 if (sai->slot_width < sai->data_size) { in stm32_sai_set_slots()
989 dev_err(cpu_dai->dev, in stm32_sai_set_slots()
991 sai->data_size); in stm32_sai_set_slots()
992 return -EINVAL; in stm32_sai_set_slots()
996 if (!sai->slots) in stm32_sai_set_slots()
997 sai->slots = 2; in stm32_sai_set_slots()
1002 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); in stm32_sai_set_slots()
1006 sai->slot_mask = (1 << sai->slots) - 1; in stm32_sai_set_slots()
1009 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); in stm32_sai_set_slots()
1012 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", in stm32_sai_set_slots()
1013 sai->slots, sai->slot_width); in stm32_sai_set_slots()
1024 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; in stm32_sai_set_frame()
1025 sai->fs_length = sai->slot_width * sai->slots; in stm32_sai_set_frame()
1027 fs_active = sai->fs_length / 2; in stm32_sai_set_frame()
1032 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); in stm32_sai_set_frame()
1033 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); in stm32_sai_set_frame()
1036 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", in stm32_sai_set_frame()
1037 sai->fs_length, fs_active); in stm32_sai_set_frame()
1041 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { in stm32_sai_set_frame()
1042 offset = sai->slot_width - sai->data_size; in stm32_sai_set_frame()
1052 unsigned char *cs = sai->iec958.status; in stm32_sai_init_iec958_status()
1066 /* Force the sample rate according to runtime rate */ in stm32_sai_set_iec958_status()
1067 mutex_lock(&sai->ctrl_lock); in stm32_sai_set_iec958_status()
1068 switch (runtime->rate) { in stm32_sai_set_iec958_status()
1070 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; in stm32_sai_set_iec958_status()
1073 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; in stm32_sai_set_iec958_status()
1076 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; in stm32_sai_set_iec958_status()
1079 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; in stm32_sai_set_iec958_status()
1082 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; in stm32_sai_set_iec958_status()
1085 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; in stm32_sai_set_iec958_status()
1088 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; in stm32_sai_set_iec958_status()
1091 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; in stm32_sai_set_iec958_status()
1094 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; in stm32_sai_set_iec958_status()
1097 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; in stm32_sai_set_iec958_status()
1100 mutex_unlock(&sai->ctrl_lock); in stm32_sai_set_iec958_status()
1109 unsigned int rate = params_rate(params); in stm32_sai_configure_clock() local
1112 if (!sai->sai_mclk) { in stm32_sai_configure_clock()
1113 ret = sai->set_sai_ck_rate(sai, rate); in stm32_sai_configure_clock()
1117 sai_clk_rate = clk_get_rate(sai->sai_ck); in stm32_sai_configure_clock()
1119 if (STM_SAI_IS_F4(sai->pdata)) { in stm32_sai_configure_clock()
1127 if (!sai->mclk_rate) in stm32_sai_configure_clock()
1130 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { in stm32_sai_configure_clock()
1132 2 * sai->mclk_rate); in stm32_sai_configure_clock()
1148 rate * 128); in stm32_sai_configure_clock()
1152 if (sai->mclk_rate) { in stm32_sai_configure_clock()
1153 mclk_ratio = sai->mclk_rate / rate; in stm32_sai_configure_clock()
1157 dev_err(cpu_dai->dev, in stm32_sai_configure_clock()
1160 return -EINVAL; in stm32_sai_configure_clock()
1168 sai->mclk_rate); in stm32_sai_configure_clock()
1172 /* mclk-fs not set, master clock not active */ in stm32_sai_configure_clock()
1173 den = sai->fs_length * params_rate(params); in stm32_sai_configure_clock()
1192 sai->data_size = params_width(params); in stm32_sai_hw_params()
1195 /* Rate not already set in runtime structure */ in stm32_sai_hw_params()
1196 substream->runtime->rate = params_rate(params); in stm32_sai_hw_params()
1197 stm32_sai_set_iec958_status(sai, substream->runtime); in stm32_sai_hw_params()
1209 if (sai->master) in stm32_sai_hw_params()
1225 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); in stm32_sai_trigger()
1234 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_trigger()
1239 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); in stm32_sai_trigger()
1252 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); in stm32_sai_trigger()
1255 sai->spdif_frm_cnt = 0; in stm32_sai_trigger()
1258 return -EINVAL; in stm32_sai_trigger()
1272 clk_disable_unprepare(sai->sai_ck); in stm32_sai_shutdown()
1276 * - Master clock is not used. Kernel clock won't be released trough sysclk in stm32_sai_shutdown()
1277 * - Put handler is defined. Involve that clock is managed exclusively in stm32_sai_shutdown()
1279 if (!sai->sai_mclk && sai->put_sai_ck_rate) in stm32_sai_shutdown()
1280 sai->put_sai_ck_rate(sai); in stm32_sai_shutdown()
1282 spin_lock_irqsave(&sai->irq_lock, flags); in stm32_sai_shutdown()
1283 sai->substream = NULL; in stm32_sai_shutdown()
1284 spin_unlock_irqrestore(&sai->irq_lock, flags); in stm32_sai_shutdown()
1290 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_pcm_new()
1294 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); in stm32_sai_pcm_new()
1295 knew.device = rtd->pcm->device; in stm32_sai_pcm_new()
1296 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); in stm32_sai_pcm_new()
1304 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_dai_probe()
1307 sai->cpu_dai = cpu_dai; in stm32_sai_dai_probe()
1309 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); in stm32_sai_dai_probe()
1312 * as it allows bytes, half-word and words transfers. (See DMA fifos in stm32_sai_dai_probe()
1315 sai->dma_params.maxburst = 4; in stm32_sai_dai_probe()
1316 if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst) in stm32_sai_dai_probe()
1317 sai->dma_params.maxburst = 1; in stm32_sai_dai_probe()
1319 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; in stm32_sai_dai_probe()
1322 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); in stm32_sai_dai_probe()
1324 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); in stm32_sai_dai_probe()
1335 if (sai->sync == SAI_SYNC_EXTERNAL) { in stm32_sai_dai_probe()
1337 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, in stm32_sai_dai_probe()
1338 sai->synco, sai->synci); in stm32_sai_dai_probe()
1344 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); in stm32_sai_dai_probe()
1376 struct snd_pcm_runtime *runtime = substream->runtime; in stm32_sai_pcm_process_spdif()
1379 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); in stm32_sai_pcm_process_spdif()
1380 int *ptr = (int *)(runtime->dma_area + hwoff + in stm32_sai_pcm_process_spdif()
1381 channel * (runtime->dma_bytes / runtime->channels)); in stm32_sai_pcm_process_spdif()
1383 unsigned int frm_cnt = sai->spdif_frm_cnt; in stm32_sai_pcm_process_spdif()
1392 mask = 1 << (frm_cnt - (byte << 3)); in stm32_sai_pcm_process_spdif()
1393 if (sai->iec958.status[byte] & mask) in stm32_sai_pcm_process_spdif()
1402 } while (--cnt); in stm32_sai_pcm_process_spdif()
1403 sai->spdif_frm_cnt = frm_cnt; in stm32_sai_pcm_process_spdif()
1421 .period_bytes_min = 1024, /* 5ms at 48kHz */
1473 .name = "stm32-sai",
1478 { .compatible = "st,stm32-sai-sub-a",
1480 { .compatible = "st,stm32-sai-sub-b",
1489 struct device_node *np = pdev->dev.of_node; in stm32_sai_sub_parse_of() local
1495 if (!np) in stm32_sai_sub_parse_of()
1496 return -ENODEV; in stm32_sai_sub_parse_of()
1502 sai->phys_addr = res->start; in stm32_sai_sub_parse_of()
1504 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; in stm32_sai_sub_parse_of()
1505 /* Note: PDM registers not available for sub-block B */ in stm32_sai_sub_parse_of()
1507 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; in stm32_sai_sub_parse_of()
1514 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, in stm32_sai_sub_parse_of()
1515 sai->regmap_config); in stm32_sai_sub_parse_of()
1516 if (IS_ERR(sai->regmap)) in stm32_sai_sub_parse_of()
1517 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), in stm32_sai_sub_parse_of()
1521 if (of_property_match_string(np, "dma-names", "tx") >= 0) { in stm32_sai_sub_parse_of()
1522 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; in stm32_sai_sub_parse_of()
1523 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { in stm32_sai_sub_parse_of()
1524 sai->dir = SNDRV_PCM_STREAM_CAPTURE; in stm32_sai_sub_parse_of()
1526 dev_err(&pdev->dev, "Unsupported direction\n"); in stm32_sai_sub_parse_of()
1527 return -EINVAL; in stm32_sai_sub_parse_of()
1531 sai->spdif = false; in stm32_sai_sub_parse_of()
1532 if (of_property_present(np, "st,iec60958")) { in stm32_sai_sub_parse_of()
1534 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { in stm32_sai_sub_parse_of()
1535 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); in stm32_sai_sub_parse_of()
1536 return -EINVAL; in stm32_sai_sub_parse_of()
1539 sai->spdif = true; in stm32_sai_sub_parse_of()
1540 sai->master = true; in stm32_sai_sub_parse_of()
1544 args.np = NULL; in stm32_sai_sub_parse_of()
1545 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); in stm32_sai_sub_parse_of()
1546 if (ret < 0 && ret != -ENOENT) { in stm32_sai_sub_parse_of()
1547 dev_err(&pdev->dev, "Failed to get st,sync property\n"); in stm32_sai_sub_parse_of()
1551 sai->sync = SAI_SYNC_NONE; in stm32_sai_sub_parse_of()
1552 if (args.np) { in stm32_sai_sub_parse_of()
1553 if (args.np == np) { in stm32_sai_sub_parse_of()
1554 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); in stm32_sai_sub_parse_of()
1555 of_node_put(args.np); in stm32_sai_sub_parse_of()
1556 return -EINVAL; in stm32_sai_sub_parse_of()
1559 sai->np_sync_provider = of_get_parent(args.np); in stm32_sai_sub_parse_of()
1560 if (!sai->np_sync_provider) { in stm32_sai_sub_parse_of()
1561 dev_err(&pdev->dev, "%pOFn parent node not found\n", in stm32_sai_sub_parse_of()
1562 np); in stm32_sai_sub_parse_of()
1563 of_node_put(args.np); in stm32_sai_sub_parse_of()
1564 return -ENODEV; in stm32_sai_sub_parse_of()
1567 sai->sync = SAI_SYNC_INTERNAL; in stm32_sai_sub_parse_of()
1568 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { in stm32_sai_sub_parse_of()
1570 dev_err(&pdev->dev, in stm32_sai_sub_parse_of()
1572 of_node_put(args.np); in stm32_sai_sub_parse_of()
1573 return -EINVAL; in stm32_sai_sub_parse_of()
1575 sai->sync = SAI_SYNC_EXTERNAL; in stm32_sai_sub_parse_of()
1577 sai->synci = args.args[0]; in stm32_sai_sub_parse_of()
1578 if (sai->synci < 1 || in stm32_sai_sub_parse_of()
1579 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { in stm32_sai_sub_parse_of()
1580 dev_err(&pdev->dev, "Wrong SAI index\n"); in stm32_sai_sub_parse_of()
1581 of_node_put(args.np); in stm32_sai_sub_parse_of()
1582 return -EINVAL; in stm32_sai_sub_parse_of()
1585 if (of_property_match_string(args.np, "compatible", in stm32_sai_sub_parse_of()
1586 "st,stm32-sai-sub-a") >= 0) in stm32_sai_sub_parse_of()
1587 sai->synco = STM_SAI_SYNC_OUT_A; in stm32_sai_sub_parse_of()
1589 if (of_property_match_string(args.np, "compatible", in stm32_sai_sub_parse_of()
1590 "st,stm32-sai-sub-b") >= 0) in stm32_sai_sub_parse_of()
1591 sai->synco = STM_SAI_SYNC_OUT_B; in stm32_sai_sub_parse_of()
1593 if (!sai->synco) { in stm32_sai_sub_parse_of()
1594 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); in stm32_sai_sub_parse_of()
1595 of_node_put(args.np); in stm32_sai_sub_parse_of()
1596 return -EINVAL; in stm32_sai_sub_parse_of()
1600 dev_dbg(&pdev->dev, "%s synchronized with %s\n", in stm32_sai_sub_parse_of()
1601 pdev->name, args.np->full_name); in stm32_sai_sub_parse_of()
1604 of_node_put(args.np); in stm32_sai_sub_parse_of()
1605 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); in stm32_sai_sub_parse_of()
1606 if (IS_ERR(sai->sai_ck)) in stm32_sai_sub_parse_of()
1607 return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck), in stm32_sai_sub_parse_of()
1610 ret = clk_prepare(sai->pdata->pclk); in stm32_sai_sub_parse_of()
1614 if (STM_SAI_IS_F4(sai->pdata)) in stm32_sai_sub_parse_of()
1618 if (of_property_present(np, "#clock-cells")) { in stm32_sai_sub_parse_of()
1623 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK"); in stm32_sai_sub_parse_of()
1624 if (IS_ERR(sai->sai_mclk)) in stm32_sai_sub_parse_of()
1625 return PTR_ERR(sai->sai_mclk); in stm32_sai_sub_parse_of()
1637 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); in stm32_sai_sub_probe()
1639 return -ENOMEM; in stm32_sai_sub_probe()
1641 sai->id = (uintptr_t)device_get_match_data(&pdev->dev); in stm32_sai_sub_probe()
1643 sai->pdev = pdev; in stm32_sai_sub_probe()
1644 mutex_init(&sai->ctrl_lock); in stm32_sai_sub_probe()
1645 spin_lock_init(&sai->irq_lock); in stm32_sai_sub_probe()
1648 sai->pdata = dev_get_drvdata(pdev->dev.parent); in stm32_sai_sub_probe()
1649 if (!sai->pdata) { in stm32_sai_sub_probe()
1650 dev_err(&pdev->dev, "Parent device data not available\n"); in stm32_sai_sub_probe()
1651 return -EINVAL; in stm32_sai_sub_probe()
1654 if (sai->pdata->conf.get_sai_ck_parent) { in stm32_sai_sub_probe()
1655 sai->set_sai_ck_rate = stm32_sai_set_parent_clk; in stm32_sai_sub_probe()
1657 sai->set_sai_ck_rate = stm32_sai_set_parent_rate; in stm32_sai_sub_probe()
1658 sai->put_sai_ck_rate = stm32_sai_put_parent_rate; in stm32_sai_sub_probe()
1666 sai->cpu_dai_drv = stm32_sai_playback_dai; in stm32_sai_sub_probe()
1668 sai->cpu_dai_drv = stm32_sai_capture_dai; in stm32_sai_sub_probe()
1669 sai->cpu_dai_drv.name = dev_name(&pdev->dev); in stm32_sai_sub_probe()
1671 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, in stm32_sai_sub_probe()
1672 IRQF_SHARED, dev_name(&pdev->dev), sai); in stm32_sai_sub_probe()
1674 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); in stm32_sai_sub_probe()
1681 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0); in stm32_sai_sub_probe()
1683 return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n"); in stm32_sai_sub_probe()
1685 ret = snd_soc_register_component(&pdev->dev, &stm32_component, in stm32_sai_sub_probe()
1686 &sai->cpu_dai_drv, 1); in stm32_sai_sub_probe()
1688 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_sai_sub_probe()
1692 pm_runtime_enable(&pdev->dev); in stm32_sai_sub_probe()
1699 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); in stm32_sai_sub_remove()
1701 clk_unprepare(sai->pdata->pclk); in stm32_sai_sub_remove()
1702 snd_dmaengine_pcm_unregister(&pdev->dev); in stm32_sai_sub_remove()
1703 snd_soc_unregister_component(&pdev->dev); in stm32_sai_sub_remove()
1704 pm_runtime_disable(&pdev->dev); in stm32_sai_sub_remove()
1713 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_suspend()
1717 regcache_cache_only(sai->regmap, true); in stm32_sai_sub_suspend()
1718 regcache_mark_dirty(sai->regmap); in stm32_sai_sub_suspend()
1720 clk_disable(sai->pdata->pclk); in stm32_sai_sub_suspend()
1730 ret = clk_enable(sai->pdata->pclk); in stm32_sai_sub_resume()
1734 regcache_cache_only(sai->regmap, false); in stm32_sai_sub_resume()
1735 ret = regcache_sync(sai->regmap); in stm32_sai_sub_resume()
1737 clk_disable(sai->pdata->pclk); in stm32_sai_sub_resume()
1749 .name = "st,stm32-sai-sub",
1759 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1761 MODULE_ALIAS("platform:st,stm32-sai-sub");