1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7  * Author: Xing Zheng <zhengxing@rock-chips.com>
21 #include <linux/clk-provider.h>
348 	.rate	= _rate##U,					\
359 	.rate	= _rate##U,			\
368 	.rate	= _rate##U,					\
377 	.rate   = _rate##U,					\
385  * struct rockchip_clk_provider - information about clock provider
388  * @cru_node: device-node of the clock-provider
389  * @grf: regmap of the general-register-files syscon
390  * @lock: maintains exclusion between callbacks for a given clock-provider.
401 	unsigned long rate;  member
430  * struct rockchip_pll_clock - information about pll clock
437  * @mode_offset: offset of the register for configuring the PLL-mode.
438  * @mode_shift: offset inside the mode-register for the mode of this pll.
441  * @pll_flags: hardware-specific flags
445  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
505  * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
539  * DDRCLK flags, including method of setting the rate
540  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
603 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\  argument
613 		.mux_shift	= ms,				\
624 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw,	\  argument
634 		.mux_shift	= ms,				\
683 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,	\  argument
693 		.mux_shift	= ms,				\
701 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf,	\  argument
711 		.mux_shift	= ms,				\
717 		.gate_offset	= -1,				\
720 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,	\  argument
730 		.mux_shift	= ms,				\
737 		.gate_offset	= -1,				\
787 		.gate_offset	= -1,				\
791 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw,	\  argument
801 		.mux_shift      = ms,                           \
806 		.gate_offset    = -1,                           \
821 		.gate_offset	= -1,				\
836 		.gate_offset	= -1,				\
852 		.gate_offset	= -1,				\
867 		.gate_offset	= -1,				\
948 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\  argument
958 		.mux_shift	= ms,				\
969 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf,	\  argument
979 		.mux_shift	= ms,				\
985 		.gate_offset	= -1,				\
1018 		.gate_offset	= -1,				\
1025 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
1027 void rockchip_clk_of_add_provider(struct device_node *np,
1061 void rockchip_register_softrst_lut(struct device_node *np,
1066 static inline void rockchip_register_softrst_lut(struct device_node *np,  in rockchip_register_softrst_lut()  argument
1074 static inline void rockchip_register_softrst(struct device_node *np,  in rockchip_register_softrst()  argument
1078 	return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);  in rockchip_register_softrst()
1081 void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
1082 void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);