Lines Matching +full:rate +full:- +full:np +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
55 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
56 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
57 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
58 …[ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 en…
59 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
60 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
61 …[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port …
62 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
63 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
64 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
65 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
66 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
67 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
68 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
69 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
70 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
71 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
72 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
137 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ in aspeed_ast2400_calc_pll()
142 mult = (2 - od) * (n + 2); in aspeed_ast2400_calc_pll()
187 u32 clk = BIT(gate->clock_idx); in aspeed_clk_is_enabled()
188 u32 rst = BIT(gate->reset_idx); in aspeed_clk_is_enabled()
189 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_clk_is_enabled()
198 if (gate->reset_idx >= 0) { in aspeed_clk_is_enabled()
199 regmap_read(gate->map, ASPEED_RESET_CTRL, ®); in aspeed_clk_is_enabled()
204 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); in aspeed_clk_is_enabled()
213 u32 clk = BIT(gate->clock_idx); in aspeed_clk_enable()
214 u32 rst = BIT(gate->reset_idx); in aspeed_clk_enable()
217 spin_lock_irqsave(gate->lock, flags); in aspeed_clk_enable()
220 spin_unlock_irqrestore(gate->lock, flags); in aspeed_clk_enable()
224 if (gate->reset_idx >= 0) { in aspeed_clk_enable()
226 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); in aspeed_clk_enable()
233 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_clk_enable()
234 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); in aspeed_clk_enable()
236 if (gate->reset_idx >= 0) { in aspeed_clk_enable()
237 /* A delay of 10ms is specified by the ASPEED docs */ in aspeed_clk_enable()
241 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); in aspeed_clk_enable()
244 spin_unlock_irqrestore(gate->lock, flags); in aspeed_clk_enable()
253 u32 clk = BIT(gate->clock_idx); in aspeed_clk_disable()
256 spin_lock_irqsave(gate->lock, flags); in aspeed_clk_disable()
258 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0; in aspeed_clk_disable()
259 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); in aspeed_clk_disable()
261 spin_unlock_irqrestore(gate->lock, flags); in aspeed_clk_disable()
297 bit -= ASPEED_RESET2_OFFSET; in aspeed_reset_deassert()
301 return regmap_update_bits(ar->map, reg, BIT(bit), 0); in aspeed_reset_deassert()
312 bit -= ASPEED_RESET2_OFFSET; in aspeed_reset_assert()
316 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); in aspeed_reset_assert()
328 bit -= ASPEED_RESET2_OFFSET; in aspeed_reset_status()
332 ret = regmap_read(ar->map, reg, &val); in aspeed_reset_status()
357 return ERR_PTR(-ENOMEM); in aspeed_clk_hw_register_gate()
365 gate->map = map; in aspeed_clk_hw_register_gate()
366 gate->clock_idx = clock_idx; in aspeed_clk_hw_register_gate()
367 gate->reset_idx = reset_idx; in aspeed_clk_hw_register_gate()
368 gate->flags = clk_gate_flags; in aspeed_clk_hw_register_gate()
369 gate->lock = lock; in aspeed_clk_hw_register_gate()
370 gate->hw.init = &init; in aspeed_clk_hw_register_gate()
372 hw = &gate->hw; in aspeed_clk_hw_register_gate()
385 struct device *dev = &pdev->dev; in aspeed_clk_probe()
389 u32 val, rate; in aspeed_clk_probe() local
392 map = syscon_node_to_regmap(dev->of_node); in aspeed_clk_probe()
400 return -ENOMEM; in aspeed_clk_probe()
402 ar->map = map; in aspeed_clk_probe()
403 ar->rcdev.owner = THIS_MODULE; in aspeed_clk_probe()
404 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); in aspeed_clk_probe()
405 ar->rcdev.ops = &aspeed_reset_ops; in aspeed_clk_probe()
406 ar->rcdev.of_node = dev->of_node; in aspeed_clk_probe()
408 ret = devm_reset_controller_register(dev, &ar->rcdev); in aspeed_clk_probe()
418 return -EINVAL; in aspeed_clk_probe()
424 rate = 24000000 / 13; in aspeed_clk_probe()
426 rate = 24000000; in aspeed_clk_probe()
428 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); in aspeed_clk_probe()
431 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_clk_probe()
434 * Memory controller (M-PLL) PLL. This clock is configured by the in aspeed_clk_probe()
435 * bootloader, and is exposed to Linux as a read-only clock rate. in aspeed_clk_probe()
438 hw = soc_data->calc_pll("mpll", val); in aspeed_clk_probe()
441 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; in aspeed_clk_probe()
451 soc_data->div_table, in aspeed_clk_probe()
455 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_clk_probe()
460 soc_data->mac_div_table, in aspeed_clk_probe()
464 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; in aspeed_clk_probe()
466 if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) { in aspeed_clk_probe()
479 aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; in aspeed_clk_probe()
487 aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; in aspeed_clk_probe()
493 soc_data->div_table, in aspeed_clk_probe()
497 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; in aspeed_clk_probe()
499 /* P-Bus (BCLK) clock divider */ in aspeed_clk_probe()
502 soc_data->div_table, in aspeed_clk_probe()
506 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; in aspeed_clk_probe()
509 hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin", in aspeed_clk_probe()
513 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; in aspeed_clk_probe()
515 hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names, in aspeed_clk_probe()
521 aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; in aspeed_clk_probe()
523 hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0, in aspeed_clk_probe()
525 3, 0, soc_data->eclk_div_table, in aspeed_clk_probe()
529 aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; in aspeed_clk_probe()
534 * D2-PLL in aspeed_clk_probe()
535 * D-PLL in aspeed_clk_probe()
549 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; in aspeed_clk_probe()
551 gd->name, in aspeed_clk_probe()
552 gd->parent_name, in aspeed_clk_probe()
553 gd->flags, in aspeed_clk_probe()
555 gd->clock_idx, in aspeed_clk_probe()
556 gd->reset_idx, in aspeed_clk_probe()
561 aspeed_clk_data->hws[i] = hw; in aspeed_clk_probe()
568 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
569 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
576 .name = "aspeed-clk",
591 int rate; in aspeed_ast2400_cc() local
598 rate = (val >> 8) & 3; in aspeed_ast2400_cc()
601 hpll = hpll_rates[1][rate]; in aspeed_ast2400_cc()
604 hpll = hpll_rates[0][rate]; in aspeed_ast2400_cc()
607 hpll = hpll_rates[0][rate]; in aspeed_ast2400_cc()
613 * High-speed PLL clock derived from the crystal. This the CPU clock, in aspeed_ast2400_cc()
624 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw; in aspeed_ast2400_cc()
641 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; in aspeed_ast2400_cc()
648 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; in aspeed_ast2400_cc()
666 * High-speed PLL clock derived from the crystal. This the CPU clock, in aspeed_ast2500_cc()
670 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); in aspeed_ast2500_cc()
678 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; in aspeed_ast2500_cc()
685 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; in aspeed_ast2500_cc()
688 static void __init aspeed_cc_init(struct device_node *np) in aspeed_cc_init() argument
695 scu_base = of_iomap(np, 0); in aspeed_cc_init()
704 aspeed_clk_data->num = ASPEED_NUM_CLKS; in aspeed_cc_init()
711 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); in aspeed_cc_init()
713 map = syscon_node_to_regmap(np); in aspeed_cc_init()
720 * but as this is an MMIO-backed regmap, subsequent regmap in aspeed_cc_init()
730 if (of_device_is_compatible(np, "aspeed,ast2400-scu")) in aspeed_cc_init()
732 else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) in aspeed_cc_init()
736 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); in aspeed_cc_init()
740 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
741 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);