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/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml166 pll0: pll0@800 {
171 clock-output-names = "pll0", "pll0-div2";
186 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
195 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
H A Dmicrochip,mpfs-ccc.yaml24 - description: PLL0's control registers
35 - description: PLL0's refclk0
36 - description: PLL0's refclk1
H A Dsilabs,si5351.yaml216 /* Use XTAL input as source of PLL0 and PLL1 */
225 * - PLL0 as clock source of multisynth 0
227 * - Multisynth 0 can change PLL0
H A Dstarfive,jh7110-syscrg.yaml30 - description: PLL0
44 - description: PLL0
H A Drenesas,cpg-clocks.yaml78 - const: pll0
204 - const: pll0
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/linux/drivers/clk/mxs/
H A Dclk-imx28.c127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
176 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); in mx28_clocks_init()
[all …]
/linux/drivers/clk/mvebu/
H A Dcp110-system-controller.c14 * - PLL0 (1 Ghz)
15 * - PPv2 core (1/3 PLL0)
16 * - x2 Core (1/2 PLL0)
18 * - SDIO (2/5 PLL0)
22 * - 2/5 PLL0
247 /* Register the PLL0 which is the root of the hw tree */ in cp110_syscon_common_probe()
248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); in cp110_syscon_common_probe()
258 /* PPv2 is PLL0/3 */ in cp110_syscon_common_probe()
268 /* X2CORE clock is PLL0/2 */ in cp110_syscon_common_probe()
289 /* NAND can be either PLL0/2.5 or core clock */ in cp110_syscon_common_probe()
[all …]
/linux/drivers/bcma/
H A Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
351 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
[all …]
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen-pll.txt12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
/linux/drivers/clk/
H A Dclk-k210.c300 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
301 * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0
340 * Set ACLK parent selector: 0 for IN0, 1 for PLL0.
398 * For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and in k210_pll_enable_hw()
461 * stop working. This is especially important for pll0, the indirect in k210_pll_disable()
576 /* PLL0 and PLL1 only have IN0 as parent */ in k210_register_plls()
577 ret = k210_register_pll(np, ksc, K210_PLL0, "pll0", 1, &k210_pll_ops); in k210_register_plls()
579 pr_err("%pOFP: register PLL0 failed\n", np); in k210_register_plls()
588 /* PLL2 has IN0, PLL0 and PLL1 as parents */ in k210_register_plls()
645 * ACLK has IN0 and PLL0 as parents.
[all …]
/linux/include/linux/firmware/imx/svc/
H A Dpm.h80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
/linux/drivers/clk/ingenic/
H A Djz4760-cgu.c93 "pll0", CGU_CLK_PLL,
117 /* TODO: PLL1 can depend on PLL0 */
212 /* Those divided clocks can connect to PLL0 or PLL1 */
254 /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
280 /* Those divided clocks can connect to EXT or PLL0 */
294 /* These divided clock can connect to PLL0 only */
H A Djz4770-cgu.c103 "pll0", CGU_CLK_PLL,
126 /* TODO: PLL1 can depend on PLL0 */
206 /* Those divided clocks can connect to PLL0 or PLL1 */
272 /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
/linux/arch/arc/boot/dts/
H A Dabilis_tb10x.dtsi48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
/linux/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c36 /* PLL0 bits common to both audio and USB PLL */
48 /* Register value that gives PLL0 post/pre dividers equal to 1 */
286 * PLL0 uses a special register value encoding. The compute functions below
290 /* Compute PLL0 multiplier from decoded version */
304 /* Compute PLL0 decoded multiplier from binary version */
320 /* Compute PLL0 bandwidth SELI reg from multiplier */
337 /* Compute PLL0 bandwidth SELP reg from multiplier */
/linux/arch/arm/boot/dts/st/
H A Dstih407-clock.dtsi70 compatible = "st,clkgen-pll0-a0";
89 clk_s_c0_pll0: clk-s-c0-pll0 {
91 compatible = "st,clkgen-pll0-c0";
H A Dstih410-clock.dtsi75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
H A Dstih418-clock.dtsi75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
/linux/drivers/gpu/drm/tegra/
H A Dhdmi.c44 u32 pll0; member
140 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
173 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
187 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
201 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
219 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
237 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
256 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
275 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
/linux/drivers/clk/renesas/
H A Dr8a7745-cpg-mssr.c44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
190 * MD EXTAL PLL0 PLL1 PLL3
198 * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
H A Dclk-r8a73a4.c87 } else if (!strcmp(name, "pll0")) { in r8a73a4_cpg_register_clock()
88 /* PLL0/1 are configurable multiplier clocks. Register them as in r8a73a4_cpg_register_clock()
153 parent_name = "pll0"; in r8a73a4_cpg_register_clock()
H A Dr8a7792-cpg-mssr.c46 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
164 * MD EXTAL PLL0 PLL1 PLL3
176 * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
H A Dr8a77470-cpg-mssr.c44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
173 * MD EXTAL PLL0 PLL1 PLL3
181 * *1 : Table 7.4 indicates VCO output (PLL0 = VCO)
/linux/sound/soc/codecs/
H A Dak4642.c116 #define PLL0 (1 << 4) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()

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