Lines Matching full:pll0
14 * - PLL0 (1 Ghz)
15 * - PPv2 core (1/3 PLL0)
16 * - x2 Core (1/2 PLL0)
18 * - SDIO (2/5 PLL0)
22 * - 2/5 PLL0
247 /* Register the PLL0 which is the root of the hw tree */ in cp110_syscon_common_probe()
248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); in cp110_syscon_common_probe()
258 /* PPv2 is PLL0/3 */ in cp110_syscon_common_probe()
268 /* X2CORE clock is PLL0/2 */ in cp110_syscon_common_probe()
289 /* NAND can be either PLL0/2.5 or core clock */ in cp110_syscon_common_probe()
304 /* SDIO clock is PLL0/2.5 */ in cp110_syscon_common_probe()