Lines Matching full:pll0

300  * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
301  * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0
340  * Set ACLK parent selector: 0 for IN0, 1 for PLL0.
398 	 * For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and  in k210_pll_enable_hw()
461 	 * stop working. This is especially important for pll0, the indirect  in k210_pll_disable()
576 	/* PLL0 and PLL1 only have IN0 as parent */  in k210_register_plls()
577 	ret = k210_register_pll(np, ksc, K210_PLL0, "pll0", 1, &k210_pll_ops);  in k210_register_plls()
579 		pr_err("%pOFP: register PLL0 failed\n", np);  in k210_register_plls()
588 	/* PLL2 has IN0, PLL0 and PLL1 as parents */  in k210_register_plls()
645  * ACLK has IN0 and PLL0 as parents.
821  * All muxed clocks have IN0 and PLL0 as parents.
940 	/* Clocks with PLL0 as source */  in k210_clk_init()
973 	/* Mux clocks with in0 or pll0 as source */  in k210_clk_init()
1004 	/* Make sure ACLK selector is set to PLL0 */  in k210_clk_early_init()