84 	u32 pll0, mask;  in bcma_pmu2_pll_init0()  local
115 	pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);  in bcma_pmu2_pll_init0()
116 	freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>  in bcma_pmu2_pll_init0()
137 	pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;  in bcma_pmu2_pll_init0()
138 	pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;  in bcma_pmu2_pll_init0()
139 	bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);  in bcma_pmu2_pll_init0()
351  * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)  in bcma_pmu_pll_clock()  argument
358 	BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));  in bcma_pmu_pll_clock()
370 	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);  in bcma_pmu_pll_clock()
374 	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);  in bcma_pmu_pll_clock()
378 	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);  in bcma_pmu_pll_clock()
389 static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)  in bcma_pmu_pll_clock_bcm4706()  argument
397 	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);  in bcma_pmu_pll_clock_bcm4706()