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/linux/drivers/hwmon/
H A Dnct7904.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
28 #define VENDOR_ID_REG 0x7A /* Any bank */
30 #define CHIP_ID_REG 0x7B /* Any bank */
32 #define DEVICE_ID_REG 0x7C /* Any bank */
50 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */
51 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */
52 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */
59 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
60 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
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/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * struct meson_pmx_group - a pinmux group
38 * struct meson_pmx_func - a pinmux function
51 * struct meson_reg_desc - a register descriptor
57 * pull-enable, direction, etc. for a single pin
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
78 * enum meson_pinconf_drv - value of drive-strength supported
88 * struct meson bank
90 * @name: bank name
91 * @first: first pin of the bank
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
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H A Dcanaan,k230-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ze Huang <18771902331@163.com>
15 performed on a per-pin basis.
19 const: canaan,k230-pinctrl
25 '-pins$':
33 '-cfg$':
36 - $ref: /schemas/pinctrl/pincfg-node.yaml
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/linux/drivers/mtd/nand/raw/
H A Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank) argument
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) argument
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) argument
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) argument
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) argument
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) argument
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) argument
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) argument
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/linux/arch/x86/kernel/cpu/mce/
H A Dinternal.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 void mce_intel_handle_storm(int bank, bool on);
45 void cmci_disable_bank(int bank);
52 static inline void mce_intel_handle_storm(int bank, bool on) { } in mce_intel_handle_storm() argument
53 static inline void cmci_disable_bank(int bank) { } in cmci_disable_bank() argument
64 void cmci_storm_begin(unsigned int bank);
65 void cmci_storm_end(unsigned int bank);
67 void mce_inherit_storm(unsigned int bank);
71 static inline void cmci_storm_begin(unsigned int bank) {} in cmci_storm_begin() argument
72 static inline void cmci_storm_end(unsigned int bank) {} in cmci_storm_end() argument
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H A Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
135 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
139 if (!b->hwid) in smca_get_bank_type()
142 return b->hwid->bank_type; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
222 /* This block's number within its bank. */
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/linux/drivers/pinctrl/
H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
78 * each register is dedicated per pin.
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
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H A Dpinctrl-eyeq5.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * pull-down, pull-up, drive strength and muxing.
10 * that is pin-dependent. Functions are declared statically in this driver.
15 * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
33 #include <linux/pinctrl/pinconf-generic.h>
39 #include "pinctrl-utils.h"
69 * Drive strength; two bits per pin.
77 /* Bank A */
110 /* Bank B */
137 /* Bank A */
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/linux/drivers/thermal/mediatek/
H A Dauxadc_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
109 /* The number of sensing points per bank */
119 #define MT8173_TEMP_MIN -20000
198 /* The number of sensing points per bank */
219 /* The number of sensing points per bank */
258 /* The number of sensing points per bank */
276 /* The number of sensing points per bank */
472 * The MT8173 thermal controller has four banks. Each bank can read up to
474 * temperature sensors. We use each bank to measure a certain area of the
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/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json8 …: "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS…
19 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch…
92 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch…
102 …: "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS…
122 …ounts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS…
142 …elect) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS…
162 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch…
177 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mo…
183 … number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
188 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major M…
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/linux/drivers/gpio/
H A Dgpio-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2007 David Brownell
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
73 /*--------------------------------------------------------------------------*/
83 int bank = offset / 32; in __davinci_direction() local
86 g = d->regs[bank]; in __davinci_direction()
87 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
88 temp = readl_relaxed(&g->dir); in __davinci_direction()
91 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
95 writel_relaxed(temp, &g->dir); in __davinci_direction()
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H A Dgpio-thunderx.c56 struct msix_entry *msix_entries; /* per line MSI-X */
57 struct thunderx_line *line_entries; /* per line irq info */
77 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_is_gpio_nowarn()
84 * allow modification of the state of non-GPIO pins from this driver.
100 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO; in thunderx_gpio_request()
108 return -EIO; in thunderx_gpio_dir_in()
110 raw_spin_lock(&txgpio->lock); in thunderx_gpio_dir_in()
111 clear_bit(line, txgpio->invert_mask); in thunderx_gpio_dir_in()
112 clear_bit(line, txgpio->od_mask); in thunderx_gpio_dir_in()
113 writeq(txgpio->line_entries[line].fil_bits, in thunderx_gpio_dir_in()
[all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json8 …: "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS…
19 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch…
92 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch…
102 …: "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS…
122 …ounts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS…
142 …elect) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS…
162 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch…
177 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mo…
183 … number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
188 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major M…
[all …]
/linux/include/linux/soundwire/
H A Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
83 /* sample packaging for block. It can be per port or per channel */
88 * enum sdw_slave_status - Slave status
106 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepar
558 unsigned int bank; global() member
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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json60 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
80 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
128 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read…
133 … number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
138 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Writ…
143 …nts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
198 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
208 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
218 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
228 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm2835-armctrl-ic.yaml2 ---
3 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml#
4 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Florian Fainelli <florian.fainelli@broadcom.com>
10 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
13 The BCM2835 contains a custom top-level interrupt controller, which supports
14 72 interrupt sources using a 2-level register scheme. The interrupt
19 but the per-CPU interrupt controller is the root, and an interrupt there
24 Bank 0:
34 Bank 1:
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/linux/Documentation/admin-guide/perf/
H A Dampere_cspmu.rst1 .. SPDX-License-Identifier: GPL-2.0
13 --------------
15 The PMU driver supports setting filters for "rank", "bank", and "threshold".
16 Note, that the filters are per PMU instance rather than per event.
28 …/ # perf stat -a -e ampere_mcu_pmu_0/act_sent,bank=5,rank=3,threshold=2/,ampere_mcu_pmu_1/rd_sent/…
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
116 .eint_mask = (1 << (pins)) - 1, \
140 .eint_mask = (1 << (pins)) - 1, \
194 .eint_mask = (1 << (pins)) - 1, \
200 * struct s3c64xx_eint0_data - EINT0 common data
212 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
213 * @bank: pin bank related to the domain
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/linux/Documentation/devicetree/bindings/gpio/
H A Dbrcm,kona-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,kona-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
15 - Ray Jui <rjui@broadcom.com>
20 - enum:
21 - brcm,bcm11351-gpio
22 - brcm,bcm21664-gpio
23 - brcm,bcm23550-gpio
[all …]
/linux/arch/arm/mach-s3c/
H A Dgpio-samsung.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
43 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
58 void __iomem *reg = chip->base + 0x08; in samsung_gpio_getpull_updown()
[all …]
/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
119 * - name: Register name (unused, for documentation purposes only)
120 * - r: Physical register address
121 * - r_width: Width of the register (in bits)
122 * - f_width: Width of the fixed-width register fields (in bits)
123 * - ids: For each register field (from left to right, i.e. MSB to LSB),
137 * - name: Register name (unused, for documentation purposes only)
138 * - r: Physical register address
139 * - r_width: Width of the register (in bits)
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json82 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
102 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
150 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
155 "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
160 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
165 "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
170 "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
236 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wid
[all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json60 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
80 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
128 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read…
133 … number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
138 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Writ…
143 …nts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
198 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
208 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
218 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
228 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json82 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
102 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
150 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read…
155 … number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
160 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Writ…
165 …nts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
227 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
237 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
247 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
257 …filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank)…
[all …]

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