Lines Matching +full:per +full:- +full:bank
56 struct msix_entry *msix_entries; /* per line MSI-X */
57 struct thunderx_line *line_entries; /* per line irq info */
77 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_is_gpio_nowarn()
84 * allow modification of the state of non-GPIO pins from this driver.
100 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO; in thunderx_gpio_request()
108 return -EIO; in thunderx_gpio_dir_in()
110 raw_spin_lock(&txgpio->lock); in thunderx_gpio_dir_in()
111 clear_bit(line, txgpio->invert_mask); in thunderx_gpio_dir_in()
112 clear_bit(line, txgpio->od_mask); in thunderx_gpio_dir_in()
113 writeq(txgpio->line_entries[line].fil_bits, in thunderx_gpio_dir_in()
114 txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_in()
115 raw_spin_unlock(&txgpio->lock); in thunderx_gpio_dir_in()
123 int bank = line / 64; in thunderx_gpio_set() local
126 void __iomem *reg = txgpio->register_base + in thunderx_gpio_set()
127 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR); in thunderx_gpio_set()
138 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE; in thunderx_gpio_dir_out()
141 return -EIO; in thunderx_gpio_dir_out()
143 raw_spin_lock(&txgpio->lock); in thunderx_gpio_dir_out()
147 if (test_bit(line, txgpio->invert_mask)) in thunderx_gpio_dir_out()
150 if (test_bit(line, txgpio->od_mask)) in thunderx_gpio_dir_out()
153 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_out()
155 raw_spin_unlock(&txgpio->lock); in thunderx_gpio_dir_out()
172 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_get_direction()
187 int bank = line / 64; in thunderx_gpio_set_config() local
189 int ret = -ENOTSUPP; in thunderx_gpio_set_config()
191 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; in thunderx_gpio_set_config()
194 return -EIO; in thunderx_gpio_set_config()
196 raw_spin_lock(&txgpio->lock); in thunderx_gpio_set_config()
197 orig_invert = test_bit(line, txgpio->invert_mask); in thunderx_gpio_set_config()
199 orig_od = test_bit(line, txgpio->od_mask); in thunderx_gpio_set_config()
202 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
206 * Weird, setting open-drain mode causes signal in thunderx_gpio_set_config()
210 set_bit(line, txgpio->invert_mask); in thunderx_gpio_set_config()
212 set_bit(line, txgpio->od_mask); in thunderx_gpio_set_config()
217 clear_bit(line, txgpio->invert_mask); in thunderx_gpio_set_config()
219 clear_bit(line, txgpio->od_mask); in thunderx_gpio_set_config()
226 ret = -EINVAL; in thunderx_gpio_set_config()
236 txgpio->line_entries[line].fil_bits = in thunderx_gpio_set_config()
240 bit_cfg |= txgpio->line_entries[line].fil_bits; in thunderx_gpio_set_config()
241 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
247 raw_spin_unlock(&txgpio->lock); in thunderx_gpio_set_config()
263 int bank = line / 64; in thunderx_gpio_get() local
265 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); in thunderx_gpio_get()
268 if (test_bit(line, txgpio->invert_mask)) in thunderx_gpio_get()
278 int bank; in thunderx_gpio_set_multiple() local
282 for (bank = 0; bank <= chip->ngpio / 64; bank++) { in thunderx_gpio_set_multiple()
283 set_bits = bits[bank] & mask[bank]; in thunderx_gpio_set_multiple()
284 clear_bits = ~bits[bank] & mask[bank]; in thunderx_gpio_set_multiple()
285 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
286 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); in thunderx_gpio_set_multiple()
298 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); in thunderx_gpio_irq_ack()
307 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); in thunderx_gpio_irq_mask()
316 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); in thunderx_gpio_irq_mask_ack()
325 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); in thunderx_gpio_irq_unmask()
334 &txgpio->line_entries[irqd_to_hwirq(d)]; in thunderx_gpio_irq_set_type()
339 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN; in thunderx_gpio_irq_set_type()
348 raw_spin_lock(&txgpio->lock); in thunderx_gpio_irq_set_type()
351 set_bit(txline->line, txgpio->invert_mask); in thunderx_gpio_irq_set_type()
353 clear_bit(txline->line, txgpio->invert_mask); in thunderx_gpio_irq_set_type()
355 clear_bit(txline->line, txgpio->od_mask); in thunderx_gpio_irq_set_type()
356 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line)); in thunderx_gpio_irq_set_type()
357 raw_spin_unlock(&txgpio->lock); in thunderx_gpio_irq_set_type()
381 * Interrupts are chained from underlying MSI-X vectors. We have
411 irq = txgpio->msix_entries[child].vector; in thunderx_gpio_child_to_parent_hwirq()
412 irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq); in thunderx_gpio_child_to_parent_hwirq()
414 return -EINVAL; in thunderx_gpio_child_to_parent_hwirq()
425 msi_alloc_info_t *info = &gfwspec->msiinfo; in thunderx_gpio_populate_parent_alloc_info()
427 info->hwirq = parent_hwirq; in thunderx_gpio_populate_parent_alloc_info()
435 struct device *dev = &pdev->dev; in thunderx_gpio_probe()
444 return -ENOMEM; in thunderx_gpio_probe()
446 raw_spin_lock_init(&txgpio->lock); in thunderx_gpio_probe()
447 chip = &txgpio->chip; in thunderx_gpio_probe()
464 txgpio->register_base = tbl[0]; in thunderx_gpio_probe()
465 if (!txgpio->register_base) { in thunderx_gpio_probe()
467 err = -ENOMEM; in thunderx_gpio_probe()
471 if (pdev->subsystem_device == 0xa10a) { in thunderx_gpio_probe()
474 txgpio->base_msi = 48; in thunderx_gpio_probe()
476 u64 c = readq(txgpio->register_base + GPIO_CONST); in thunderx_gpio_probe()
479 txgpio->base_msi = (c >> 8) & 0xff; in thunderx_gpio_probe()
482 txgpio->msix_entries = devm_kcalloc(dev, in thunderx_gpio_probe()
485 if (!txgpio->msix_entries) { in thunderx_gpio_probe()
486 err = -ENOMEM; in thunderx_gpio_probe()
490 txgpio->line_entries = devm_kcalloc(dev, in thunderx_gpio_probe()
494 if (!txgpio->line_entries) { in thunderx_gpio_probe()
495 err = -ENOMEM; in thunderx_gpio_probe()
500 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i)); in thunderx_gpio_probe()
502 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i); in thunderx_gpio_probe()
503 txgpio->line_entries[i].line = i; in thunderx_gpio_probe()
504 txgpio->line_entries[i].txgpio = txgpio; in thunderx_gpio_probe()
510 txgpio->line_entries[i].fil_bits = bit_cfg ? in thunderx_gpio_probe()
514 set_bit(i, txgpio->od_mask); in thunderx_gpio_probe()
516 set_bit(i, txgpio->invert_mask); in thunderx_gpio_probe()
520 /* Enable all MSI-X for interrupts on all possible lines. */ in thunderx_gpio_probe()
521 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio); in thunderx_gpio_probe()
525 chip->label = KBUILD_MODNAME; in thunderx_gpio_probe()
526 chip->parent = dev; in thunderx_gpio_probe()
527 chip->owner = THIS_MODULE; in thunderx_gpio_probe()
528 chip->request = thunderx_gpio_request; in thunderx_gpio_probe()
529 chip->base = -1; /* System allocated */ in thunderx_gpio_probe()
530 chip->can_sleep = false; in thunderx_gpio_probe()
531 chip->ngpio = ngpio; in thunderx_gpio_probe()
532 chip->get_direction = thunderx_gpio_get_direction; in thunderx_gpio_probe()
533 chip->direction_input = thunderx_gpio_dir_in; in thunderx_gpio_probe()
534 chip->get = thunderx_gpio_get; in thunderx_gpio_probe()
535 chip->direction_output = thunderx_gpio_dir_out; in thunderx_gpio_probe()
536 chip->set = thunderx_gpio_set; in thunderx_gpio_probe()
537 chip->set_multiple = thunderx_gpio_set_multiple; in thunderx_gpio_probe()
538 chip->set_config = thunderx_gpio_set_config; in thunderx_gpio_probe()
539 girq = &chip->irq; in thunderx_gpio_probe()
541 girq->fwnode = dev_fwnode(dev); in thunderx_gpio_probe()
542 girq->parent_domain = in thunderx_gpio_probe()
543 irq_get_irq_data(txgpio->msix_entries[0].vector)->domain; in thunderx_gpio_probe()
544 girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq; in thunderx_gpio_probe()
545 girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info; in thunderx_gpio_probe()
546 girq->handler = handle_bad_irq; in thunderx_gpio_probe()
547 girq->default_type = IRQ_TYPE_NONE; in thunderx_gpio_probe()
561 err = irq_domain_push_irq(girq->domain, in thunderx_gpio_probe()
562 txgpio->msix_entries[i].vector, in thunderx_gpio_probe()
569 ngpio, chip->base); in thunderx_gpio_probe()
581 for (i = 0; i < txgpio->chip.ngpio; i++) in thunderx_gpio_remove()
582 irq_domain_pop_irq(txgpio->chip.irq.domain, in thunderx_gpio_remove()
583 txgpio->msix_entries[i].vector); in thunderx_gpio_remove()
585 irq_domain_remove(txgpio->chip.irq.domain); in thunderx_gpio_remove()
606 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");