xref: /linux/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml (revision bf373e4c786bfe989e637195252698f45b157a68) 
1%YAML 1.2
2---
3$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml#
4$schema: http://devicetree.org/meta-schemas/core.yaml#
5
6title: BCM2835 ARMCTRL Interrupt Controller
7
8maintainers:
9  - Florian Fainelli <florian.fainelli@broadcom.com>
10  - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
11
12description: >
13  The BCM2835 contains a custom top-level interrupt controller, which supports
14  72 interrupt sources using a 2-level register scheme. The interrupt
15  controller, or the HW block containing it, is referred to occasionally as
16  "armctrl" in the SoC documentation, hence naming of this binding.
17
18  The BCM2836 contains the same interrupt controller with the same interrupts,
19  but the per-CPU interrupt controller is the root, and an interrupt there
20  indicates that the ARMCTRL has an interrupt to handle.
21
22  The interrupt sources are as follows:
23
24  Bank 0:
25    0: ARM_TIMER
26    1: ARM_MAILBOX
27    2: ARM_DOORBELL_0
28    3: ARM_DOORBELL_1
29    4: VPU0_HALTED
30    5: VPU1_HALTED
31    6: ILLEGAL_TYPE0
32    7: ILLEGAL_TYPE1
33
34  Bank 1:
35    0: TIMER0
36    1: TIMER1
37    2: TIMER2
38    3: TIMER3
39    4: CODEC0
40    5: CODEC1
41    6: CODEC2
42    7: VC_JPEG
43    8: ISP
44    9: VC_USB
45    10: VC_3D
46    11: TRANSPOSER
47    12: MULTICORESYNC0
48    13: MULTICORESYNC1
49    14: MULTICORESYNC2
50    15: MULTICORESYNC3
51    16: DMA0
52    17: DMA1
53    18: VC_DMA2
54    19: VC_DMA3
55    20: DMA4
56    21: DMA5
57    22: DMA6
58    23: DMA7
59    24: DMA8
60    25: DMA9
61    26: DMA10
62    27: DMA11-14 - shared interrupt for DMA 11 to 14
63    28: DMAALL - triggers on all dma interrupts (including channel 15)
64    29: AUX
65    30: ARM
66    31: VPUDMA
67
68  Bank 2:
69    0: HOSTPORT
70    1: VIDEOSCALER
71    2: CCP2TX
72    3: SDC
73    4: DSI0
74    5: AVE
75    6: CAM0
76    7: CAM1
77    8: HDMI0
78    9: HDMI1
79    10: PIXELVALVE1
80    11: I2CSPISLV
81    12: DSI1
82    13: PWA0
83    14: PWA1
84    15: CPR
85    16: SMI
86    17: GPIO0
87    18: GPIO1
88    19: GPIO2
89    20: GPIO3
90    21: VC_I2C
91    22: VC_SPI
92    23: VC_I2SPCM
93    24: VC_SDIO
94    25: VC_UART
95    26: SLIMBUS
96    27: VEC
97    28: CPG
98    29: RNG
99    30: VC_ARASANSDIO
100    31: AVSPMON
101
102properties:
103  compatible:
104    enum:
105      - brcm,bcm2835-armctrl-ic
106      - brcm,bcm2836-armctrl-ic
107
108  reg:
109    maxItems: 1
110
111  interrupt-controller: true
112
113  '#interrupt-cells':
114    const: 2
115    description: >
116      The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
117      pending" register, or 1/2 respectively for interrupts in the "IRQ pending
118      1/2" register.
119
120      The 2nd cell contains the interrupt number within the bank. Valid values
121      are 0..7 for bank 0, and 0..31 for bank 1.
122
123  interrupts:
124    maxItems: 1
125
126required:
127  - compatible
128  - reg
129  - interrupt-controller
130  - '#interrupt-cells'
131
132allOf:
133  - if:
134      properties:
135        compatible:
136          contains:
137            const: brcm,bcm2836-armctrl-ic
138    then:
139      required:
140        - interrupts
141    else:
142      properties:
143        interrupts: false
144
145additionalProperties: false
146
147examples:
148  - |
149    interrupt-controller@7e00b200 {
150        compatible = "brcm,bcm2835-armctrl-ic";
151        reg = <0x7e00b200 0x200>;
152        interrupt-controller;
153        #interrupt-cells = <2>;
154    };
155  - |
156    interrupt-controller@7e00b200 {
157        compatible = "brcm,bcm2836-armctrl-ic";
158        reg = <0x7e00b200 0x200>;
159        interrupt-controller;
160        #interrupt-cells = <2>;
161        interrupts = <8>;
162    };
163