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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-rd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (RD-88F6820-AP)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 /dts-v1/;
13 #include "armada-388.dtsi"
17 compatible = "marvell,a385-rd", "marvell,armada388",
21 stdout-path = "serial0:115200n8";
35 internal-regs {
38 clock-frequency = <100000>;
[all …]
H A Darmada-xp-axpwifiap.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Marvell RD-AXPWiFiAP.
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include "armada-xp-mv78230.dtsi"
21 model = "Marvell RD-AXPWiFiAP";
22 …compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,arma…
25 stdout-path = "serial0:115200n8";
[all …]
H A Darmada-388-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6820)
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 /dts-v1/;
12 #include "armada-388.dtsi"
16 compatible = "marvell,a385-db", "marvell,armada388",
20 stdout-path = "serial0:115200n8";
35 internal-regs {
38 clock-frequency = <100000>;
39 audio_codec: audio-codec@4a {
[all …]
H A Darmada-385-db-ap.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (DB-88F6820-AP)
11 /dts-v1/;
12 #include "armada-385.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
21 stdout-path = "serial1:115200n8";
36 internal-regs {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins>;
[all …]
H A Darmada-370-mirabox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include "armada-370.dtsi"
14 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17 stdout-path = "serial0:115200n8";
30 internal-regs {
35 clock-frequency = <600000000>;
40 compatible = "gpio-leds";
[all …]
H A Darmada-xp-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-78460-BP)
6 * Copyright (C) 2012-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
23 /dts-v1/;
24 #include "armada-xp-mv78460.dtsi"
28 …compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
31 stdout-path = "serial0:115200n8";
[all …]
H A Darmada-370-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6710-BP-DDR3)
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include "armada-370.dtsi"
27 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
30 stdout-path = "serial0:115200n8";
43 internal-regs {
[all …]
H A Darmada-xp-gp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-xp-mv78460.dtsi"
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie.txt1 MediaTek Gen2 PCIe controller
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
[all …]
H A Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp1022rdk.dts2 * P1022 RDK 32-bit Physical Address Map Device Tree Source
35 /include/ "p1022si-pre.dtsi"
56 /* MCLK source is a stand-alone oscillator */
57 clock-frequency = <12288000>;
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "spansion,m25p80", "jedec,spi-nor";
91 spi-max-frequency = <1000000>;
93 label = "full-spi-flash";
100 fsl,mode = "i2s-slave";
[all …]
H A Dge_imp3a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
51 #address-cells = <1>;
[all …]
H A Dmvme2500.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
11 /include/ "p2020si-pre.dtsi"
66 fsl,espi-num-chipselects = <2>;
69 compatible = "atmel,at25df641", "jedec,spi-nor";
71 spi-max-frequency = <10000000>;
74 compatible = "atmel,at25df641", "jedec,spi-nor";
76 spi-max-frequency = <10000000>;
86 tbi-handle = <&tbi0>;
87 phy-handle = <&phy1>;
[all …]
H A Dmvme7100.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
10 /include/ "mpc8641si-pre.dtsi"
37 phy-handle = <&phy0>;
38 phy-connection-type = "rgmii-id";
42 phy0: ethernet-phy@1 {
45 phy1: ethernet-phy@2 { label
48 phy2: ethernet-phy@3 {
51 phy3: ethernet-phy@4 {
57 phy-handle = <&phy1>;
[all …]
H A Dp2020rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009-2012 Freescale Semiconductor Inc.
8 /include/ "p2020si-pre.dtsi"
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
[all …]
H A Dc293pcie.dts2 * C293 PCIE Device Tree Source
35 /include/ "c293si-pre.dtsi"
45 ifc: memory-controller@fffe1e000 {
57 pci0: pcie@fffe0a000 {
61 pcie@0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "cfi-flash";
79 bank-width = <2>;
80 device-width = <1>;
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-s922x-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
30 * update these nodes accordingly if PCIe mode is selected by the MCU.
[all …]
H A Dmeson-g12b-a311d-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
30 * update these nodes accordingly if PCIe mode is selected by the MCU.
[all …]
H A Dmeson-sm1-khadas-vim3l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1.dtsi"
10 #include "meson-khadas-vim3.dtsi"
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
17 vddcpu: regulator-vddcpu {
21 compatible = "pwm-regulator";
23 regulator-name = "VDDCPU";
24 regulator-min-microvolt = <690000>;
25 regulator-max-microvolt = <1050000>;
[all …]
/linux/arch/arm/boot/dts/axis/
H A Dartpec6-devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 // Axis ARTPEC-6 development board.
4 /dts-v1/;
8 model = "ARTPEC-6 development board";
9 compatible = "axis,artpec6-dev-board", "axis,artpec6";
19 stdout-path = "serial3:115200n8";
44 &pcie {
51 phy-handle = <&phy1>;
52 phy-mode = "gmii";
55 #address-cells = <0x1>;
[all …]
/linux/drivers/reset/
H A Dreset-uniphier.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/reset-controller.h>
22 #define UNIPHIER_RESET_ID_END ((unsigned int)(-1))
58 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
66 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
69 UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */
80 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
81 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
82 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
83 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654-pcie-usb2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/phy/phy-am654-serdes.h>
13 #include "k3-pinctrl.h"
16 assigned-clocks = <&k3_clks 153 4>,
19 assigned-clock-parents = <&k3_clks 153 8>,
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-bananapi-bpi-r3-mini.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Authors: Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
19 model = "Bananapi BPI-R3 Mini";
20 chassis-type = "embedded";
21 compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";
[all …]

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