Lines Matching +full:pcie +full:- +full:phy1
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-xp-mv78460.dtsi"
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
28 …compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
31 stdout-path = "serial0:115200n8";
37 * 8 GB of plug-in RAM modules by default.The amount
51 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
65 devbus-bootcs {
71 devbus,bus-width = <16>;
72 devbus,turn-off-ps = <60000>;
73 devbus,badr-skew-ps = <0>;
74 devbus,acc-first-ps = <124000>;
75 devbus,acc-next-ps = <248000>;
76 devbus,rd-setup-ps = <0>;
77 devbus,rd-hold-ps = <0>;
80 devbus,sync-enable = <0>;
81 devbus,wr-high-ps = <60000>;
82 devbus,wr-low-ps = <60000>;
83 devbus,ale-wr-ps = <60000>;
87 compatible = "cfi-flash";
89 bank-width = <2>;
93 internal-regs {
107 pinctrl-0 = <&pic_pins>;
108 pinctrl-names = "default";
109 pic_pins: pic-pins-0 {
116 nr-ports = <2>;
123 phy-mode = "qsgmii";
124 buffer-manager = <&bm>;
125 bm,pool-long = <0>;
129 phy = <&phy1>;
130 phy-mode = "qsgmii";
131 buffer-manager = <&bm>;
132 bm,pool-long = <1>;
137 phy-mode = "qsgmii";
138 buffer-manager = <&bm>;
139 bm,pool-long = <2>;
144 phy-mode = "qsgmii";
145 buffer-manager = <&bm>;
146 bm,pool-long = <3>;
149 /* Front-side USB slot */
154 /* Back-side USB slot */
163 nand-controller@d0000 {
168 label = "pxa3xx_nand-0";
169 nand-rb = <0>;
170 nand-on-flash-bbt;
175 bm-bppi {
186 * standard PCIe slots on the board.
188 pcie@1,0 {
192 pcie@9,0 {
196 pcie@a,0 {
203 phy0: ethernet-phy@0 {
207 phy1: ethernet-phy@1 { label
211 phy2: ethernet-phy@2 {
215 phy3: ethernet-phy@3 {
224 #address-cells = <1>;
225 #size-cells = <1>;
226 compatible = "n25q128a13", "jedec,spi-nor";
228 spi-max-frequency = <108000000>;