Lines Matching +full:pcie +full:- +full:phy1
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
11 /include/ "p2020si-pre.dtsi"
66 fsl,espi-num-chipselects = <2>;
69 compatible = "atmel,at25df641", "jedec,spi-nor";
71 spi-max-frequency = <10000000>;
74 compatible = "atmel,at25df641", "jedec,spi-nor";
76 spi-max-frequency = <10000000>;
86 tbi-handle = <&tbi0>;
87 phy-handle = <&phy1>;
88 phy-connection-type = "rgmii-id";
92 phy1: ethernet-phy@1 { label
98 phy2: ethernet-phy@2 {
104 phy3: ethernet-phy@3 {
110 phy7: ethernet-phy@7 {
116 tbi0: tbi-phy@11 {
118 device_type = "tbi-phy";
123 tbi-handle = <&tbi1>;
124 phy-handle = <&phy7>;
125 phy-connection-type = "rgmii-id";
129 tbi1: tbi-phy@11 {
131 device_type = "tbi-phy";
136 tbi-handle = <&tbi2>;
137 phy-handle = <&phy3>;
138 phy-connection-type = "rgmii-id";
142 tbi2: tbi-phy@11 {
144 device_type = "tbi-phy";
164 clock-frequency = <1843200>;
172 clock-frequency = <1843200>;
180 clock-frequency = <1843200>;
188 clock-frequency = <1843200>;
193 compatible = "everspin,mram", "mtd-ram";
195 bank-width = <2>;
198 board-control@5,0 {
199 compatible = "artesyn,mvme2500-fpga";
204 compatible = "artesyn,mvme2500-cpld";
210 pci0: pcie@ffe08000 {
214 pcie@0 {
225 pci1: pcie@ffe09000 {
229 pcie@0 {
241 pci2: pcie@ffe0a000 {
245 pcie@0 {
257 /include/ "p2020si-post.dtsi"
270 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
271 non-removable;