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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epc.h>
15 #include "pcie-cadence.h"
22 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
30 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_get_fn_from_vfn()
31 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
32 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
33 fn = fn + first_vf_offset + ((vfn - 1) * stride); in cdns_pcie_get_fn_from_vfn()
[all …]
H A Dpcie-cadence-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence PCIe platform driver.
13 #include "pcie-cadence.h"
18 * struct cdns_plat_pcie - private data for this PCIe platform driver
19 * @pcie: Cadence PCIe controller
22 struct cdns_pcie *pcie; member
31 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
44 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()
46 struct cdns_pcie_ep *ep; in cdns_plat_pcie_probe() local
54 return -EINVAL; in cdns_plat_pcie_probe()
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H A Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
26 #include "pcie-cadence.h"
28 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
83 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
85 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
88 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
91 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
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/linux/drivers/pci/controller/
H A Dpcie-rcar-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 #include <linux/pci-epc.h>
17 #include "pcie-rcar.h"
21 /* Structure representing the PCIe interface */
23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
40 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
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H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
28 * @rockchip: Rockchip PCIe controller
37 * IRQ) TLP through the PCIe bus.
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/linux/drivers/pci/controller/dwc/
H A Dpci-layerscape-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
19 #include "pcie-designware.h"
24 /* PEX PFa PCIE PME and message interrupt registers*/
35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
52 static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_pcie_pf_lut_readl() argument
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl()
56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()
57 return ioread32be(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
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H A Dpcie-keembay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Intel Keem Bay
22 #include "pcie-designware.h"
72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
84 * Specification Revision 1.1, Table-2.4. in keembay_ep_reset_deassert()
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
10 bool "DesignWare PCIe debugfs entries"
14 Say Y here to enable debugfs entries for the PCIe controller. These
30 bool "Amazon Annapurna Labs PCIe controller"
36 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
37 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
39 required only for DT-based platforms. ACPI platforms with the
40 Annapurna Labs PCIe controller don't need to enable this.
43 bool "AMD MDB Versal2 PCIe controller"
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H A Dpcie-stm32-ep.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * STMicroelectronics STM32MP25 PCIe endpoint driver.
18 #include "pcie-designware.h"
19 #include "pcie-stm32.h"
31 static void stm32_pcie_ep_init(struct dw_pcie_ep *ep) in stm32_pcie_ep_init() argument
33 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in stm32_pcie_ep_init()
44 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, in stm32_pcie_enable_link()
55 regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LTSSM_EN, 0); in stm32_pcie_disable_link()
63 dev_dbg(pci->dev, "Enable link\n"); in stm32_pcie_start_link()
67 dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); in stm32_pcie_start_link()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
4 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
5 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
6 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
7 obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
8 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
9 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
10 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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H A Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Samsung Exynos SoCs
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
28 /* PCIe ELBI registers */
71 static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) in exynos_pcie_sideband_dbi_w_mode() argument
73 struct dw_pcie *pci = &ep->pci; in exynos_pcie_sideband_dbi_w_mode()
76 val = exynos_pcie_readl(pci->elbi_base, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
81 exynos_pcie_writel(pci->elbi_base, val, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
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H A Dpcie-designware.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Synopsys DesignWare PCIe host controller driver
17 #include <linux/dma-mapping.h>
23 #include <linux/pci-ecam.h>
26 #include <linux/pci-epc.h>
27 #include <linux/pci-epf.h>
31 /* DWC PCIe IP-core versions (native support since v4.70a) */
41 ((_pci)->version _op DW_PCIE_VER_ ## _ver)
55 /* DWC PCIe controller capabilities */
61 test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
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H A Dpcie-rcar-gen4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
4 * Copyright (C) 2022-2023 Renesas Electronics Corporation
6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
7 * provided, to initialize the PHY. Otherwise, the PCIe controller will not
24 #include "pcie-designware.h"
26 /* Renesas-specific */
27 /* PCIe Mode Setting Register 0 */
34 /* PCIe Interrupt Status 0 */
37 /* PCIe Interrupt Status 0 Enable */
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/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
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H A Drcar-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
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H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
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H A Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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H A Drcar-gen4-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Endpoint
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 - $ref: snps,dw-pcie-ep.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie-ep # R-Car S4-8
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H A Drockchip-dw-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
10 - Niklas Cassel <cassel@kernel.org>
13 RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
14 PCIe IP and thus inherits all the common properties defined in
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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H A Dcdns,cdns-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-ep.yaml#
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
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H A Daxis,artpec6-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
11 - Jesper Nilsson <jesper.nilsson@axis.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
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H A Dti,am65-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: pci-ep.yaml#
19 - ti,am654-pcie-ep
24 reg-names:
26 - const: app
[all …]
H A Dst,stm32-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32MP25 PCIe Endpoint
10 - Christian Bruel <christian.bruel@foss.st.com>
13 PCIe endpoint controller based on the Synopsys DesignWare PCIe core.
16 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
17 - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
21 const: st,stm32mp25-pcie-ep
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H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Endpoint
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
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/linux/drivers/phy/samsung/
H A Dphy-exynos-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series PCIe PHY driver
5 * Phy provider for PCIe controller on Exynos SoC series
7 * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
34 /* PMU PCIE PHY isolation control */
37 /* For Exynos pcie phy */
52 struct exynos_pcie_phy *ep = phy_get_drvdata(phy); in exynos5433_pcie_phy_init() local
54 regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, in exynos5433_pcie_phy_init()
56 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
58 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, in exynos5433_pcie_phy_init()
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