13f3f67cbSNiklas Cassel* Axis ARTPEC-6 PCIe interface 23f3f67cbSNiklas Cassel 33f3f67cbSNiklas CasselThis PCIe host controller is based on the Synopsys DesignWare PCIe IP 4*320e1098SMauro Carvalho Chehaband thus inherits all the common properties defined in snps,dw-pcie.yaml. 53f3f67cbSNiklas Cassel 63f3f67cbSNiklas CasselRequired properties: 7dff9cba6SNiklas Cassel- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; 8dff9cba6SNiklas Cassel "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; 94c3f9e9cSNiklas Cassel "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; 104c3f9e9cSNiklas Cassel "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; 113f3f67cbSNiklas Cassel- reg: base addresses and lengths of the PCIe controller (DBI), 1296291d56SBjorn Helgaas the PHY controller, and configuration address space. 133f3f67cbSNiklas Cassel- reg-names: Must include the following entries: 143f3f67cbSNiklas Cassel - "dbi" 153f3f67cbSNiklas Cassel - "phy" 163f3f67cbSNiklas Cassel - "config" 173f3f67cbSNiklas Cassel- interrupts: A list of interrupt outputs of the controller. Must contain an 183f3f67cbSNiklas Cassel entry for each entry in the interrupt-names property. 193f3f67cbSNiklas Cassel- interrupt-names: Must include the following entries: 203f3f67cbSNiklas Cassel - "msi": The interrupt that is asserted when an MSI is received 213f3f67cbSNiklas Cassel- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, 223f3f67cbSNiklas Cassel used to enable and control the Synopsys IP. 233f3f67cbSNiklas Cassel 243f3f67cbSNiklas CasselExample: 253f3f67cbSNiklas Cassel 263f3f67cbSNiklas Cassel pcie@f8050000 { 273f3f67cbSNiklas Cassel compatible = "axis,artpec6-pcie", "snps,dw-pcie"; 283f3f67cbSNiklas Cassel reg = <0xf8050000 0x2000 293f3f67cbSNiklas Cassel 0xf8040000 0x1000 30610e1283SNiklas Cassel 0xc0000000 0x2000>; 313f3f67cbSNiklas Cassel reg-names = "dbi", "phy", "config"; 323f3f67cbSNiklas Cassel #address-cells = <3>; 333f3f67cbSNiklas Cassel #size-cells = <2>; 343f3f67cbSNiklas Cassel device_type = "pci"; 353f3f67cbSNiklas Cassel /* downstream I/O */ 36610e1283SNiklas Cassel ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 373f3f67cbSNiklas Cassel /* non-prefetchable memory */ 38610e1283SNiklas Cassel 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; 393f3f67cbSNiklas Cassel num-lanes = <2>; 40610e1283SNiklas Cassel bus-range = <0x00 0xff>; 413f3f67cbSNiklas Cassel interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 423f3f67cbSNiklas Cassel interrupt-names = "msi"; 433f3f67cbSNiklas Cassel #interrupt-cells = <1>; 443f3f67cbSNiklas Cassel interrupt-map-mask = <0 0 0 0x7>; 453f3f67cbSNiklas Cassel interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 463f3f67cbSNiklas Cassel <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 473f3f67cbSNiklas Cassel <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 483f3f67cbSNiklas Cassel <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 493f3f67cbSNiklas Cassel axis,syscon-pcie = <&syscon>; 503f3f67cbSNiklas Cassel }; 51