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/linux/drivers/pci/hotplug/
H A Dpciehp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
26 #include "../pcie/portdrv.h"
35 #define ctrl_dbg(ctrl, format, arg...) \ argument
36 pci_dbg(ctrl->pcie->port, format, ## arg)
37 #define ctrl_err(ctrl, format, arg...) \ argument
38 pci_err(ctrl->pcie->port, format, ## arg)
39 #define ctrl_info(ctrl, format, arg...) \ argument
40 pci_info(ctrl->pcie->port, format, ## arg)
[all …]
H A Dpciehp_hpc.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
37 * assert presence detect--and those will still work, they will
49 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) in ctrl_dev() argument
51 return ctrl->pcie->port; in ctrl_dev()
58 static inline int pciehp_request_irq(struct controller *ctrl) in pciehp_request_irq() argument
60 int retval, irq = ctrl->pcie->irq; in pciehp_request_irq()
63 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl, in pciehp_request_irq()
64 "pciehp_poll-%s", in pciehp_request_irq()
[all …]
H A Dpciehp_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
25 * pciehp_configure_device() - enumerate PCI devices below a hotplug bridge
26 * @ctrl: PCIe hotplug controller
29 * Return 0 on success, %-EEXIST if the devices are already enumerated or
30 * %-ENODEV if enumeration failed.
32 int pciehp_configure_device(struct controller *ctrl) in pciehp_configure_device() argument
35 struct pci_dev *bridge = ctrl->pcie->port; in pciehp_configure_device()
36 struct pci_bus *parent = bridge->subordinate; in pciehp_configure_device()
[all …]
/linux/drivers/pci/controller/
H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
28 * @rockchip: Rockchip PCIe controller
37 * IRQ) TLP through the PCIe bus.
[all …]
H A Dpci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
30 * PCIe unit register offsets.
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
83 /* Structure representing all PCIe interfaces */
99 /* Structure representing one PCIe interface */
116 struct mvebu_pcie *pcie; member
130 writel(val, port->base + reg); in mvebu_writel()
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
[all …]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-layerscape-gen4.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
5 * Copyright 2019-2020 NXP
23 #include "pcie-mobiveil.h"
37 #define to_ls_g4_pcie(x) platform_get_drvdata((x)->pdev)
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
[all …]
H A Dmarvell,armada8k-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 7K/8K PCIe interface
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
13 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
20 - marvell,armada8k-pcie
22 - compatible
25 - $ref: snps,dw-pcie.yaml#
[all …]
H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
[all …]
/linux/drivers/pci/
H A Drebar.c1 // SPDX-License-Identifier: GPL-2.0
22 * pci_rebar_bytes_to_size - Convert size in bytes to PCI BAR Size
26 * (PCIe r6.2, sec. 7.8.6.3).
28 * Return: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
36 return max(ilog2(bytes), rebar_minsize) - rebar_minsize; in pci_rebar_bytes_to_size()
41 * pci_rebar_size_to_bytes - Convert encoded BAR Size to size in bytes
42 * @size: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
54 pdev->rebar_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); in pci_rebar_init()
58 * pci_rebar_find_pos - find position of resize control reg for BAR
65 * * %-ENOTSUPP if resizable BARs are not supported at all,
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-histb.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for HiSilicon STB SoCs
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
24 #include "pcie-designware.h"
26 #define to_histb_pcie(x) dev_get_drvdata((x)->dev)
62 void __iomem *ctrl; member
69 return readl(histb_pcie->ctrl + reg); in histb_pcie_readl()
74 writel(val, histb_pcie->ctrl + reg); in histb_pcie_writel()
110 histb_pcie_dbi_r_mode(&pci->pp, true); in histb_pcie_read_dbi()
112 histb_pcie_dbi_r_mode(&pci->pp, false); in histb_pcie_read_dbi()
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@kernel.org>
23 - Roger Quadros <rogerq@kernel.org>
28 - enum:
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-evm-pcie0-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
32 #address-cells = <2>;
33 #size-cells = <2>;
34 interrupt-parent = <&gic500>;
36 pcie0_ep: pcie-ep@2900000 {
[all …]
H A Dk3-am68-sk-base-board-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
4 * AM68-SK board.
6 * AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
[all …]
H A Dk3-j721s2-evm-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
30 interrupt-parent = <&gic500>;
32 pcie1_ep: pcie-ep@2910000 {
[all …]
H A Dk3-j7200-evm-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
30 interrupt-parent = <&gic500>;
32 pcie1_ep: pcie-ep@2910000 {
[all …]
H A Dk3-am642-evm-pcie0-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
30 interrupt-parent = <&gic500>;
32 pcie0_ep: pcie-ep@f102000 {
[all …]
H A Dk3-j721e-evm-pcie0-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
30 interrupt-parent = <&gic500>;
32 pcie0_ep: pcie-ep@2900000 {
[all …]
H A Dk3-j721e-evm-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
30 interrupt-parent = <&gic500>;
32 pcie1_ep: pcie-ep@2910000 {
[all …]
/linux/drivers/nvme/target/
H A Dpassthru.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Western Digital Corporation or its
7 * Copyright (c) 2019-2020, Eideticom Inc.
23 void nvmet_passthrough_override_cap(struct nvmet_ctrl *ctrl) in nvmet_passthrough_override_cap() argument
29 if (!nvme_multi_css(ctrl->subsys->passthru_ctrl)) in nvmet_passthrough_override_cap()
30 ctrl->cap &= ~(1ULL << 43); in nvmet_passthrough_override_cap()
35 struct nvmet_ctrl *ctrl = req->sq->ctrl; in nvmet_passthru_override_id_descs() local
42 if (!ctrl->subsys->clear_ids) in nvmet_passthru_override_id_descs()
59 if (cur->nidl == 0) in nvmet_passthru_override_id_descs()
62 if (cur->nidt == NVME_NIDT_CSI) { in nvmet_passthru_override_id_descs()
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-polarberry-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
[all …]
H A Dmpfs-m100pfs-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
17 pcie: pcie@2000000000 { label
[all …]

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