/freebsd/sys/contrib/device-tree/Bindings/pci/ |
H A D | pci-keystone.txt | 3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI 6 Documentation/devicetree/bindings/pci/designware-pcie.txt 8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt 12 Required Properties:- 14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC 15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC 16 reg: Three register ranges as listed in the reg-names property 17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the 22 interrupt-cells: should be set to 1 23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines [all …]
|
H A D | brcm,iproc-pcie.txt | 4 - compatible: 5 "brcm,iproc-pcie" for the first generation of PAXB based controller, 7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based 9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based 11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based 13 PAXB-based root complex is used for external endpoint devices. PAXC-based 15 - reg: base address and length of the PCIe controller I/O register space 16 - #interrupt-cells: set to <1> 17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the 19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller [all …]
|
H A D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link 17 - $ref: /schemas/pci/pci-bus.yaml# 21 const: mediatek,mt7621-pci 25 - description: host-pci bridge registers 26 - description: pcie port 0 RC control registers [all …]
|
H A D | renesas,pci-rcar-gen2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas AHB to PCI bridge 10 - Marek Vasut <marek.vasut+renesas@gmail.com> 11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 21 - items: 22 - enum: 23 - renesas,pci-r8a7742 # RZ/G1H [all …]
|
H A D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/brc [all...] |
H A D | qcom,pcie.txt | 1 * Qualcomm PCI express root complex 3 - compatible: 7 - "qcom,pcie-ipq8064" for ipq8064 8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 9 - "qcom,pcie-apq8064" for apq8064 10 - "qcom,pcie-apq8084" for apq8084 11 - "qcom,pcie-msm8996" for msm8996 or apq8096 12 - "qcom,pcie-ipq4019" for ipq4019 13 - "qcom,pcie-ipq8074" for ipq8074 14 - "qcom,pcie-qcs404" for qcs404 [all …]
|
H A D | mediatek-pcie.txt | 4 - compatible: Should contain one of the following strings: 5 "mediatek,mt2701-pcie" 6 "mediatek,mt2712-pcie" 7 "mediatek,mt7622-pcie" 8 "mediatek,mt7623-pcie" 9 "mediatek,mt7629-pcie" 10 "airoha,en7523-pcie" 11 - device_type: Must be "pci" 12 - reg: Base addresses and lengths of the root ports. 13 - reg-names: Names of the above areas to use during resource lookup. [all …]
|
H A D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/qco [all...] |
H A D | amlogic,axg-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <neil.armstrong@linaro.org> 13 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. 16 - $ref: /schemas/pci/pci-bus.yaml# 17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml# 19 # We need a select here so we don't match all nodes with 'snps,dw-pcie' 24 - amlogic,axg-pcie [all …]
|
H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schema [all...] |
H A D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be: 5 - "nvidia,tegra20-pcie": for Tegra20 6 - "nvidia,tegra30-pcie": for Tegra30 7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 8 - "nvidia,tegra210-pcie": for Tegra210 9 - "nvidia,tegra186-pcie": for Tegra186 10 - power-domains: To ungate power partition by BPMP powergate driver. Must 13 - device_type: Must be "pci" 14 - reg: A list of physical base address and length for each set of controller 15 registers. Must contain an entry for each entry in the reg-names property. [all …]
|
H A D | socionext,uniphier-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 PCI core. It shares common features with the PCIe DesignWare core and 13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 19 - $ref: /schemas/pci/snps,dw-pcie.yaml# 24 - socionext,uniphier-pcie 30 reg-names: [all …]
|
H A D | fsl,imx6q-pcie.txt | 4 and thus inherits all the common properties defined in designware-pcie.txt. 7 - compatible: 8 - "fsl,imx6q-pcie" 9 - "fsl,imx6sx-pcie", 10 - "fsl,imx6qp-pcie" 11 - "fsl,imx7d-pcie" 12 - "fsl,imx8mq-pcie" 13 - reg: base address and length of the PCIe controller 14 - interrupts: A list of interrupt outputs of the controller. Must contain an 15 entry for each entry in the interrupt-names property. [all …]
|
H A D | amlogic,meson-pcie.txt | 3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. 6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 11 - compatible: 13 - "amlogic,axg-pcie" for AXG SoC Family 14 - "amlogic,g12a-pcie" for G12A SoC Family 16 - reg: 18 - reg-names: Must be 19 - "elbi" External local bus interface registers 20 - "cfg" Meson specific registers 21 - "config" PCIe configuration space [all …]
|
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
H A D | mpc8641_hpcn_36b.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2008-2009 Freescale Semiconductor Inc. 8 /include/ "mpc8641si-pre.dtsi" 13 #address-cells = <2>; 14 #size-cells = <2>; 29 compatible = "cfi-flash"; 31 bank-width = <2>; 32 device-width = <2>; 33 #address-cells = <1>; 34 #size-cells = <1>; [all …]
|
H A D | mpc8641_hpcn.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 8 /include/ "mpc8641si-pre.dtsi" 27 compatible = "cfi-flash"; 29 bank-width = <2>; 30 device-width = <2>; 31 #address-cells = <1>; 32 #size-cells = <1>; 40 read-only; 49 read-only; 58 tbi-handle = <&tbi0>; [all …]
|
H A D | mpc8572ds.dtsi | 2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges) 37 #address-cells = <1>; 38 #size-cells = <1>; 39 compatible = "cfi-flash"; 41 bank-width = <2>; 42 device-width = <1>; 46 label = "ramdisk-nor"; 51 label = "diagnostic-nor"; 52 read-only; 57 label = "dink-nor"; [all …]
|
H A D | ppa8548.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * PPA8548 Device Tree Source (36-bit address map) 7 * MPC8548 CDS Device Tree Source (36-bit address map) 11 /include/ "mpc8548si-pre.dtsi" 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&mpic>; 34 pci0: pci@fe0008000 { 35 /* ppa8548 board doesn't support PCI */ 39 pci1: pci@fe0009000 { [all …]
|
H A D | p2020ds.dtsi | 2 * P2020DS Device Tree Source stub (no addresses or top-level ranges) 4 * Copyright 2011-2012 Freescale Semiconductor Inc. 37 #address-cells = <1>; 38 #size-cells = <1>; 39 compatible = "cfi-flash"; 41 bank-width = <2>; 42 device-width = <1>; 46 read-only; 51 read-only; 56 read-only; [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | mediatek,mt7621-pci-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/mediate [all...] |
/freebsd/sys/dev/le/ |
H A D | lancereg.h | 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause 34 /*- 70 * - Am7990 Local Area Network Controller for Ethernet (LANCE) 71 * (and its descendent Am79c90 C-LANCE). 73 * - Am79c900 Integrated Local Area Communications Controller (ILACC) 75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA 77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller 80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip 83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller [all …]
|
/freebsd/sys/dts/powerpc/ |
H A D | mpc8572ds.dts | 4 * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved 55 * MA 02110-1301, USA. 58 *------------------------------------------------------------------ 61 /dts-v1/; 65 #address-cells = <2>; 66 #size-cells = <2>; 81 #address-cells = <1>; 82 #size-cells = <0>; 87 d-cache-line-size = <32>; // 32 bytes 88 i-cache-line-size = <32>; // 32 bytes [all …]
|
/freebsd/sys/contrib/device-tree/src/mips/ralink/ |
H A D | mt7621.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 #include <dt-bindings/interrupt-controller/mips-gic.h> 3 #include <dt-binding [all...] |
/freebsd/sys/dev/bhnd/cores/pci/ |
H A D | bhnd_pcivar.h | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 40 * Shared PCI Bridge/PCI Host Bridge definitions. 56 int bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, 58 int bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, 60 int bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, 62 int bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, 65 /** PCI register block layouts. */ 67 BHND_PCI_REGFMT_PCI = 0, /* PCI register definitions */ 68 BHND_PCI_REGFMT_PCIE = 1, /* PCIe-Gen1 register definitions */ [all …]
|
H A D | bhnd_pci.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 34 * Broadcom Common PCI/PCIe Support. 79 BHND_PCI_DEV(PCI, "Host-PCI bridge", BHND_DF_HOSTB), 80 BHND_PCI_DEV(PCI, "PCI-BHND bridge", BHND_DF_SOC), 81 BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB), 82 BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC), 102 bhnd_bus_read_4((_sc)->mem_res, (_reg)) 104 bhnd_bus_write_4((_sc)->mem_res, (_reg), (_val)) 107 KASSERT(bhnd_get_class(sc->dev) == BHND_DEVCLASS_PCIE, \ [all …]
|