Lines Matching +full:pci +full:- +full:phy
4 * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved
55 * MA 02110-1301, USA.
58 *------------------------------------------------------------------
61 /dts-v1/;
65 #address-cells = <2>;
66 #size-cells = <2>;
81 #address-cells = <1>;
82 #size-cells = <0>;
87 d-cache-line-size = <32>; // 32 bytes
88 i-cache-line-size = <32>; // 32 bytes
89 d-cache-size = <0x8000>; // L1, 32K
90 i-cache-size = <0x8000>; // L1, 32K
91 timebase-frequency = <0>;
92 bus-frequency = <0>;
93 clock-frequency = <0>;
94 next-level-cache = <&L2>;
100 d-cache-line-size = <32>; // 32 bytes
101 i-cache-line-size = <32>; // 32 bytes
102 d-cache-size = <0x8000>; // L1, 32K
103 i-cache-size = <0x8000>; // L1, 32K
104 timebase-frequency = <0>;
105 bus-frequency = <0>;
106 clock-frequency = <0>;
107 next-level-cache = <&L2>;
116 #address-cells = <2>;
117 #size-cells = <1>;
118 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
121 interrupt-parent = <&mpic>;
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "cfi-flash";
130 bank-width = <2>;
131 device-width = <1>;
135 label = "ramdisk-nor";
136 read-only;
141 label = "diagnostic-nor";
142 read-only;
147 label = "dink-nor";
148 read-only;
153 label = "kernel-nor";
154 read-only;
159 label = "jffs2-nor";
164 label = "dtb-nor";
165 read-only;
170 label = "u-boot-nor";
171 read-only;
176 #address-cells = <1>;
177 #size-cells = <1>;
178 compatible = "fsl,mpc8572-fcm-nand",
179 "fsl,elbc-fcm-nand";
184 label = "u-boot-nand";
185 read-only;
190 label = "jffs2-nand";
195 label = "ramdisk-nand";
196 read-only;
201 label = "kernel-nand";
206 label = "dtb-nand";
207 read-only;
212 label = "reserved-nand";
217 compatible = "fsl,mpc8572-fcm-nand",
218 "fsl,elbc-fcm-nand";
223 compatible = "fsl,mpc8572-fcm-nand",
224 "fsl,elbc-fcm-nand";
229 compatible = "fsl,mpc8572-fcm-nand",
230 "fsl,elbc-fcm-nand";
236 #address-cells = <1>;
237 #size-cells = <1>;
239 compatible = "simple-bus";
241 bus-frequency = <0>; // Filled out by uboot.
243 ecm-law@0 {
244 compatible = "fsl,ecm-law";
246 fsl,num-laws = <12>;
250 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
253 interrupt-parent = <&mpic>;
256 memory-controller@2000 {
257 compatible = "fsl,mpc8572-memory-controller";
259 interrupt-parent = <&mpic>;
263 memory-controller@6000 {
264 compatible = "fsl,mpc8572-memory-controller";
266 interrupt-parent = <&mpic>;
270 L2: l2-cache-controller@20000 {
271 compatible = "fsl,mpc8572-l2-cache-controller";
273 cache-line-size = <32>; // 32 bytes
274 cache-size = <0x100000>; // L2, 1M
275 interrupt-parent = <&mpic>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 cell-index = <0>;
283 compatible = "fsl-i2c";
286 interrupt-parent = <&mpic>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 cell-index = <1>;
294 compatible = "fsl-i2c";
297 interrupt-parent = <&mpic>;
302 #address-cells = <1>;
303 #size-cells = <1>;
304 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
307 cell-index = <1>;
308 dma-channel@0 {
309 compatible = "fsl,mpc8572-dma-channel",
310 "fsl,eloplus-dma-channel";
312 cell-index = <0>;
313 interrupt-parent = <&mpic>;
316 dma-channel@80 {
317 compatible = "fsl,mpc8572-dma-channel",
318 "fsl,eloplus-dma-channel";
320 cell-index = <1>;
321 interrupt-parent = <&mpic>;
324 dma-channel@100 {
325 compatible = "fsl,mpc8572-dma-channel",
326 "fsl,eloplus-dma-channel";
328 cell-index = <2>;
329 interrupt-parent = <&mpic>;
332 dma-channel@180 {
333 compatible = "fsl,mpc8572-dma-channel",
334 "fsl,eloplus-dma-channel";
336 cell-index = <3>;
337 interrupt-parent = <&mpic>;
343 #address-cells = <1>;
344 #size-cells = <1>;
345 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
348 cell-index = <0>;
349 dma-channel@0 {
350 compatible = "fsl,mpc8572-dma-channel",
351 "fsl,eloplus-dma-channel";
353 cell-index = <0>;
354 interrupt-parent = <&mpic>;
357 dma-channel@80 {
358 compatible = "fsl,mpc8572-dma-channel",
359 "fsl,eloplus-dma-channel";
361 cell-index = <1>;
362 interrupt-parent = <&mpic>;
365 dma-channel@100 {
366 compatible = "fsl,mpc8572-dma-channel",
367 "fsl,eloplus-dma-channel";
369 cell-index = <2>;
370 interrupt-parent = <&mpic>;
373 dma-channel@180 {
374 compatible = "fsl,mpc8572-dma-channel",
375 "fsl,eloplus-dma-channel";
377 cell-index = <3>;
378 interrupt-parent = <&mpic>;
384 compatible = "fsl,gianfar-ptp-timer";
389 #address-cells = <1>;
390 #size-cells = <1>;
391 cell-index = <0>;
397 local-mac-address = [ 00 00 00 00 00 00 ];
399 interrupt-parent = <&mpic>;
400 tbi-handle = <&tbi0>;
401 phy-handle = <&phy0>;
402 ptimer-handle = < &ptp_timer >;
403 phy-connection-type = "rgmii-id";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 compatible = "fsl,gianfar-mdio";
411 phy0: ethernet-phy@0 {
412 interrupt-parent = <&mpic>;
416 phy1: ethernet-phy@1 {
417 interrupt-parent = <&mpic>;
421 phy2: ethernet-phy@2 {
422 interrupt-parent = <&mpic>;
426 phy3: ethernet-phy@3 {
427 interrupt-parent = <&mpic>;
432 tbi0: tbi-phy@11 {
434 device_type = "tbi-phy";
440 #address-cells = <1>;
441 #size-cells = <1>;
442 cell-index = <1>;
448 local-mac-address = [ 00 00 00 00 00 00 ];
450 interrupt-parent = <&mpic>;
451 tbi-handle = <&tbi1>;
452 phy-handle = <&phy1>;
453 ptimer-handle = < &ptp_timer >;
454 phy-connection-type = "rgmii-id";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "fsl,gianfar-tbi";
462 tbi1: tbi-phy@11 {
464 device_type = "tbi-phy";
470 #address-cells = <1>;
471 #size-cells = <1>;
472 cell-index = <2>;
478 local-mac-address = [ 00 00 00 00 00 00 ];
480 interrupt-parent = <&mpic>;
481 tbi-handle = <&tbi2>;
482 phy-handle = <&phy2>;
483 ptimer-handle = < &ptp_timer >;
484 phy-connection-type = "rgmii-id";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "fsl,gianfar-tbi";
492 tbi2: tbi-phy@11 {
494 device_type = "tbi-phy";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 cell-index = <3>;
508 local-mac-address = [ 00 00 00 00 00 00 ];
510 interrupt-parent = <&mpic>;
511 tbi-handle = <&tbi3>;
512 phy-handle = <&phy3>;
513 phy-connection-type = "rgmii-id";
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "fsl,gianfar-tbi";
521 tbi3: tbi-phy@11 {
523 device_type = "tbi-phy";
529 cell-index = <0>;
533 clock-frequency = <0>;
535 interrupt-parent = <&mpic>;
539 cell-index = <1>;
543 clock-frequency = <0>;
545 interrupt-parent = <&mpic>;
548 global-utilities@e0000 { //global utilities block
549 compatible = "fsl,mpc8572-guts";
551 fsl,has-rstcr;
555 compatible = "fsl,mpc8548-pmc";
560 compatible = "fsl,mpic-global-timer";
563 interrupt-parent = <&mpic>;
567 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
569 msi-available-ranges = <0 0x100>;
579 interrupt-parent = <&mpic>;
587 interrupt-parent = <&mpic>;
588 fsl,num-channels = <4>;
589 fsl,channel-fifo-len = <24>;
590 fsl,exec-units-mask = <0x9fe>;
591 fsl,descriptor-types-mask = <0x3ab0ebf>;
594 /* PME (pattern-matcher) */
600 interrupt-parent = <&mpic>;
604 interrupt-controller;
605 #address-cells = <0>;
606 #interrupt-cells = <2>;
608 compatible = "chrp,open-pic";
609 device_type = "open-pic";
614 compatible = "fsl,mpc8548-pcie";
615 device_type = "pci";
616 #interrupt-cells = <1>;
617 #size-cells = <2>;
618 #address-cells = <3>;
620 bus-range = <0 255>;
623 clock-frequency = <33333333>;
624 interrupt-parent = <&mpic>;
626 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
627 interrupt-map = <
628 /* IDSEL 0x11 func 0 - PCI slot 1 */
634 /* IDSEL 0x11 func 1 - PCI slot 1 */
640 /* IDSEL 0x11 func 2 - PCI slot 1 */
646 /* IDSEL 0x11 func 3 - PCI slot 1 */
652 /* IDSEL 0x11 func 4 - PCI slot 1 */
658 /* IDSEL 0x11 func 5 - PCI slot 1 */
664 /* IDSEL 0x11 func 6 - PCI slot 1 */
670 /* IDSEL 0x11 func 7 - PCI slot 1 */
676 /* IDSEL 0x12 func 0 - PCI slot 2 */
682 /* IDSEL 0x12 func 1 - PCI slot 2 */
688 /* IDSEL 0x12 func 2 - PCI slot 2 */
694 /* IDSEL 0x12 func 3 - PCI slot 2 */
700 /* IDSEL 0x12 func 4 - PCI slot 2 */
706 /* IDSEL 0x12 func 5 - PCI slot 2 */
712 /* IDSEL 0x12 func 6 - PCI slot 2 */
718 /* IDSEL 0x12 func 7 - PCI slot 2 */
745 #size-cells = <2>;
746 #address-cells = <3>;
747 device_type = "pci";
757 #size-cells = <2>;
758 #address-cells = <3>;
768 #interrupt-cells = <2>;
769 #size-cells = <1>;
770 #address-cells = <2>;
774 interrupt-parent = <&i8259>;
776 i8259: interrupt-controller@20 {
780 interrupt-controller;
781 device_type = "interrupt-controller";
782 #address-cells = <0>;
783 #interrupt-cells = <2>;
786 interrupt-parent = <&mpic>;
790 #size-cells = <0>;
791 #address-cells = <1>;
794 interrupt-parent =
823 compatible = "fsl,mpc8548-pcie";
824 device_type = "pci";
825 #interrupt-cells = <1>;
826 #size-cells = <2>;
827 #address-cells = <3>;
829 bus-range = <0 255>;
832 clock-frequency = <33333333>;
833 interrupt-parent = <&mpic>;
835 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
836 interrupt-map = <
845 #size-cells = <2>;
846 #address-cells = <3>;
847 device_type = "pci";
859 compatible = "fsl,mpc8548-pcie";
860 device_type = "pci";
861 #interrupt-cells = <1>;
862 #size-cells = <2>;
863 #address-cells = <3>;
865 bus-range = <0 255>;
868 clock-frequency = <33333333>;
869 interrupt-parent = <&mpic>;
871 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
872 interrupt-map = <
881 #size-cells = <2>;
882 #address-cells = <3>;
883 device_type = "pci";