Lines Matching +full:pci +full:- +full:phy

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   PCI core. It shares common features with the PCIe DesignWare core and
13   Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16   - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19   - $ref: /schemas/pci/snps,dw-pcie.yaml#
24       - socionext,uniphier-pcie
30   reg-names:
33       - const: dbi
34       - const: link
35       - const: config
36       - const: atu
44   num-viewport: true
46   num-lanes: true
51   phy-names:
52     const: pcie-phy
54   interrupt-controller:
59       interrupt-controller: true
61       '#interrupt-cells':
68   - compatible
69   - reg
70   - reg-names
71   - clocks
72   - resets
77   - |
79         gic: interrupt-controller {
80             interrupt-controller;
81             #interrupt-cells = <3>;
86         compatible = "socionext,uniphier-pcie";
87         reg-names = "dbi", "link", "config";
89         #address-cells = <3>;
90         #size-cells = <2>;
93         num-lanes = <1>;
94         num-viewport = <1>;
95         bus-range = <0x0 0xff>;
96         device_type = "pci";
99         phy-names = "pcie-phy";
101         #interrupt-cells = <1>;
102         interrupt-names = "dma", "msi";
103         interrupt-parent = <&gic>;
105         interrupt-map-mask = <0 0 0  7>;
106         interrupt-map = <0 0 0  1  &pcie_intc 0>,
111         pcie_intc: interrupt-controller {
112             interrupt-controller;
113             #interrupt-cells = <1>;
114             interrupt-parent = <&gic>;