Lines Matching +full:pci +full:- +full:phy
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "mediatek,mt7621-soc";
13 #address-cells = <1>;
14 #size-cells = <0>;
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
36 mmc_fixed_3v3: regulator-3v3 {
37 compatible = "regulator-fixed";
38 regulator-name = "mmc_power";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 enable-active-high;
42 regulator-always-on;
45 mmc_fixed_1v8_io: regulator-1v8 {
46 compatible = "regulator-fixed";
47 regulator-name = "mmc_io";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 enable-active-high;
51 regulator-always-on;
59 #address-cells = <1>;
60 #size-cells = <1>;
63 compatible = "mediatek,mt7621-sysc", "syscon";
65 #clock-cells = <1>;
66 #reset-cells = <1>;
68 clock-output-names = "xtal", "cpu", "bus",
74 compatible = "mediatek,mt7621-wdt";
80 #gpio-cells = <2>;
81 #interrupt-cells = <2>;
82 compatible = "mediatek,mt7621-gpio";
83 gpio-controller;
84 gpio-ranges = <&pinctrl 0 0 95>;
85 interrupt-controller;
87 interrupt-parent = <&gic>;
92 compatible = "mediatek,mt7621-i2c";
96 clock-names = "i2c";
98 reset-names = "i2c";
100 #address-cells = <1>;
101 #size-cells = <0>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&i2c_pins>;
109 memc: memory-controller@5000 {
110 compatible = "mediatek,mt7621-memc", "syscon";
120 interrupt-parent = <&gic>;
123 reg-shift = <2>;
124 reg-io-width = <4>;
125 no-loopback-test;
131 compatible = "ralink,mt7621-spi";
135 clock-names = "spi";
138 reset-names = "spi";
140 #address-cells = <1>;
141 #size-cells = <0>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&spi_pins>;
149 compatible = "ralink,mt7621-pinctrl";
151 i2c_pins: i2c0-pins {
158 spi_pins: spi0-pins {
165 uart1_pins: uart1-pins {
172 uart2_pins: uart2-pins {
179 uart3_pins: uart3-pins {
186 rgmii1_pins: rgmii1-pins {
193 rgmii2_pins: rgmii2-pins {
200 mdio_pins: mdio0-pins {
207 pcie_pins: pcie0-pins {
214 nand_pins: nand0-pins {
215 spi-pinmux {
220 sdhci-pinmux {
226 sdhci_pins: sdhci0-pins {
237 compatible = "mediatek,mt7620-mmc";
240 bus-width = <4>;
241 max-frequency = <48000000>;
242 cap-sd-highspeed;
243 cap-mmc-highspeed;
244 vmmc-supply = <&mmc_fixed_3v3>;
245 vqmmc-supply = <&mmc_fixed_1v8_io>;
246 disable-wp;
248 pinctrl-names = "default", "state_uhs";
249 pinctrl-0 = <&sdhci_pins>;
250 pinctrl-1 = <&sdhci_pins>;
254 clock-names = "source", "hclk";
256 interrupt-parent = <&gic>;
261 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
264 reg-names = "mac", "ippc";
267 clock-names = "sys_ck";
269 interrupt-parent = <&gic>;
273 gic: interrupt-controller@1fbc0000 {
277 interrupt-controller;
278 #interrupt-cells = <3>;
280 mti,reserved-cpu-vectors = <7>;
283 compatible = "mti,gic-timer";
290 compatible = "mti,mips-cpc";
295 compatible = "mti,mips-cdmm";
300 compatible = "mediatek,mt7621-eth";
304 clock-names = "fe", "ethif";
306 #address-cells = <1>;
307 #size-cells = <0>;
310 reset-names = "fe", "eth";
312 interrupt-parent = <&gic>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
321 compatible = "mediatek,eth-mac";
323 phy-mode = "trgmii";
325 fixed-link {
327 full-duplex;
333 compatible = "mediatek,eth-mac";
335 phy-mode = "rgmii";
337 fixed-link {
339 full-duplex;
344 mdio: mdio-bus {
345 #address-cells = <1>;
346 #size-cells = <0>;
353 reset-names = "mcm";
354 interrupt-controller;
355 #interrupt-cells = <1>;
359 #address-cells = <1>;
360 #size-cells = <0>;
395 phy-mode = "rgmii";
397 fixed-link {
399 full-duplex;
407 phy-mode = "trgmii";
409 fixed-link {
411 full-duplex;
421 compatible = "mediatek,mt7621-pci";
422 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
426 #address-cells = <3>;
427 #size-cells = <2>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pcie_pins>;
432 device_type = "pci";
434 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
437 #interrupt-cells = <1>;
438 interrupt-map-mask = <0xF800 0 0 0>;
439 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
445 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
449 #address-cells = <3>;
450 #size-cells = <2>;
451 device_type = "pci";
452 #interrupt-cells = <1>;
453 interrupt-map-mask = <0 0 0 0>;
454 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
458 phy-names = "pcie-phy0";
464 #address-cells = <3>;
465 #size-cells = <2>;
466 device_type = "pci";
467 #interrupt-cells = <1>;
468 interrupt-map-mask = <0 0 0 0>;
469 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
473 phy-names = "pcie-phy1";
479 #address-cells = <3>;
480 #size-cells = <2>;
481 device_type = "pci";
482 #interrupt-cells = <1>;
483 interrupt-map-mask = <0 0 0 0>;
484 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
488 phy-names = "pcie-phy2";
493 pcie0_phy: pcie-phy@1e149000 {
494 compatible = "mediatek,mt7621-pci-phy";
497 #phy-cells = <1>;
500 pcie2_phy: pcie-phy@1e14a000 {
501 compatible = "mediatek,mt7621-pci-phy";
504 #phy-cells = <1>;