Lines Matching +full:pci +full:- +full:phy
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
16 - reg-names: Must include the following entries:
20 - interrupts: A list of interrupt outputs of the controller. Must contain an
21 entry for each entry in the interrupt-names property.
22 - interrupt-names: Must include the following entries:
25 - bus-range: Range of bus numbers associated with this controller
26 - #address-cells: Address representation for root ports (must be 3)
27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
31 - cell 2 contains the lower 32 address bits and is used to translate to the
33 - #size-cells: Size representation for root ports (must be 2)
34 - ranges: Describes the translation of addresses for root ports and standard
35 PCI regions. The entries must be 6 cells each, where the first three cells
36 correspond to the address as described for the #address-cells property
38 fifth and six cells are as described for the #size-cells property above.
39 - The first two entries are expected to translate the addresses for the root
40 port registers, which are referenced by the assigned-addresses property of
42 - The remaining entries setup the mapping for the standard I/O, memory and
43 prefetchable PCI regions. The first cell determines the type of region
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
48 Please refer to the standard PCI bus binding document for a more detailed
50 - #interrupt-cells: Size representation for interrupts (must be 1)
51 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
52 Please refer to the standard PCI bus binding document for a more detailed
54 - clocks: Must contain an entry for each entry in clock-names.
55 See ../clocks/clock-bindings.txt for details.
56 - clock-names: Must include the following entries:
57 - pex
58 - afi
59 - pll_e
60 - cml (not required for Tegra20)
61 - resets: Must contain an entry for each entry in reset-names.
63 - reset-names: Must include the following entries:
64 - pex
65 - afi
66 - pcie_x
69 - pinctrl-names: A list of pinctrl state names. Must contain the following
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
73 - pinctrl-0: phandle for the default/active state of pin configurations.
74 - pinctrl-1: phandle for the idle state of pin configurations.
77 - phys: Must contain an entry for each entry in phy-names.
78 - phy-names: Must include the following entries:
79 - pcie
81 These properties are deprecated in favour of per-lane PHYs define in each of
85 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
86 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
87 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
89 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
91 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
94 - Required:
95 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
97 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
99 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
101 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
103 - Optional:
104 - If lanes 0 to 3 are used:
105 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
106 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
107 - If lanes 4 or 5 are used:
108 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
109 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
112 - Required:
113 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
114 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
115 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
117 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
118 supply 2.8-3.3 V.
121 - Required:
122 - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
124 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
125 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
129 - Required:
130 - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
131 - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
133 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
135 - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
141 - device_type: Must be "pci"
142 - assigned-addresses: Address and size of the port configuration registers
143 - reg: PCI bus address of the root port
144 - #address-cells: Must be 3
145 - #size-cells: Must be 2
146 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
154 - phys: Must contain an phandle to a PHY for each entry in phy-names.
155 - phy-names: Must include an entry for each active lane. Note that the number
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
164 --------
168 pcie-controller@80003000 {
169 compatible = "nvidia,tegra20-pcie";
170 device_type = "pci";
174 reg-names = "pads", "afi", "cs";
177 interrupt-names = "intr", "msi";
179 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 0>;
181 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
183 bus-range = <0x00 0xff>;
184 #address-cells = <3>;
185 #size-cells = <2>;
190 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
194 clock-names = "pex", "afi", "pll_e";
196 reset-names = "pex", "afi", "pcie_x";
199 pci@1,0 {
200 device_type = "pci";
201 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
205 #address-cells = <3>;
206 #size-cells = <2>;
210 nvidia,num-lanes = <2>;
213 pci@2,0 {
214 device_type = "pci";
215 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
219 #address-cells = <3>;
220 #size-cells = <2>;
224 nvidia,num-lanes = <2>;
230 pcie-controller@80003000 {
233 vdd-supply = <&pci_vdd_reg>;
234 pex-clk-supply = <&pci_clk_reg>;
237 pci@1,0 {
241 pci@0,0 {
244 #address-cells = <3>;
245 #size-cells = <2>;
247 device_type = "pci";
250 pci@0,0 {
257 Note that devices on the PCI bus are dynamically discovered using PCI's bus
259 if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
265 --------
269 pcie-controller@3000 {
270 compatible = "nvidia,tegra30-pcie";
271 device_type = "pci";
275 reg-names = "pads", "afi", "cs";
278 interrupt-names = "intr", "msi";
280 #interrupt-cells = <1>;
281 interrupt-map-mask = <0 0 0 0>;
282 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
284 bus-range = <0x00 0xff>;
285 #address-cells = <3>;
286 #size-cells = <2>;
292 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
299 clock-names = "pex", "afi", "pll_e", "cml";
303 reset-names = "pex", "afi", "pcie_x";
306 pci@1,0 {
307 device_type = "pci";
308 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
312 #address-cells = <3>;
313 #size-cells = <2>;
316 nvidia,num-lanes = <2>;
319 pci@2,0 {
320 device_type = "pci";
321 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
325 #address-cells = <3>;
326 #size-cells = <2>;
329 nvidia,num-lanes = <2>;
332 pci@3,0 {
333 device_type = "pci";
334 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
338 #address-cells = <3>;
339 #size-cells = <2>;
342 nvidia,num-lanes = <2>;
348 pcie-controller@3000 {
351 avdd-pexa-supply = <&ldo1_reg>;
352 vdd-pexa-supply = <&ldo1_reg>;
353 avdd-pexb-supply = <&ldo1_reg>;
354 vdd-pexb-supply = <&ldo1_reg>;
355 avdd-pex-pll-supply = <&ldo1_reg>;
356 avdd-plle-supply = <&ldo1_reg>;
357 vddio-pex-ctl-supply = <&sys_3v3_reg>;
358 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
360 pci@1,0 {
364 pci@3,0 {
370 ---------
374 pcie-controller@1003000 {
375 compatible = "nvidia,tegra124-pcie";
376 device_type = "pci";
380 reg-names = "pads", "afi", "cs";
383 interrupt-names = "intr", "msi";
385 #interrupt-cells = <1>;
386 interrupt-map-mask = <0 0 0 0>;
387 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
389 bus-range = <0x00 0xff>;
390 #address-cells = <3>;
391 #size-cells = <2>;
396 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
403 clock-names = "pex", "afi", "pll_e", "cml";
407 reset-names = "pex", "afi", "pcie_x";
410 pci@1,0 {
411 device_type = "pci";
412 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
416 #address-cells = <3>;
417 #size-cells = <2>;
420 nvidia,num-lanes = <2>;
423 pci@2,0 {
424 device_type = "pci";
425 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
429 #address-cells = <3>;
430 #size-cells = <2>;
433 nvidia,num-lanes = <1>;
439 pcie-controller@1003000 {
442 avddio-pex-supply = <&vdd_1v05_run>;
443 dvddio-pex-supply = <&vdd_1v05_run>;
444 avdd-pex-pll-supply = <&vdd_1v05_run>;
445 hvdd-pex-supply = <&vdd_3v3_lp0>;
446 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
447 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
448 avdd-pll-erefe-supply = <&avdd_1v05_run>;
451 pci@1,0 {
452 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
453 phy-names = "pcie-0";
458 pci@2,0 {
459 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
460 phy-names = "pcie-0";
466 ---------
470 pcie-controller@1003000 {
471 compatible = "nvidia,tegra210-pcie";
472 device_type = "pci";
476 reg-names = "pads", "afi", "cs";
479 interrupt-names = "intr", "msi";
481 #interrupt-cells = <1>;
482 interrupt-map-mask = <0 0 0 0>;
483 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
485 bus-range = <0x00 0xff>;
486 #address-cells = <3>;
487 #size-cells = <2>;
492 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
499 clock-names = "pex", "afi", "pll_e", "cml";
503 reset-names = "pex", "afi", "pcie_x";
506 pci@1,0 {
507 device_type = "pci";
508 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
512 #address-cells = <3>;
513 #size-cells = <2>;
516 nvidia,num-lanes = <4>;
519 pci@2,0 {
520 device_type = "pci";
521 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
525 #address-cells = <3>;
526 #size-cells = <2>;
529 nvidia,num-lanes = <1>;
535 pcie-controller@1003000 {
538 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
539 hvddio-pex-supply = <&vdd_1v8>;
540 dvddio-pex-supply = <&vdd_pex_1v05>;
541 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
542 hvdd-pex-pll-e-supply = <&vdd_1v8>;
543 vddio-pex-ctl-supply = <&vdd_1v8>;
545 pci@1,0 {
546 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
547 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
548 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
549 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
550 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
554 pci@2,0 {
555 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
556 phy-names = "pcie-0";
562 ---------
567 compatible = "nvidia,tegra186-pcie";
568 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
569 device_type = "pci";
573 reg-names = "pads", "afi", "cs";
577 interrupt-names = "intr", "msi";
579 #interrupt-cells = <1>;
580 interrupt-map-mask = <0 0 0 0>;
581 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
583 bus-range = <0x00 0xff>;
584 #address-cells = <3>;
585 #size-cells = <2>;
591 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
597 clock-names = "afi", "pex", "pll_e";
602 reset-names = "afi", "pex", "pcie_x";
606 pci@1,0 {
607 device_type = "pci";
608 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
612 #address-cells = <3>;
613 #size-cells = <2>;
616 nvidia,num-lanes = <2>;
619 pci@2,0 {
620 device_type = "pci";
621 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
625 #address-cells = <3>;
626 #size-cells = <2>;
629 nvidia,num-lanes = <1>;
632 pci@3,0 {
633 device_type = "pci";
634 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
638 #address-cells = <3>;
639 #size-cells = <2>;
642 nvidia,num-lanes = <1>;
651 dvdd-pex-supply = <&vdd_pex>;
652 hvdd-pex-pll-supply = <&vdd_1v8>;
653 hvdd-pex-supply = <&vdd_1v8>;
654 vddio-pexctl-aud-supply = <&vdd_1v8>;
656 pci@1,0 {
657 nvidia,num-lanes = <4>;
661 pci@2,0 {
662 nvidia,num-lanes = <0>;
666 pci@3,0 {
667 nvidia,num-lanes = <1>;