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/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
23 geography of a PCI bus address by concatenating the various components to
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
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/linux/drivers/pci/controller/
H A Dpci-host-generic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Simple, generic PCI host controller driver targeting firmware-initialised
4 * systems and virtual machines (e.g. the PCI emulation provided by kvmtool).
14 #include <linux/pci-ecam.h>
17 #include "pci-host-common.h"
30 struct pci_config_window *cfg = bus->sysdata; in pci_dw_valid_device()
33 * The Synopsys DesignWare PCIe controller in ECAM mode will not filter in pci_dw_valid_device()
38 if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) in pci_dw_valid_device()
62 { .compatible = "pci-host-cam-generic",
65 { .compatible = "pci-host-ecam-generic",
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_CADENCE) += cadence/
3 obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
4 obj-$(CONFIG_PCI_IXP4XX) += pci-ixp4xx.o
5 obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
6 obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o
7 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
8 obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
9 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
10 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "PCI controller drivers"
4 depends on PCI
18 Add support for Aardvark 64bit PCIe Host Controller. This
52 system-on-chips, like the Apple M1. This is required for the USB
53 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
58 bool "ARM Versatile PB PCI controller"
70 Say Y here to enable PCIe host controller support for
88 through the generic platform bus interface
111 bool "Cavium Thunder PCIe controller to off-chip devices"
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H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
9 * Bits taken from Synopsys DesignWare Host controller driver and
10 * ARM PCI Host generic driver.
15 #include <linux/irqchip/irq-msi-lib.h>
24 #include <linux/pci.h>
25 #include <linux/pci-ecam.h>
28 #include "../pci.h"
95 * struct xilinx_pcie - PCIe port information
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H A Dpci-hyperv.c1 // SPDX-License-Identifier: GPL-2.0
8 * This driver acts as a paravirtual front-end for PCI Express root buses.
9 * When a PCI Express function (either an entire device or an SR-IOV
11 * a new bus to the guest VM. This is modeled as a root PCI bus because
13 * VM within Hyper-V, there may seem to be no PCI bus at all in the VM
16 * Each root PCI bus has its own PCI domain, which is called "Segment" in
17 * the PCI Firmware Specifications. Thus while each device passed through
18 * to the VM using this front-end will appear at "device 0", the domain will
19 * be unique. Typically, each bus will have one PCI function on it, though
24 * MSI or MSI-X) associated with the functions on the bus. As interrupts are
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H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
26 #include <linux/pci.h>
27 #include <linux/pci-ecam.h>
36 #include "../pci.h"
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
173 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
201 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
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/linux/Documentation/PCI/
H A Dacpi-info.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ACPI considerations for PCI host bridges
10 For example, there's no standard hardware mechanism for enumerating PCI
11 host bridges, so the ACPI namespace must describe each host bridge, the
12 method for accessing PCI config space below it, the address space windows
13 the host bridge forwards to PCI (using _CRS), and the routing of legacy
16 PCI devices, which are below the host bridge, generally do not need to be
17 described via ACPI. The OS can discover them via the standard PCI
19 devices and read and size their BARs. However, ACPI may describe PCI
25 namespace [2]. The _CRS is like a generalized PCI BAR: the OS can read
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/linux/drivers/pci/controller/dwc/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
4 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
5 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
6 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
7 obj-$(CONFIG_PCIE_AMD_MDB) += pcie-amd-mdb.o
8 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
9 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
10 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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H A Dpcie-designware-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
14 #include <linux/irqchip/irq-msi-lib.h>
22 #include "../../pci.h"
23 #include "pcie-designware.h"
43 .prefix = "DW-",
54 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in dw_handle_msi_irq() local
56 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; in dw_handle_msi_irq()
59 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + in dw_handle_msi_irq()
69 generic_handle_domain_irq(pp->irq_domain, in dw_handle_msi_irq()
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/linux/arch/arm64/boot/dts/arm/
H A Dmorello-sdp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
6 /dts-v1/;
11 compatible = "arm,morello-sdp", "arm,morello";
18 stdout-path = "serial0:115200n8";
21 dpu_aclk: clock-350000000 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <350000000>;
26 clock-output-names = "aclk";
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H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 #address-cells = <1>;
14 #size-cells = <1>;
18 frame-number = <1>;
30 #mbox-cells = <1>;
32 clock-names = "apb_pclk";
36 compatible = "arm,mmu-400", "arm,smmu-v1";
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H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2013-2016 Broadcom
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
28 enable-method = "psci";
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/linux/arch/xtensa/boot/dts/
H A Dvirt.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "cdns,xtensa-iss";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&pic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 compatible = "cdns,xtensa-cpu";
31 #clock-cells = <0>;
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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64v_4core_virtio.dts1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
5 /dts-v1/;
7 compatible = "loongson,loongson64v-4core-virtio";
8 #address-cells = <2>;
9 #size-cells = <2>;
11 cpuintc: interrupt-controller {
12 #address-cells = <0>;
13 #interrupt-cells = <1>;
14 interrupt-controller;
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/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
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/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-soc.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 /include/ "amd-seattle-clks.dtsi"
16 gic0: interrupt-controller@e1101000 {
17 compatible = "arm,gic-400", "arm,cortex-a15-gic";
18 interrupt-controller;
19 #interrupt-cells = <3>;
20 #address-cells = <2>;
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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