non\-cacheable (full) in projects: linux

Searched +full:non +full:- +full:cacheable (Results 1 – 25 of 139) sorted by relevance

/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re… 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee… 18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed… 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." 46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and… 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", 91 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 258 "BriefDescription": "Total Page Table Walks on I-side.", [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee… 18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed… 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 90 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 197 "BriefDescription": "Total Page Table Walks on I-side.", 215 "BriefDescription": "Total Page Table Walks on D-side.", 262 … the processor core. Software PREFETCH instruction saw a match on an already-allocated miss reques…
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	cache.json	7 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 16 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 27 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 36 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 45 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
H A D	other.json	3 … where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 7 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX… 16 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct… 25 …running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). … 123 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 203 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 213 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 283 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 293 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 363 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hav… [all …]
/linux/arch/riscv/include/asm/
H A D	pgtable-64.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 23 #define PGDIR_MASK (~(PGDIR_SIZE - 1)) 25 / p4d is folded into pgd in case of 4-level page table / 32 #define P4D_MASK (~(P4D_SIZE - 1)) 34 / pud is folded into pgd in case of 3-level page table */ 37 #define PUD_MASK (~(PUD_SIZE - 1)) 42 #define PMD_MASK (~(PMD_SIZE - 1)) 98 for (order = NAPOT_ORDER_MAX - 1; \ 99 order >= NAPOT_CONT_ORDER_BASE; order--) 104 #define napot_cont_mask(order) (~(napot_cont_size(order) - 1UL)) [all …]`
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	memory.json	`30 "PublicDescription": "External memory request to non-cacheable memory", 33 "BriefDescription": "External memory request to non-cacheable memory"`
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	15 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 24 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 35 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 53 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 62 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	cache.json	15 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 24 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 35 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 53 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 62 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
/linux/Documentation/devicetree/bindings/pmem/
H A D	pmem-region.txt	`1 Device-tree bindings for persistent memory regions 2 ----------------------------------------------------- 6 a) Usable as main system memory (i.e. cacheable), and 16 ----------------------------- 19 - compatible = "pmem-region" 21 - reg = <base, size>; 25 (i.e cacheable). 33 - Any relevant NUMA associativity properties for the target platform. 35 - volatile; This property indicates that this region is actually 36 backed by non-persistent memory. This lets the OS know that it [all …]`
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	cache.json	15 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 24 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 35 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 44 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 53 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	cache.json	24 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L… 63 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 67 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C… 72 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 76 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca… 81 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 85 …che or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 90 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 94 …nstruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", 117 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	24 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L… 63 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 67 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C… 72 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 76 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca… 81 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 85 …che or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 90 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 94 …nstruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", 117 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	cache.json	7 "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 116 "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", 320 "BriefDescription": "Core-originate [all...]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	cache.json	16 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 26 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 38 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 58 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 68 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
/linux/arch/m68k/include/asm/
H A D	m54xxacr.h	1 /* SPDX-License-Identifier: GPL-2.0 / 47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) 51 #define ICACHE_SIZE 0x4000 / instruction - 16k / 52 #define DCACHE_SIZE 0x2000 / data - 8k / 56 #define ICACHE_SIZE 0x8000 / instruction - 32k / 57 #define DCACHE_SIZE 0x8000 / data - 32k / 61 #define ICACHE_SIZE 0x2000 / instruction - 8k / 62 #define DCACHE_SIZE 0x2000 / data - 8k */ 68 #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) 69 #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	cache.json	7 "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 116 "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", 320 "BriefDescription": "Core-originate [all...]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	cache.json	16 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 26 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 38 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 48 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 58 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
/linux/tools/arch/powerpc/include/asm/
H A D	barrier.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 15 providing an ordering (separately) for (a) cacheable stores and (b) 16 * loads and stores to non-cacheable memory (e.g. I/O devices).`
/linux/arch/powerpc/include/asm/
H A D	barrier.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 8 #include <asm/asm-const.h> 11 #include <asm/ppc-opcode.h> 19 providing an ordering (separately) for (a) cacheable stores and (b) 20 * loads and stores to non-cacheable memory (e.g. I/O devices). 30 * For the smp_ barriers, ordering is for cacheable memory operations 36 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. 42 /* The sub-arch has lwsync */ 117 #include <asm-generic/barrier.h>`
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	cache.json	7 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 16 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 27 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 36 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 45 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
/linux/arch/powerpc/include/asm/nohash/32/
H A D	pte-85xx.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 14 - PRESENT must* be in the bottom two bits because swap PTEs use 19 /* Definitions for FSL Book-E Cores / 45 cacheable kernel and user pages) and one for non cacheable 56 #include <asm/pgtable-masks.h>`
/linux/arch/sparc/include/asm/
H A D	viking.h	1 /* SPDX-License-Identifier: GPL-2.0 / 18 ----------------------------------------------------------- 19 * \|impl-vers\| RSV \|TC\|AC\|SP\|BM\|PC\|MBM\|SB\|IC\|DC\|PSO\|RSV\|NF\|ME\| 20 * ----------------------------------------------------------- 21 * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0 23 * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache 24 * 1 = Twalks are cacheable in E-cache 26 * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present 28 * for machines lacking an E-cache (ie. in MBUS mode) this bit must 31 * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable [all …]

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Project(s)	No entries found freebsd illumos-gate linux titanic_41 titanic_44 titanic_50 titanic_51 titanic_52

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