1ddc141e5SOliver O'HalloranDevice-tree bindings for persistent memory regions 2ddc141e5SOliver O'Halloran----------------------------------------------------- 3ddc141e5SOliver O'Halloran 4ddc141e5SOliver O'HalloranPersistent memory refers to a class of memory devices that are: 5ddc141e5SOliver O'Halloran 6ddc141e5SOliver O'Halloran a) Usable as main system memory (i.e. cacheable), and 7ddc141e5SOliver O'Halloran b) Retain their contents across power failure. 8ddc141e5SOliver O'Halloran 9ddc141e5SOliver O'HalloranGiven b) it is best to think of persistent memory as a kind of memory mapped 10ddc141e5SOliver O'Halloranstorage device. To ensure data integrity the operating system needs to manage 11ddc141e5SOliver O'Halloranpersistent regions separately to the normal memory pool. To aid with that this 12ddc141e5SOliver O'Halloranbinding provides a standardised interface for discovering where persistent 13ddc141e5SOliver O'Halloranmemory regions exist inside the physical address space. 14ddc141e5SOliver O'Halloran 15ddc141e5SOliver O'HalloranBindings for the region nodes: 16ddc141e5SOliver O'Halloran----------------------------- 17ddc141e5SOliver O'Halloran 18ddc141e5SOliver O'HalloranRequired properties: 19ddc141e5SOliver O'Halloran - compatible = "pmem-region" 20ddc141e5SOliver O'Halloran 21ddc141e5SOliver O'Halloran - reg = <base, size>; 22*47aab533SBjorn Helgaas The reg property should specify an address range that is 23ddc141e5SOliver O'Halloran translatable to a system physical address range. This address 24ddc141e5SOliver O'Halloran range should be mappable as normal system memory would be 25ddc141e5SOliver O'Halloran (i.e cacheable). 26ddc141e5SOliver O'Halloran 27ddc141e5SOliver O'Halloran If the reg property contains multiple address ranges 28ddc141e5SOliver O'Halloran each address range will be treated as though it was specified 29ddc141e5SOliver O'Halloran in a separate device node. Having multiple address ranges in a 30ddc141e5SOliver O'Halloran node implies no special relationship between the two ranges. 31ddc141e5SOliver O'Halloran 32ddc141e5SOliver O'HalloranOptional properties: 33*47aab533SBjorn Helgaas - Any relevant NUMA associativity properties for the target platform. 34ddc141e5SOliver O'Halloran 35ddc141e5SOliver O'Halloran - volatile; This property indicates that this region is actually 36ddc141e5SOliver O'Halloran backed by non-persistent memory. This lets the OS know that it 37ddc141e5SOliver O'Halloran may skip the cache flushes required to ensure data is made 38ddc141e5SOliver O'Halloran persistent after a write. 39ddc141e5SOliver O'Halloran 40ddc141e5SOliver O'Halloran If this property is absent then the OS must assume that the region 41ddc141e5SOliver O'Halloran is backed by non-volatile memory. 42ddc141e5SOliver O'Halloran 43ddc141e5SOliver O'HalloranExamples: 44ddc141e5SOliver O'Halloran-------------------- 45ddc141e5SOliver O'Halloran 46ddc141e5SOliver O'Halloran /* 47ddc141e5SOliver O'Halloran * This node specifies one 4KB region spanning from 48ddc141e5SOliver O'Halloran * 0x5000 to 0x5fff that is backed by non-volatile memory. 49ddc141e5SOliver O'Halloran */ 50ddc141e5SOliver O'Halloran pmem@5000 { 51ddc141e5SOliver O'Halloran compatible = "pmem-region"; 52ddc141e5SOliver O'Halloran reg = <0x00005000 0x00001000>; 53ddc141e5SOliver O'Halloran }; 54ddc141e5SOliver O'Halloran 55ddc141e5SOliver O'Halloran /* 56ddc141e5SOliver O'Halloran * This node specifies two 4KB regions that are backed by 57ddc141e5SOliver O'Halloran * volatile (normal) memory. 58ddc141e5SOliver O'Halloran */ 59ddc141e5SOliver O'Halloran pmem@6000 { 60ddc141e5SOliver O'Halloran compatible = "pmem-region"; 61ddc141e5SOliver O'Halloran reg = < 0x00006000 0x00001000 62ddc141e5SOliver O'Halloran 0x00008000 0x00001000 >; 63ddc141e5SOliver O'Halloran volatile; 64ddc141e5SOliver O'Halloran }; 65ddc141e5SOliver O'Halloran 66