Lines Matching +full:non +full:- +full:cacheable

5 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re…
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
105     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
111 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
134     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
140 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable…
146     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
152 …fDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cache…
158 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
164     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
170     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
206 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
212 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
218 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
224 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
230 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
236 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
242 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
248 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
254 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
260 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
266 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…