Lines Matching +full:non +full:- +full:cacheable

5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable…
76     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
82 …fDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cache…
88 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
94     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
100     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
136 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
148 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
154 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
166 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
172 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
178 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
184 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
190 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
196 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
226 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re…
275 … instruction stream was being modified by another processor in an MP system - typically a highly u…
292 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
298 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
304 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…