1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /*
3a439fe51SSam Ravnborg * viking.h: Defines specific to the GNU/Viking MBUS module.
4a439fe51SSam Ravnborg * This is SRMMU stuff.
5a439fe51SSam Ravnborg *
6a439fe51SSam Ravnborg * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7a439fe51SSam Ravnborg */
8a439fe51SSam Ravnborg #ifndef _SPARC_VIKING_H
9a439fe51SSam Ravnborg #define _SPARC_VIKING_H
10a439fe51SSam Ravnborg
11a439fe51SSam Ravnborg #include <asm/asi.h>
12a439fe51SSam Ravnborg #include <asm/mxcc.h>
13*8e958839SWill Deacon #include <asm/pgtable.h>
14a439fe51SSam Ravnborg #include <asm/pgtsrmmu.h>
15a439fe51SSam Ravnborg
16a439fe51SSam Ravnborg /* Bits in the SRMMU control register for GNU/Viking modules.
17a439fe51SSam Ravnborg *
18a439fe51SSam Ravnborg * -----------------------------------------------------------
19a439fe51SSam Ravnborg * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
20a439fe51SSam Ravnborg * -----------------------------------------------------------
21a439fe51SSam Ravnborg * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
22a439fe51SSam Ravnborg *
23a439fe51SSam Ravnborg * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
24a439fe51SSam Ravnborg * 1 = Twalks are cacheable in E-cache
25a439fe51SSam Ravnborg *
26a439fe51SSam Ravnborg * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
27a439fe51SSam Ravnborg * and never caches them internally (or so states the docs). Therefore
28a439fe51SSam Ravnborg * for machines lacking an E-cache (ie. in MBUS mode) this bit must
29a439fe51SSam Ravnborg * remain cleared.
30a439fe51SSam Ravnborg *
31a439fe51SSam Ravnborg * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
32a439fe51SSam Ravnborg * 1 = Passthru physical accesses cacheable
33a439fe51SSam Ravnborg *
34a439fe51SSam Ravnborg * This indicates whether accesses are cacheable when no cachable bit
35a439fe51SSam Ravnborg * is present in the pte when the processor is in boot-mode or the
36a439fe51SSam Ravnborg * access does not need pte's for translation (ie. pass-thru ASI's).
37a439fe51SSam Ravnborg * "Cachable" is only referring to E-cache (if present) and not the
38a439fe51SSam Ravnborg * on chip split I/D caches of the GNU/Viking.
39a439fe51SSam Ravnborg *
40a439fe51SSam Ravnborg * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
41a439fe51SSam Ravnborg *
42a439fe51SSam Ravnborg * This enables snooping on the GNU/Viking bus. This must be on
43a439fe51SSam Ravnborg * for the hardware cache consistency mechanisms of the GNU/Viking
44a439fe51SSam Ravnborg * to work at all. On non-mxcc GNU/Viking modules the split I/D
45a439fe51SSam Ravnborg * caches will snoop regardless of whether they are enabled, this
46a439fe51SSam Ravnborg * takes care of the case where the I or D or both caches are turned
47a439fe51SSam Ravnborg * off yet still contain valid data. Note also that this bit does
48a439fe51SSam Ravnborg * not affect GNU/Viking store-buffer snoops, those happen if the
49a439fe51SSam Ravnborg * store-buffer is enabled no matter what.
50a439fe51SSam Ravnborg *
51a439fe51SSam Ravnborg * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
52a439fe51SSam Ravnborg *
53a439fe51SSam Ravnborg * This indicates whether the GNU/Viking is in boot-mode or not,
54a439fe51SSam Ravnborg * if it is then all instruction fetch physical addresses are
55a439fe51SSam Ravnborg * computed as 0xff0000000 + low 28 bits of requested address.
56a439fe51SSam Ravnborg * GNU/Viking boot-mode does not affect data accesses. Also,
57a439fe51SSam Ravnborg * in boot mode instruction accesses bypass the split on chip I/D
58a439fe51SSam Ravnborg * caches, they may be cached by the GNU/MXCC if present and enabled.
59a439fe51SSam Ravnborg *
60a439fe51SSam Ravnborg * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
61a439fe51SSam Ravnborg *
62a439fe51SSam Ravnborg * This indicated the GNU/Viking configuration present. If in
63a439fe51SSam Ravnborg * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
64a439fe51SSam Ravnborg * not then the GNU/Viking is on a module VBUS connected directly
65a439fe51SSam Ravnborg * to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
66a439fe51SSam Ravnborg * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
67a439fe51SSam Ravnborg *
68a439fe51SSam Ravnborg * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
69a439fe51SSam Ravnborg *
70a439fe51SSam Ravnborg * The GNU/Viking store buffer allows the chip to continue execution
71a439fe51SSam Ravnborg * after a store even if the data cannot be placed in one of the
72a439fe51SSam Ravnborg * caches during that cycle. If disabled, all stores operations
73a439fe51SSam Ravnborg * occur synchronously.
74a439fe51SSam Ravnborg *
75a439fe51SSam Ravnborg * IC: Instruction Cache -- 0 = off, 1 = on
76a439fe51SSam Ravnborg * DC: Data Cache -- 0 = off, 1 = 0n
77a439fe51SSam Ravnborg *
78a439fe51SSam Ravnborg * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
79a439fe51SSam Ravnborg * as mentioned above, these caches will snoop the bus in GNU/MBUS
80a439fe51SSam Ravnborg * configurations even when disabled to avoid data corruption.
81a439fe51SSam Ravnborg *
82a439fe51SSam Ravnborg * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
83a439fe51SSam Ravnborg * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
84a439fe51SSam Ravnborg *
85a439fe51SSam Ravnborg */
86a439fe51SSam Ravnborg
87a439fe51SSam Ravnborg #define VIKING_MMUENABLE 0x00000001
88a439fe51SSam Ravnborg #define VIKING_NOFAULT 0x00000002
89a439fe51SSam Ravnborg #define VIKING_PSO 0x00000080
90a439fe51SSam Ravnborg #define VIKING_DCENABLE 0x00000100 /* Enable data cache */
91a439fe51SSam Ravnborg #define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
92a439fe51SSam Ravnborg #define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
93a439fe51SSam Ravnborg #define VIKING_MMODE 0x00000800 /* MBUS mode */
94a439fe51SSam Ravnborg #define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
95a439fe51SSam Ravnborg #define VIKING_BMODE 0x00002000
96a439fe51SSam Ravnborg #define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
97a439fe51SSam Ravnborg #define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
98a439fe51SSam Ravnborg #define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
99a439fe51SSam Ravnborg #define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
100a439fe51SSam Ravnborg
101a439fe51SSam Ravnborg /*
102a439fe51SSam Ravnborg * GNU/Viking Breakpoint Action Register fields.
103a439fe51SSam Ravnborg */
104a439fe51SSam Ravnborg #define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
105a439fe51SSam Ravnborg
106a439fe51SSam Ravnborg /*
107a439fe51SSam Ravnborg * GNU/Viking Cache Tags.
108a439fe51SSam Ravnborg */
109a439fe51SSam Ravnborg #define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
110a439fe51SSam Ravnborg #define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
111a439fe51SSam Ravnborg #define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
112a439fe51SSam Ravnborg
113a439fe51SSam Ravnborg #ifndef __ASSEMBLY__
114a439fe51SSam Ravnborg
viking_flush_icache(void)115a439fe51SSam Ravnborg static inline void viking_flush_icache(void)
116a439fe51SSam Ravnborg {
117a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
118a439fe51SSam Ravnborg : /* no outputs */
119a439fe51SSam Ravnborg : "i" (ASI_M_IC_FLCLEAR)
120a439fe51SSam Ravnborg : "memory");
121a439fe51SSam Ravnborg }
122a439fe51SSam Ravnborg
viking_flush_dcache(void)123a439fe51SSam Ravnborg static inline void viking_flush_dcache(void)
124a439fe51SSam Ravnborg {
125a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
126a439fe51SSam Ravnborg : /* no outputs */
127a439fe51SSam Ravnborg : "i" (ASI_M_DC_FLCLEAR)
128a439fe51SSam Ravnborg : "memory");
129a439fe51SSam Ravnborg }
130a439fe51SSam Ravnborg
viking_unlock_icache(void)131a439fe51SSam Ravnborg static inline void viking_unlock_icache(void)
132a439fe51SSam Ravnborg {
133a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
134a439fe51SSam Ravnborg : /* no outputs */
135a439fe51SSam Ravnborg : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
136a439fe51SSam Ravnborg : "memory");
137a439fe51SSam Ravnborg }
138a439fe51SSam Ravnborg
viking_unlock_dcache(void)139a439fe51SSam Ravnborg static inline void viking_unlock_dcache(void)
140a439fe51SSam Ravnborg {
141a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
142a439fe51SSam Ravnborg : /* no outputs */
143a439fe51SSam Ravnborg : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
144a439fe51SSam Ravnborg : "memory");
145a439fe51SSam Ravnborg }
146a439fe51SSam Ravnborg
viking_set_bpreg(unsigned long regval)147a439fe51SSam Ravnborg static inline void viking_set_bpreg(unsigned long regval)
148a439fe51SSam Ravnborg {
149a439fe51SSam Ravnborg __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
150a439fe51SSam Ravnborg : /* no outputs */
151a439fe51SSam Ravnborg : "r" (regval), "i" (ASI_M_ACTION)
152a439fe51SSam Ravnborg : "memory");
153a439fe51SSam Ravnborg }
154a439fe51SSam Ravnborg
viking_get_bpreg(void)155a439fe51SSam Ravnborg static inline unsigned long viking_get_bpreg(void)
156a439fe51SSam Ravnborg {
157a439fe51SSam Ravnborg unsigned long regval;
158a439fe51SSam Ravnborg
159a439fe51SSam Ravnborg __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
160a439fe51SSam Ravnborg : "=r" (regval)
161a439fe51SSam Ravnborg : "i" (ASI_M_ACTION));
162a439fe51SSam Ravnborg return regval;
163a439fe51SSam Ravnborg }
164a439fe51SSam Ravnborg
viking_get_dcache_ptag(int set,int block,unsigned long * data)165a439fe51SSam Ravnborg static inline void viking_get_dcache_ptag(int set, int block,
166a439fe51SSam Ravnborg unsigned long *data)
167a439fe51SSam Ravnborg {
168a439fe51SSam Ravnborg unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
169a439fe51SSam Ravnborg 0x80000000;
170a439fe51SSam Ravnborg unsigned long info, page;
171a439fe51SSam Ravnborg
172a439fe51SSam Ravnborg __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
173a439fe51SSam Ravnborg "or %%g0, %%g2, %0\n\t"
174a439fe51SSam Ravnborg "or %%g0, %%g3, %1\n\t"
175a439fe51SSam Ravnborg : "=r" (info), "=r" (page)
176a439fe51SSam Ravnborg : "r" (ptag), "i" (ASI_M_DATAC_TAG)
177a439fe51SSam Ravnborg : "g2", "g3");
178a439fe51SSam Ravnborg data[0] = info;
179a439fe51SSam Ravnborg data[1] = page;
180a439fe51SSam Ravnborg }
181a439fe51SSam Ravnborg
viking_mxcc_turn_off_parity(unsigned long * mregp,unsigned long * mxcc_cregp)182a439fe51SSam Ravnborg static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
183a439fe51SSam Ravnborg unsigned long *mxcc_cregp)
184a439fe51SSam Ravnborg {
185a439fe51SSam Ravnborg unsigned long mreg = *mregp;
186a439fe51SSam Ravnborg unsigned long mxcc_creg = *mxcc_cregp;
187a439fe51SSam Ravnborg
188a439fe51SSam Ravnborg mreg &= ~(VIKING_PCENABLE);
189a439fe51SSam Ravnborg mxcc_creg &= ~(MXCC_CTL_PARE);
190a439fe51SSam Ravnborg
191a439fe51SSam Ravnborg __asm__ __volatile__ ("set 1f, %%g2\n\t"
192a439fe51SSam Ravnborg "andcc %%g2, 4, %%g0\n\t"
193a439fe51SSam Ravnborg "bne 2f\n\t"
194a439fe51SSam Ravnborg " nop\n"
195a439fe51SSam Ravnborg "1:\n\t"
196a439fe51SSam Ravnborg "sta %0, [%%g0] %3\n\t"
197a439fe51SSam Ravnborg "sta %1, [%2] %4\n\t"
198a439fe51SSam Ravnborg "b 1f\n\t"
199a439fe51SSam Ravnborg " nop\n\t"
200a439fe51SSam Ravnborg "nop\n"
201a439fe51SSam Ravnborg "2:\n\t"
202a439fe51SSam Ravnborg "sta %0, [%%g0] %3\n\t"
203a439fe51SSam Ravnborg "sta %1, [%2] %4\n"
204a439fe51SSam Ravnborg "1:\n\t"
205a439fe51SSam Ravnborg : /* no output */
206a439fe51SSam Ravnborg : "r" (mreg), "r" (mxcc_creg),
207a439fe51SSam Ravnborg "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
208a439fe51SSam Ravnborg "i" (ASI_M_MXCC)
209a439fe51SSam Ravnborg : "g2", "memory", "cc");
210a439fe51SSam Ravnborg *mregp = mreg;
211a439fe51SSam Ravnborg *mxcc_cregp = mxcc_creg;
212a439fe51SSam Ravnborg }
213a439fe51SSam Ravnborg
viking_hwprobe(unsigned long vaddr)214a439fe51SSam Ravnborg static inline unsigned long viking_hwprobe(unsigned long vaddr)
215a439fe51SSam Ravnborg {
216a439fe51SSam Ravnborg unsigned long val;
217a439fe51SSam Ravnborg
218a439fe51SSam Ravnborg vaddr &= PAGE_MASK;
219a439fe51SSam Ravnborg /* Probe all MMU entries. */
220a439fe51SSam Ravnborg __asm__ __volatile__("lda [%1] %2, %0\n\t"
221a439fe51SSam Ravnborg : "=r" (val)
222a439fe51SSam Ravnborg : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
223a439fe51SSam Ravnborg if (!val)
224a439fe51SSam Ravnborg return 0;
225a439fe51SSam Ravnborg
226a439fe51SSam Ravnborg /* Probe region. */
227a439fe51SSam Ravnborg __asm__ __volatile__("lda [%1] %2, %0\n\t"
228a439fe51SSam Ravnborg : "=r" (val)
229a439fe51SSam Ravnborg : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
230a439fe51SSam Ravnborg if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
231*8e958839SWill Deacon vaddr &= ~PGDIR_MASK;
232a439fe51SSam Ravnborg vaddr >>= PAGE_SHIFT;
233a439fe51SSam Ravnborg return val | (vaddr << 8);
234a439fe51SSam Ravnborg }
235a439fe51SSam Ravnborg
236a439fe51SSam Ravnborg /* Probe segment. */
237a439fe51SSam Ravnborg __asm__ __volatile__("lda [%1] %2, %0\n\t"
238a439fe51SSam Ravnborg : "=r" (val)
239a439fe51SSam Ravnborg : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
240a439fe51SSam Ravnborg if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
241*8e958839SWill Deacon vaddr &= ~PMD_MASK;
242a439fe51SSam Ravnborg vaddr >>= PAGE_SHIFT;
243a439fe51SSam Ravnborg return val | (vaddr << 8);
244a439fe51SSam Ravnborg }
245a439fe51SSam Ravnborg
246a439fe51SSam Ravnborg /* Probe page. */
247a439fe51SSam Ravnborg __asm__ __volatile__("lda [%1] %2, %0\n\t"
248a439fe51SSam Ravnborg : "=r" (val)
249a439fe51SSam Ravnborg : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
250a439fe51SSam Ravnborg return val;
251a439fe51SSam Ravnborg }
252a439fe51SSam Ravnborg
253a439fe51SSam Ravnborg #endif /* !__ASSEMBLY__ */
254a439fe51SSam Ravnborg
255a439fe51SSam Ravnborg #endif /* !(_SPARC_VIKING_H) */
256