| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio-mux-mmioreg.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
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| H A D | mdio-mux-mmioreg.txt | 1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected. The mdio-mux
5 node must be a child of the memory-mapped device. The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
16 - mux-mask : integer, contains an eight-bit mask that specifies which
18 'reg' property of each child mdio-mux node must be constrained by
19 this mask.
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | mmp3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
[all …]
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| H A D | mmp2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | keystone-pll.txt | 9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
24 compatible = "ti,keystone,main-pll-clock";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mux/ |
| H A D | reg-mux.txt | 1 Generic register bitfield-based multiplexer controller bindings
7 - compatible : should be one of
8 "reg-mux" : if parent device of mux controller is not syscon device
9 "mmio-mux" : if parent device of mux controller is syscon device
10 - #mux-control-cells : <1>
11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
12 pairs, each describing a single mux control.
13 * Standard mux-controller bindings as decribed in mux-controller.txt
16 - idle-states : if present, the state the muxes will have when idle. The
20 bitfield described by the corresponding register offset and bitfield mask
[all …]
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| H A D | reg-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
[all …]
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| H A D | atmel,at91rm9200-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manikandan Muralidharan <manikandan.m@microchip.com>
22 - items:
23 - enum:
24 - atmel,at91rm9200-pinctrl
25 - atmel,at91sam9x5-pinctrl
26 - atmel,sama5d3-pinctrl
[all …]
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| H A D | atmel,at91-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
24 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
46 From the datasheet Table 10-2.
84 - atmel,pins: 4 integers array, represents a group of pins mux and config
91 MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
[all …]
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| H A D | pinctrl-single.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
[all …]
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| /freebsd/sys/arm/mv/clk/ |
| H A D | periph.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
97 .clk_def.full_dd.gate.mask = 0x1, \
131 .clk_def.full_d.gate.mask = 0x1, \
173 .clk_def.gate.gate.mask = 0x1, \
219 .clk_def.mux_gate.mux.clkdef.name = _mux_name, \
220 .clk_def.mux_gate.mux.offset = TBG_SEL, \
221 .clk_def.mux_gate.mux.shift = _mux_shift, \
222 .clk_def.mux_gate.mux.width = 0x1, \
223 .clk_def.mux_gate.mux.mux_flags = 0x0, \
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | mrvl,intc.txt | 4 - compatible : Should be
5 "mrvl,mmp-intc" on Marvel MMP,
6 "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
7 "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
8 - reg : Address and length of the register set of the interrupt controller.
10 of the whole interrupt controller. The "marvell,mmp3-intc" controller
12 controller is mux-intc, address and length means one register. Since
13 address of mux-intc is in the range of intc. mux-intc is secondary
15 - reg-names : Name of the register set of the interrupt controller. It's
16 only required in mux-intc interrupt controller.
[all …]
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| H A D | mrvl,intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
14 - if:
19 const: marvell,orion-intc
22 - mrvl,intc-nr-irqs
23 - if:
[all …]
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| H A D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
20 - not all bits within the interrupt controller actually map to an interrupt
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
27 \-----------\
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
[all …]
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| H A D | brcm,bcm7120-l2-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
[all...] |
| /freebsd/sys/dev/ath/ath_hal/ar5416/ |
| H A D | ar5416_gpio.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
32 * Configure GPIO Output Mux control
43 /* each MUX controls 6 GPIO pins */ in cfgOutputMux()
52 * 5 bits per GPIO pin. Bits 0..4 for 1st pin in that mux, in cfgOutputMux()
90 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); in ar5416GpioCfgOutput()
110 * Convert HAL signal type definitions to hardware-specific values. in ar5416GpioCfgOutput()
113 ath_hal_printf(ah, "%s: mux %d is invalid!\n", in ar5416GpioCfgOutput()
[all …]
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_gpio.c | 33 * Configure GPIO Output Mux control
87 /* each MUX controls 6 GPIO pins */ in ar9300_gpio_cfg_output_mux()
98 * Bits 0..4 for 1st pin in that mux, in ar9300_gpio_cfg_output_mux()
163 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); in ar9300_gpio_cfg_output()
170 /* Convert HAL signal type definitions to hardware-specific values. */ in ar9300_gpio_cfg_output()
222 /* Configure the MUX */ in ar9300_gpio_cfg_output()
237 * Configure GPIO Output lines -LED off
287 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); in ar9300_gpio_cfg_output_led_off()
289 /* Convert HAL signal type definitions to hardware-specific values. */ in ar9300_gpio_cfg_output_led_off()
325 // Configure the MUX in ar9300_gpio_cfg_output_led_off()
[all …]
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| H A D | ar9300reg.h | 32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
51 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue…
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
109 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
148 #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale
152 #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout
156 #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout
[all …]
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| /freebsd/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_per.c | 1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
213 /* bank L -> 0-31 */
241 /* bank H -> 32-63 */
270 /* bank U -> 64-95 */
299 /* bank V -> 96-127 */
325 /* bank W -> 128-159*/
354 /* bank X -> 160-191*/
403 /* Mux with fractional 8.1 divider. */
407 /* Mux with fractional 16.1 divider. */
[all …]
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| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_per.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 #include <dt-bindings/clock/tegra210-car.h>
40 #include <dt-bindings/reset/tegra210-car.h>
308 /* bank L -> 0-31 */
332 /* bank H -> 32-63 */
353 /* bank U -> 64-95 */
378 /* bank V -> 96-127 */
398 /* bank W -> 128-159*/
425 /* bank X -> 160-191*/
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
| H A D | mux.txt | 1 Binding for TI mux clock.
4 register-mapped multiplexer with multiple input clock signals or
22 "index-starts-at-one" modified the scheme as follows:
29 The binding must provide the register to control the mux. Optionally
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38 - #clock-cells : from common clock binding; shall be set to 0.
39 - clocks : link phandles of parent clocks
40 - reg : register offset for register controlling adjustable mux
43 - clock-output-names : from common clock binding.
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
55 #define AR_IMR 0x00a0 /* Primary interrupt mask register */
56 #define AR_IMR_S0 0x00a4 /* Secondary interrupt mask reg 0 */
57 #define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */
58 #define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */
59 #define AR_IMR_S3 0x00b0 /* Secondary interrupt mask reg 3 */
60 #define AR_IMR_S4 0x00b4 /* Secondary interrupt mask reg 4 */
[all …]
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| /freebsd/sys/dev/qcom_clk/ |
| H A D | qcom_clk_rcg2.c | 1 /*-
52 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_CFG_REG)
54 ((sc)->cmd_rcgr + QCOM_CLK_RCG2_CMD_REG)
56 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_M_REG)
58 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_N_REG)
60 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_D_REG)
88 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
91 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
99 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
108 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
52 #define AR_IMR 0x00a0 /* MAC Primary interrupt mask register */
53 #define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */
54 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */
55 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */
56 #define AR_IMR_S3 0x00b0 /* MAC Secondary interrupt mask register 3 */
57 #define AR_IMR_S4 0x00b4 /* MAC Secondary interrupt mask register 4 */
[all …]
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