Lines Matching +full:mux +full:- +full:mask
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
52 #define AR_IMR 0x00a0 /* MAC Primary interrupt mask register */
53 #define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */
54 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */
55 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */
56 #define AR_IMR_S3 0x00b0 /* MAC Secondary interrupt mask register 3 */
57 #define AR_IMR_S4 0x00b4 /* MAC Secondary interrupt mask register 4 */
58 #define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */
59 /* Shadow copies with read-and-clear access */
73 #define AR_DCM_A 0x0400 /* Decompression mask address */
74 #define AR_DCM_D 0x0404 /* Decompression mask data */
97 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
99 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
157 #define AR_D0_QCUMASK 0x1000 /* MAC QCU Mask */
158 #define AR_D1_QCUMASK 0x1004 /* MAC QCU Mask */
159 #define AR_D2_QCUMASK 0x1008 /* MAC QCU Mask */
160 #define AR_D3_QCUMASK 0x100c /* MAC QCU Mask */
161 #define AR_D4_QCUMASK 0x1010 /* MAC QCU Mask */
162 #define AR_D5_QCUMASK 0x1014 /* MAC QCU Mask */
163 #define AR_D6_QCUMASK 0x1018 /* MAC QCU Mask */
164 #define AR_D7_QCUMASK 0x101c /* MAC QCU Mask */
165 #define AR_D8_QCUMASK 0x1020 /* MAC QCU Mask */
166 #define AR_D9_QCUMASK 0x1024 /* MAC QCU Mask */
169 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
170 #define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */
171 #define AR_D2_LCL_IFS 0x1048 /* MAC DCU-specific IFS settings */
172 #define AR_D3_LCL_IFS 0x104c /* MAC DCU-specific IFS settings */
173 #define AR_D4_LCL_IFS 0x1050 /* MAC DCU-specific IFS settings */
174 #define AR_D5_LCL_IFS 0x1054 /* MAC DCU-specific IFS settings */
175 #define AR_D6_LCL_IFS 0x1058 /* MAC DCU-specific IFS settings */
176 #define AR_D7_LCL_IFS 0x105c /* MAC DCU-specific IFS settings */
177 #define AR_D8_LCL_IFS 0x1060 /* MAC DCU-specific IFS settings */
178 #define AR_D9_LCL_IFS 0x1064 /* MAC DCU-specific IFS settings */
205 #define AR_D0_MISC 0x1100 /* MAC Miscellaneous DCU-specific settings */
206 #define AR_D1_MISC 0x1104 /* MAC Miscellaneous DCU-specific settings */
207 #define AR_D2_MISC 0x1108 /* MAC Miscellaneous DCU-specific settings */
208 #define AR_D3_MISC 0x110c /* MAC Miscellaneous DCU-specific settings */
209 #define AR_D4_MISC 0x1110 /* MAC Miscellaneous DCU-specific settings */
210 #define AR_D5_MISC 0x1114 /* MAC Miscellaneous DCU-specific settings */
211 #define AR_D6_MISC 0x1118 /* MAC Miscellaneous DCU-specific settings */
212 #define AR_D7_MISC 0x111c /* MAC Miscellaneous DCU-specific settings */
213 #define AR_D8_MISC 0x1120 /* MAC Miscellaneous DCU-specific settings */
214 #define AR_D9_MISC 0x1124 /* MAC Miscellaneous DCU-specific settings */
219 /* MAC DCU-global IFS settings */
241 #define AR_QSM 0x402C /* QCU sleep mask */
253 #define AR_STA_ID0 0x8000 /* MAC station ID0 register - low 32 bits */
254 #define AR_STA_ID1 0x8004 /* MAC station ID1 register - upper 16 bits */
257 #define AR_SLOT_TIME 0x8010 /* MAC Time-out after a collision */
258 #define AR_TIME_OUT 0x8014 /* MAC ACK & CTS time-out */
276 #define AR_QOS_MASK 0x805c /* MAC AES mute mask: QoS field */
277 #define AR_SEQ_MASK 0x8060 /* MAC AES mute mask: seqnum field */
292 #define AR_BSSMSKL 0x80e0 /* BSSID mask lower 32 bits */
293 #define AR_BSSMSKU 0x80e4 /* BSSID mask upper 16 bits */
325 #define AR_PHYCNTMASK1 0x8130 /* Phy Error 1 counter mask */
327 #define AR_PHYCNTMASK2 0x8138 /* Phy Error 2 counter mask */
329 #define AR_MIBCNT_INTRMASK (3<<22) /* Mask for top two bits of counters */
331 #define AR_RATE_DURATION_0 0x8700 /* base of multi-rate retry */
337 #define AR_CFP_MASK 0x0000ffff /* Mask for next beacon time */
341 #define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
348 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
352 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 /* Mask of PCI core master request queue full thr…
367 #define AR_FTRIG 0x000003F0 /* Mask for Frame trigger level */
375 #define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
382 #define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
384 #define AR_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
386 #define AR_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
387 #define AR_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */
391 #define AR_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
393 #define AR_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
395 #define AR_MACMISC_DMA_OBS 0x000001E0 /* Mask for DMA observation bus mux select */
396 #define AR_MACMISC_DMA_OBS_S 5 /* Shift for DMA observation bus mux select */
397 #define AR_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */
398 #define AR_MACMISC_MISC_OBS_S 9 /* Shift for MISC observation bus mux select */
399 #define AR_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
400 #define AR_MACMISC_MAC_OBS_BUS_LSB_S 12 /* Shift for MAC observation bus mux select (lsb) */
401 #define AR_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
402 #define AR_MACMISC_MAC_OBS_BUS_MSB_S 15 /* Shift for MAC observation bus mux select (msb) */
409 * the secondary interrupt status/mask registers control what bits
413 * and IMR_P is non-zero. The secondary interrupt mask/status
429 #define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
432 #define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
449 #define AR_ISR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
451 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
454 #define AR_ISR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
456 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
459 #define AR_ISR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
472 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
473 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
475 #define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
479 * Interrupt Mask Registers
483 * mask registers control what bits get set in the primary
499 #define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
502 #define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
517 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* TXOK (QCU 0-9) */
519 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* TXDESC (QCU 0-9) */
522 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* TXERR (QCU 0-9) */
524 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* TXEOL (QCU 0-9) */
527 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
547 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
548 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
549 #define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
551 #define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
555 #define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
567 #define AR_Q_CBRCFG_CBR_INTERVAL 0x00FFFFFF /* Mask for CBR interval (us) */
569 #define AR_Q_CBRCFG_CBR_OVF_THRESH 0xFF000000 /* Mask for CBR overflow threshold */
575 /* bits 25-31 are reserved */
577 #define AR_Q_MISC_FSP 0x0000000F /* Frame Scheduling Policy mask */
582 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
597 #define AR_Q_STS_PEND_FR_CNT 0x00000003 /* Mask for Pending Frame Count */
599 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 /* Mask for CBR expired counter */
615 #define AR_D_QCUMASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
618 #define AR_D_LCL_IFS_CWMIN 0x000003FF /* Mask for CW_MIN */
620 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 /* Mask for CW_MAX */
622 #define AR_D_LCL_IFS_AIFS 0x0FF00000 /* Mask for AIFS */
659 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 /* Mask for Virtual collision
669 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
673 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
693 #define AR_RC_PCI 0x00000010 /* PCI-core reset */
715 #define AR_PCICFG_EEPROM_SIZE 0x00000018 /* Mask for EEPROM size */
726 #define AR_PCICFG_PCI_BUS_SEL 0x00000380 /* PCI observation bus mux select */
732 #define AR_PCICFG_SPWR_DN 0x00010000 /* mask for sleep/awake indication */
758 #define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */
764 #define AR_SREV_ID 0x000000FF /* Mask to read SREV info */
765 #define AR_SREV_ID_S 4 /* Mask to shift Major Rev Info */
766 #define AR_SREV_REVISION 0x0000000F /* Mask for Chip revision level */
779 #define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */
855 #define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
857 self-generated frames */
867 self-generated frames */
869 #define AR_STA_ID1_KSRCH_MODE 0x10000000 /* Look-up key when keyID != 0 */
878 #define AR_SLOT_TIME_MASK 0x000007FF /* Slot time mask */
880 #define AR_TIME_OUT_ACK 0x00003FFF /* ACK time-out */
882 #define AR_TIME_OUT_CTS 0x3FFF0000 /* CTS time-out */
899 #define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period mask in TU/msec */
926 #define AR_DIAG_FRAME_NV0 0x00020000 /* Accept frames of non-zero
978 #define AR_MISC_MODE_TX_ADD_TSF 0x8 /* Beacon/Probe-Rsp timestamp add (not replace) */
980 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */
981 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */
982 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */
983 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */
984 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */
994 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */
995 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */
999 #define AR_CCFG_WIN_M 0x00000007 /* mask for AR_CCFG_WIN size */