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Searched +full:mpfs +full:- +full:gpio (Results 1 – 7 of 7) sorted by relevance

/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
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H A Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
8 /dts-v1/;
10 #include "mpfs.dtsi"
11 #include "mpfs-m100pfs-fabric.dtsi"
15 compatible = "aries,m100pfsevp", "microchip,mpfs";
30 stdout-path = "serial1:115200n8";
63 pmic-irq-hog {
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H A Dmpfs-tysom-m.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2020-2022 - Aldec
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
9 /dts-v1/;
11 #include "mpfs.dtsi"
12 #include "mpfs-tysom-m-fabric.dtsi"
15 model = "Aldec TySOM-M-MPFS250T-REV2";
16 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
31 stdout-path = "serial1:115200n8";
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/linux/Documentation/devicetree/bindings/gpio/
H A Dmicrochip,mpfs-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MPFS GPIO Controller
10 - Conor Dooley <conor.dooley@microchip.com>
15 - enum:
16 - microchip,mpfs-gpio
17 - microchip,coregpio-rtl-v3
24 Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
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/linux/drivers/reset/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
10 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
90 tristate "GPIO reset controller"
94 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
97 If compiled as module, it will be called reset-gpio.
146 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
155 Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
201 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
231 Raspberry Pi 4's co-processor controls some of the board's HW
234 interfacing with RPi4's co-processor and model these firmware
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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