| /linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Memory devices
6 menuconfig MEMORY config
7 bool "Memory Controller drivers"
9 This option allows to enable specific memory controller drivers,
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
15 if MEMORY
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
31 controller, say Y or M here.
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| /linux/drivers/memory/tegra/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "NVIDIA Tegra Memory Controller support"
8 This driver supports the Memory Controller (MC) hardware found on
14 tristate "NVIDIA Tegra20 External Memory Controller driver"
21 This driver is for the External Memory Controller (EMC) found on
23 This driver is required to change memory timings / clock rate for
24 external memory.
27 tristate "NVIDIA Tegra30 External Memory Controller driver"
33 This driver is for the External Memory Controller (EMC) found on
35 This driver is required to change memory timings / clock rate for
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nuvoton,npcm-memory-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Memory Controller
10 - Marvin Lin <kflin@nuvoton.com>
11 - Stanley Chu <yschu@nuvoton.com>
14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
17 The memory controller supports single bit error correction, double bit error
18 detection (in-line ECC in which a section (1/8th) of the memory device used to
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| H A D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
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| H A D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
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| H A D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
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| H A D | nvidia,tegra20-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The Tegra20 Memory Controller merges request streams from various client
16 interfaces into request stream(s) for the various memory target devices,
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| H A D | xlnx,versal-ddrmc-edac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
20 const: xlnx,versal-ddrmc
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| H A D | snps,dw-umctl2-ddrc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
15 working with the memory devices supporting up to (LP)DDR4 protocol. It can
17 16-bits or 32-bits or 64-bits wide.
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| /linux/include/uapi/linux/ |
| H A D | um_timetravel.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (C) 2019 - 2023 Intel Corporation
10 * struct um_timetravel_msg - UM time travel message
14 * This is the message passed between the host (user-mode Linux instance)
30 * @seq: sequence number for the message - shall be reflected in
46 * enum um_timetravel_shared_mem_fds - fds sent in ACK message for START message
50 * @UM_TIMETRAVEL_SHARED_MEMFD: Index of the shared memory file
63 * enum um_timetravel_start_ack - ack-time mask for start message
67 * @UM_TIMETRAVEL_START_ACK_ID: client ID that controller allocated.
73 * enum um_timetravel_ops - Operation codes
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| /linux/Documentation/admin-guide/ |
| H A D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
12 of cgroup including core and specific controller behaviors. All
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
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| /linux/drivers/mmc/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MMC/SD host controller drivers
6 comment "MMC/SD/SDIO Host Controller Drivers"
18 tristate "Sunplus SP7021 MMC Controller"
37 bool "Qualcomm Data Mover for SD Card Controller"
41 This selects the Qualcomm Data Mover lite/local on SD Card controller.
48 bool "STMicroelectronics STM32 SDMMC Controller"
52 This selects the STMicroelectronics STM32 SDMMC host controller.
68 tristate "Secure Digital Host Controller Interface support"
71 This selects the generic Secure Digital Host Controller Interface.
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| /linux/Documentation/devicetree/bindings/ata/ |
| H A D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
12 core memory resource.
13 Third memory resource shall be the host controller
14 diagnostic memory resource.
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| /linux/Documentation/devicetree/bindings/edac/ |
| H A D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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| /linux/Documentation/devicetree/bindings/mips/brcm/ |
| H A D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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| /linux/Documentation/devicetree/bindings/display/tegra/ |
| H A D | nvidia,tegra20-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused)
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| /linux/include/linux/ |
| H A D | edac.h | 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
99 * fatal (maybe it is on an unused memory area,
100 * or the memory controller could recover from
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
39 * DCFCLK: Display Controller Fabric Clock
43 * MCLK: Memory Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
102 Display Memory Interface
108 Display Micro-Controller Unit
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| /linux/drivers/memory/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 bool "Samsung Exynos Memory Controller support" if COMPILE_TEST
5 Support for the Memory Controller (MC) devices found on
11 tristate "Exynos5422 Dynamic Memory Controller driver"
17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
18 Controller). The driver provides support for Dynamic Voltage and
21 based on DT memory information.
25 bool "Exynos SROM controller driver" if COMPILE_TEST
28 This adds driver for Samsung Exynos SoC SROM controller. The driver
31 is provided, the driver enables support for external memory
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-devices-edac | 3 Contact: linux-edac@vger.kernel.org
4 Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
14 Contact: linux-edac@vger.kernel.org
21 Contact: linux-edac@vger.kernel.org
22 Description: This attribute file displays the type of memory controller
27 Contact: linux-edac@vger.kernel.org
28 Description: This attribute file displays, in count of megabytes, of memory
29 that this memory controller manages.
33 Contact: linux-edac@vger.kernel.org
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| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
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| /linux/drivers/edac/ |
| H A D | mpc85xx_edac.c | 2 * Freescale MPC85xx Memory Controller kernel module
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
52 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; in mpc85xx_pci_check()
55 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); in mpc85xx_pci_check()
59 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check()
67 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); in mpc85xx_pci_check()
69 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check()
71 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); in mpc85xx_pci_check()
73 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check()
75 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check()
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| H A D | synopsys_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
19 /* Number of cs_rows needed per memory controller */
22 /* Number of channels per memory controller */
33 /* Synopsys DDR memory controller registers that are relevant to ECC */
94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
193 /* DDR Memory type defines */
268 * struct ecc_error_info - ECC error log information.
288 * struct synps_ecc_status - ECC status information to report.
302 * struct synps_edac_priv - DDR memory controller private instance data.
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| /linux/Documentation/driver-api/dmaengine/ |
| H A D | provider.rst | 2 DMAengine controller documentation
20 DMA-eligible devices to the controller itself. Whenever the device
24 A very simple DMA controller would only take into account a single
33 memory copy operation, but our audio device could have a narrower FIFO
39 or destination, can group the reads or writes in memory into a buffer,
40 so instead of having a lot of small memory accesses, which is not
43 reads/writes it's allowed to do without the controller splitting the
44 transfer into smaller sub-transfers.
46 Our theoretical DMA controller would then only be able to do transfers
49 non-contiguous buffers to a contiguous buffer, which is called
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