/linux/drivers/memory/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Memory devices 6 menuconfig MEMORY config 7 bool "Memory Controller drivers" 9 This option allows to enable specific memory controller drivers, 12 vary from memory tuning and frequency scaling to enabling 13 access to attached peripherals through memory bus. 15 if MEMORY 29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller. 31 controller, say Y or M here. [all …]
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/linux/drivers/memory/tegra/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 bool "NVIDIA Tegra Memory Controller support" 8 This driver supports the Memory Controller (MC) hardware found on 14 tristate "NVIDIA Tegra20 External Memory Controller driver" 21 This driver is for the External Memory Controller (EMC) found on 23 This driver is required to change memory timings / clock rate for 24 external memory. 27 tristate "NVIDIA Tegra30 External Memory Controller driver" 33 This driver is for the External Memory Controller (EMC) found on 35 This driver is required to change memory timings / clock rate for [all …]
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/linux/drivers/edac/ |
H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 40 levels are 0-4 (from low to high) and by default it is set to 2. 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 49 occurring on your machine in human-readable form. 60 Not all machines support hardware-driven error report. Some of those 61 provide a BIOS-driven error report mechanism via ACPI, using the 65 When this option is enabled, it will disable the hardware-driven [all …]
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H A D | mpc85xx_edac.c | 2 * Freescale MPC85xx Memory Controller kernel module 8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 52 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; in mpc85xx_pci_check() 55 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); in mpc85xx_pci_check() 59 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check() 67 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); in mpc85xx_pci_check() 69 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check() 71 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); in mpc85xx_pci_check() 73 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check() 75 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check() [all …]
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/linux/drivers/dma/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 12 used to offload memory copies in the network stack and 65 Enable support for Altera / Intel mSGDMA controller. 93 Enable support for Audio DMA Controller found on Apple Silicon SoCs. 96 tristate "Arm DMA-350 support" 101 Enable support for the Arm DMA-350 controller. 109 Support the Atmel AHB DMA controller. 116 Support the Atmel XDMA controller. 119 tristate "Analog Devices AXI-DMAC DMA support" 125 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA [all …]
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/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | nuvoton,npcm-memory-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Nuvoton NPCM Memory Controller 10 - Marvin Lin <kflin@nuvoton.com> 11 - Stanley Chu <yschu@nuvoton.com> 14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction 17 The memory controller supports single bit error correction, double bit error 18 detection (in-line ECC in which a section (1/8th) of the memory device used to [all …]
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H A D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra186 (and later) SoC Memory Controller 10 - Jon Hunter <jonathanh@nvidia.com> 11 - Thierry Reding <thierry.reding@gmail.com> 14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split 16 handles memory requests for 40-bit virtual addresses from internal clients 17 and arbitrates among them to allocate memory bandwidth. [all …]
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H A D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Arm PL35x Series Static Memory Controller (SMC) 10 - Miquel Raynal <miquel.raynal@bootlin.com> 13 The PL35x Static Memory Controller is a bus where you can connect two kinds 14 of memory interfaces, which are NAND and memory mapped interfaces (such as 18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa 26 - arm,pl353-smc-r2p1 [all …]
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H A D | nvidia,tegra20-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra20 SoC Memory Controller 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 15 The Tegra20 Memory Controller merges request streams from various client 16 interfaces into request stream(s) for the various memory target devices, [all …]
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H A D | xlnx,versal-ddrmc-edac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) 10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> 11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> 14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ 15 4X memory interfaces. Versal DDR memory controller has an optional ECC support 20 const: xlnx,versal-ddrmc [all …]
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H A D | snps,dw-umctl2-ddrc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Michal Simek <michal.simek@amd.com> 14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of 15 working with the memory devices supporting up to (LP)DDR4 protocol. It can 17 16-bits or 32-bits or 64-bits wide. [all …]
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H A D | samsung,exynos5422-dmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory 9 Controller device 12 - Krzysztof Kozlowski <krzk@kernel.org> 13 - Lukasz Luba <lukasz.luba@arm.com> 16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the 17 DRAM memory chips are connected. The driver is to monitor the controller in [all …]
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/linux/Documentation/admin-guide/ |
H A D | cgroup-v2.rst | 1 .. _cgroup-v2: 11 conventions of cgroup v2. It describes all userland-visible aspects 12 of cgroup including core and specific controller behaviors. All 14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`. 22 1-1. Terminology 23 1-2. What is cgroup? 25 2-1. Mounting 26 2-2. Organizing Processes and Threads 27 2-2-1. Processes 28 2-2-2. Threads [all …]
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/linux/include/uapi/linux/ |
H A D | um_timetravel.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */ 3 * Copyright (C) 2019 - 2023 Intel Corporation 10 * struct um_timetravel_msg - UM time travel message 14 * This is the message passed between the host (user-mode Linux instance) 30 * @seq: sequence number for the message - shall be reflected in 46 * enum um_timetravel_shared_mem_fds - fds sent in ACK message for START message 50 * @UM_TIMETRAVEL_SHARED_MEMFD: Index of the shared memory file 63 * enum um_timetravel_start_ack - ack-time mask for start message 67 * @UM_TIMETRAVEL_START_ACK_ID: client ID that controller allocated. 73 * enum um_timetravel_ops - Operation codes [all …]
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/linux/Documentation/devicetree/bindings/mips/brcm/ |
H A D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843" 6 "brcm,bcm3384-viper", "brcm,bcm33843-viper" 12 The experimental -viper variants are for running Linux on the 3384's 16 ---------------- 21 = Always-On control block (AON CTRL) 23 This hardware provides control registers for the "always-on" (even in low-power 27 - compatible : should be one of 28 "brcm,bcm7425-aon-ctrl" 29 "brcm,bcm7429-aon-ctrl" 30 "brcm,bcm7435-aon-ctrl" and [all …]
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/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra20-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra Display Controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^dc@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra20-dc [all …]
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/linux/Documentation/devicetree/bindings/dma/ |
H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ST-Ericsson DMA40 DMA Engine 10 - Linus Walleij <linus.walleij@linaro.org> 13 - $ref: dma-controller.yaml# 16 "#dma-cells": 22 0: SPI controller 0 23 1: SD/MMC controller 0 (unused) 24 2: SD/MMC controller 1 (unused) [all …]
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H A D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller 3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move 4 blocks of memory contents between memory and peripherals or 5 from memory to memory. 7 Refer to "Generic DMA Controller and DMA request bindings" in 11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma"; 12 - reg: should contain the DMA controller registers location and length; 13 - interrupt for the DMA controller: syntax of interrupt client node 14 is described in interrupt-controller/interrupts.txt file. 15 - #dma-cells: the length of the DMA specifier, must be <1>. [all …]
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/linux/drivers/memory/samsung/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 3 bool "Samsung Exynos Memory Controller support" if COMPILE_TEST 5 Support for the Memory Controller (MC) devices found on 11 tristate "Exynos5422 Dynamic Memory Controller driver" 17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory 18 Controller). The driver provides support for Dynamic Voltage and 21 based on DT memory information. 25 bool "Exynos SROM controller driver" if COMPILE_TEST 28 This adds driver for Samsung Exynos SoC SROM controller. The driver 31 is provided, the driver enables support for external memory
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/linux/Documentation/nvme/ |
H A D | nvme-pci-endpoint-target.rst | 1 .. SPDX-License-Identifier: GPL-2.0 9 The NVMe PCI endpoint function target driver implements an NVMe PCIe controller 10 using an NVMe fabrics target controller configured with the PCI transport type. 16 controller over a PCIe link, thus implementing an NVMe PCIe device similar to a 17 regular M.2 SSD. The target controller is created in the same manner as when 18 using NVMe over fabrics: the controller represents the interface to an NVMe 22 existing physical NVMe device or an NVMe fabrics host controller (e.g. a NVMe 23 TCP host controller). 51 data buffer is transferred from the host into a local memory buffer before 53 memory buffer is allocated to execute the command and the content of that [all …]
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-devices-edac | 3 Contact: linux-edac@vger.kernel.org 4 Description: This write-only control file will zero all the statistical 5 counters for UE and CE errors on the given memory controller. 14 Contact: linux-edac@vger.kernel.org 21 Contact: linux-edac@vger.kernel.org 22 Description: This attribute file displays the type of memory controller 27 Contact: linux-edac@vger.kernel.org 28 Description: This attribute file displays, in count of megabytes, of memory 29 that this memory controller manages. 33 Contact: linux-edac@vger.kernel.org [all …]
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/linux/Documentation/driver-api/ |
H A D | edac.rst | 5 ---------------------------------------- 8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*, 16 * Memory devices 18 The individual DRAM chips on a memory stick. These devices commonly 20 provides the number of bits that the memory controller expects: 23 * Memory Stick 25 A printed circuit board that aggregates multiple memory devices in 28 called DIMM (Dual Inline Memory Module). 30 * Memory Socket 32 A physical connector on the motherboard that accepts a single memory [all …]
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/linux/Documentation/driver-api/dmaengine/ |
H A D | provider.rst | 2 DMAengine controller documentation 20 DMA-eligible devices to the controller itself. Whenever the device 24 A very simple DMA controller would only take into account a single 33 memory copy operation, but our audio device could have a narrower FIFO 39 or destination, can group the reads or writes in memory into a buffer, 40 so instead of having a lot of small memory accesses, which is not 43 reads/writes it's allowed to do without the controller splitting the 44 transfer into smaller sub-transfers. 46 Our theoretical DMA controller would then only be able to do transfers 49 non-contiguous buffers to a contiguous buffer, which is called [all …]
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/linux/Documentation/devicetree/bindings/arm/mediatek/ |
H A D | mediatek,mt7622-wed.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek Wireless Ethernet Dispatch Controller for MT7622 10 - Lorenzo Bianconi <lorenzo@kernel.org> 11 - Felix Fietkau <nbd@nbd.name> 14 The mediatek wireless ethernet dispatch controller can be configured to 21 - enum: 22 - mediatek,mt7622-wed [all …]
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
H A D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 14 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 19 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.… 61 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre", 72 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD… 115 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.… 120 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre", 126 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM … [all …]
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