Lines Matching +full:memory +full:- +full:controller
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8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
44 controller. Typically, it contains two channels. Two channels at the
48 just one memory stick when an error occurs, as the error correction code
52 * Single-channel
54 The data accessed by the memory controller is contained into one dimm
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
62 The data size accessed by the memory controller is interlaced into two
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
71 dual channel 128 bits. It may not be visible by the memory controller,
72 as some DIMM types have a memory buffer that can hide direct access to
73 it from the Memory Controller.
75 * Single-Ranked stick
77 A Single-ranked stick has 1 chip-select row of memory. Motherboards
78 commonly drive two chip-select pins to a memory stick. A single-ranked
83 * Double-Ranked stick
85 A double-ranked stick has two chip-select rows which access different
86 sets of memory devices. The two rows cannot be accessed concurrently.
88 * Double-sided stick
90 **DEPRECATED TERM**, see :ref:`Double-Ranked stick <doubleranked>`.
92 A double-sided stick has two chip-select rows which access different sets
93 of memory devices. The two rows cannot be accessed concurrently.
94 "Double-sided" is irrespective of the memory devices being mounted on
95 both sides of the memory stick.
99 All of the memory sticks that are required for a single memory access or
100 all of the memory sticks spanned by a chip-select row. A single socket
101 set has two chip-select rows and if double-sided sticks are used these
102 will occupy those chip-select rows.
107 between chip-select rows and socket sets.
109 * High Bandwidth Memory (HBM)
111 HBM is a new memory type with low power consumption and ultra-wide
112 communication lanes. It uses vertically stacked memory chips (DRAM dies)
113 interconnected by microscopic wires called "through-silicon vias," or
116 Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
118 are nearly indistinguishable from on-chip integrated RAM.
120 Memory Controllers
121 ------------------
123 Most of the EDAC core is focused on doing Memory Controller error detection.
125 to describe the memory controllers, with is an opaque struct for the EDAC
128 .. kernel-doc:: include/linux/edac.h
130 .. kernel-doc:: drivers/edac/edac_mc.h
133 ---------------
139 .. kernel-doc:: drivers/edac/edac_pci.h
142 -----------
152 …s the APIs for the same, provide for registering EDAC type devices which are NOT standard memory or
155 - CPU caches (L1 and L2)
156 - DMA engines
157 - Core CPU switches
158 - Fabric switch units
159 - PCIe interface controllers
160 - other EDAC/ECC type devices that can be monitored for
173 mc/ <existing memory device directory>
175 /L1-cache/ce_count
177 /L2-cache/ce_count
180 /L1-cache/ce_count
182 /L2-cache/ce_count
188 .. kernel-doc:: drivers/edac/edac_device.h
192 ----------------------------
199 and each GPU data fabric contains four Unified Memory Controllers (UMC).
200 Each UMC contains eight channels. Each UMC channel controls one 128-bit
202 of 4096-bits of DRAM data bus.
207 Memory controllers on AMD GPU nodes can be represented in EDAC thusly:
209 GPU DF / GPU Node -> EDAC MC
210 GPU UMC -> EDAC CSROW
211 GPU UMC channel -> EDAC CHANNEL
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
221 - CPU UMCs use 1 channel, In this case UMC = EDAC channel. This follows the
222 marketing speak. CPU has X memory channels, etc.
223 - CPU UMCs use up to 4 chip selects, So UMC chip select = EDAC CSROW.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
235 mc0 - CPU MC node 0
237 mc2 |- GPU card[0] => node 0(mc1), node 1(mc2)
239 mc4 |- GPU card[1] => node 0(mc3), node 1(mc4)
241 mc6 |- GPU card[2] => node 0(mc5), node 1(mc6)
243 mc8 |- GPU card[3] => node 0(mc7), node 1(mc8)