Lines Matching +full:memory +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
19 Up to 15 GiB of physical memory can be supported. Security features such as
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
32 - nvidia,tegra186-mc
33 - nvidia,tegra194-mc
34 - nvidia,tegra234-mc
35 - nvidia,tegra264-mc
41 reg-names:
49 interrupt-names:
53 "#address-cells":
56 "#size-cells":
61 dma-ranges: true
63 "#interconnect-cells":
67 "^external-memory-controller@[0-9a-f]+$":
69 The bulk of the work involved in controlling the external memory
70 controller on NVIDIA Tegra186 and later is performed on the BPMP. This
72 which the external memory is clocked and a remote procedure call that
78 - enum:
79 - nvidia,tegra186-emc
80 - nvidia,tegra194-emc
81 - nvidia,tegra234-emc
82 - nvidia,tegra264-emc
90 - description: EMC general interrupt
94 - description: external memory clock
96 clock-names:
98 - const: emc
100 "#interconnect-cells":
109 - if:
112 const: nvidia,tegra186-emc
118 - if:
121 const: nvidia,tegra194-emc
127 - if:
130 const: nvidia,tegra234-emc
136 - if:
139 const: nvidia,tegra264-emc
148 - compatible
149 - reg
150 - interrupts
151 - clocks
152 - clock-names
153 - "#interconnect-cells"
154 - nvidia,bpmp
157 - if:
160 const: nvidia,tegra186-mc
165 description: 5 memory controller channels and 1 for stream-id registers
167 reg-names:
169 - const: sid
170 - const: broadcast
171 - const: ch0
172 - const: ch1
173 - const: ch2
174 - const: ch3
178 - description: MC general interrupt
180 interrupt-names: false
182 - if:
185 const: nvidia,tegra194-mc
190 description: 17 memory controller channels and 1 for stream-id registers
192 reg-names:
194 - const: sid
195 - const: broadcast
196 - const: ch0
197 - const: ch1
198 - const: ch2
199 - const: ch3
200 - const: ch4
201 - const: ch5
202 - const: ch6
203 - const: ch7
204 - const: ch8
205 - const: ch9
206 - const: ch10
207 - const: ch11
208 - const: ch12
209 - const: ch13
210 - const: ch14
211 - const: ch15
215 - description: MC general interrupt
217 interrupt-names: false
219 - if:
222 const: nvidia,tegra234-mc
227 description: 17 memory controller channels and 1 for stream-id registers
229 reg-names:
231 - const: sid
232 - const: broadcast
233 - const: ch0
234 - const: ch1
235 - const: ch2
236 - const: ch3
237 - const: ch4
238 - const: ch5
239 - const: ch6
240 - const: ch7
241 - const: ch8
242 - const: ch9
243 - const: ch10
244 - const: ch11
245 - const: ch12
246 - const: ch13
247 - const: ch14
248 - const: ch15
252 - description: MC general interrupt
254 interrupt-names: false
256 - if:
259 const: nvidia,tegra264-mc
265 description: 17 memory controller channels
267 reg-names:
269 - const: broadcast
270 - const: ch0
271 - const: ch1
272 - const: ch2
273 - const: ch3
274 - const: ch4
275 - const: ch5
276 - const: ch6
277 - const: ch7
278 - const: ch8
279 - const: ch9
280 - const: ch10
281 - const: ch11
282 - const: ch12
283 - const: ch13
284 - const: ch14
285 - const: ch15
292 interrupt-names:
294 - const: mcf
295 - const: hub1
296 - const: hub2
297 - const: hub3
298 - const: hub4
299 - const: hub5
300 - const: sbs
301 - const: channel
306 - compatible
307 - reg
308 - reg-names
309 - interrupts
310 - "#address-cells"
311 - "#size-cells"
314 - |
315 #include <dt-bindings/clock/tegra186-clock.h>
316 #include <dt-bindings/interrupt-controller/arm-gic.h>
319 #address-cells = <2>;
320 #size-cells = <2>;
322 memory-controller@2c00000 {
323 compatible = "nvidia,tegra186-mc";
324 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
330 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
333 #address-cells = <2>;
334 #size-cells = <2>;
339 * Memory clients have access to all 40 bits that the memory
340 * controller can address.
342 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
344 external-memory-controller@2c60000 {
345 compatible = "nvidia,tegra186-emc";
349 clock-names = "emc";
351 #interconnect-cells = <0>;