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Searched +full:mclk +full:- +full:calibrate (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,i2s-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
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/linux/Documentation/devicetree/bindings/mfd/
H A Drockchip,rk817.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
21 - rockchip,rk809
22 - rockchip,rk817
30 '#clock-cells':
32 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
39 clock-names:
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/linux/sound/soc/codecs/
H A Des8326.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // es8326.c -- es8326 ALSA SoC audio driver
6 // Authors: David Yang <yangxiaohua@everest-semi.com>
17 #include <sound/soc-dapm.h>
22 struct clk *mclk; member
56 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h); in es8326_crosstalk1_get()
57 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); in es8326_crosstalk1_get()
61 ucontrol->value.integer.value[0] = crosstalk; in es8326_crosstalk1_get()
74 crosstalk = ucontrol->value.integer.value[0]; in es8326_crosstalk1_set()
75 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); in es8326_crosstalk1_set()
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H A Dcs35l34.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs35l34.c -- CS35l34 ALSA SoC audio driver
28 #include <sound/soc-dapm.h>
48 struct gpio_desc *reset_gpio; /* Active-low reset GPIO */
235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs35l34_sdin_event()
241 if (priv->tdm_mode) in cs35l34_sdin_event()
242 regmap_update_bits(priv->regmap, CS35L34_PWRCTL3, in cs35l34_sdin_event()
245 ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1, in cs35l34_sdin_event()
248 dev_err(component->dev, "Cannot set Power bits %d\n", ret); in cs35l34_sdin_event()
254 if (priv->tdm_mode) { in cs35l34_sdin_event()
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H A Drt5659.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
25 #include <sound/soc-dapm.h>
1136 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
1137 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
1138 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
1139 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
1140 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
1142 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1249 * rt5659_headset_detect - Detect headset.
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H A Dwm8904.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8904.c -- WM8904 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
48 struct clk *mclk; member
84 /* DC servo configuration - cached offset values */
89 { 4, 0x0018 }, /* R4 - Bias Control 0 */
90 { 5, 0x0000 }, /* R5 - VMID Control 0 */
91 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
92 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
93 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
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H A Dwm8903.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8903.c -- WM8903 ALSA SoC Audio driver
5 * Copyright 2008-12 Wolfson Microelectronics
6 * Copyright 2011-2012 NVIDIA, Inc.
11 * - TDM mode configuration.
41 { 4, 0x0018 }, /* R4 - Bias Control 0 */
42 { 5, 0x0000 }, /* R5 - VMID Control 0 */
43 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
44 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
45 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
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H A Drt5663.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5663.c -- RT5663 ALSA SoC audio codec driver
24 #include <sound/soc-dapm.h>
1374 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1375 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1376 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1377 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1406 /* reset in-line command */ in rt5663_enable_push_button_irq()
1413 switch (rt5663->codec_ver) { in rt5663_enable_push_button_irq()
1425 dev_err(component->dev, "Unknown CODEC Version\n"); in rt5663_enable_push_button_irq()
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H A Drt1011.c1 // SPDX-License-Identifier: GPL-2.0
3 * rt1011.c -- rt1011 ALSA SoC amplifier component driver
25 #include <sound/soc-dapm.h>
683 regmap_multi_reg_write(rt1011->regmap, in rt1011_reg_init()
1042 ucontrol->value.integer.value[0] = rt1011->recv_spk_mode; in rt1011_recv_spk_mode_get()
1055 if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode) in rt1011_recv_spk_mode_put()
1059 rt1011->recv_spk_mode = ucontrol->value.integer.value[0]; in rt1011_recv_spk_mode_put()
1061 if (rt1011->recv_spk_mode) { in rt1011_recv_spk_mode_put()
1119 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value; in rt1011_bq_drc_coeff_get()
1122 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set")) in rt1011_bq_drc_coeff_get()
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/linux/drivers/gpu/drm/ast/
H A Dast_post.c14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
65 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */ in ast_set_def_ext_reg()
108 return __ast_mindwm(ast->regs, r); in ast_mindwm()
113 __ast_moutdwm(ast->regs, r, v); in ast_moutdwm()
119 #define CBR_SIZE_AST2150 ((16 << 10) - 1)
173 #if 0 /* unused in DDX driver - here for completeness */
244 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150) in cbrdlli_ast2150()
247 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); in cbrdlli_ast2150()
272 if (ast->chip == AST2100 || ast->chip == AST2200) in ast_init_dram_reg()
290 while (dram_reg_info->index != 0xffff) { in ast_init_dram_reg()
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_hwmgr.c65 (struct vega20_hwmgr *)(hwmgr->backend); in vega20_set_default_registry_data()
67 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT; in vega20_set_default_registry_data()
68 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT; in vega20_set_default_registry_data()
69 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT; in vega20_set_default_registry_data()
70 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT; in vega20_set_default_registry_data()
71 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT; in vega20_set_default_registry_data()
73 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT; in vega20_set_default_registry_data()
74 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; in vega20_set_default_registry_data()
75 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; in vega20_set_default_registry_data()
76 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; in vega20_set_default_registry_data()
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