1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2a91eb199SMark Brown /*
3a91eb199SMark Brown * wm8904.c -- WM8904 ALSA SoC Audio driver
4a91eb199SMark Brown *
5656baaebSMark Brown * Copyright 2009-12 Wolfson Microelectronics plc
6a91eb199SMark Brown *
7a91eb199SMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8a91eb199SMark Brown */
9a91eb199SMark Brown
108b9920e3SBo Shen #include <linux/clk.h>
11a91eb199SMark Brown #include <linux/module.h>
12a91eb199SMark Brown #include <linux/init.h>
13a91eb199SMark Brown #include <linux/delay.h>
14a91eb199SMark Brown #include <linux/pm.h>
15a91eb199SMark Brown #include <linux/i2c.h>
1684d0d831SMark Brown #include <linux/regmap.h>
17a91eb199SMark Brown #include <linux/regulator/consumer.h>
185a0e3ad6STejun Heo #include <linux/slab.h>
19a91eb199SMark Brown #include <sound/core.h>
20a91eb199SMark Brown #include <sound/pcm.h>
21a91eb199SMark Brown #include <sound/pcm_params.h>
22a91eb199SMark Brown #include <sound/soc.h>
23a91eb199SMark Brown #include <sound/initval.h>
24a91eb199SMark Brown #include <sound/tlv.h>
25a91eb199SMark Brown #include <sound/wm8904.h>
26a91eb199SMark Brown
27a91eb199SMark Brown #include "wm8904.h"
28a91eb199SMark Brown
298c126474SMark Brown enum wm8904_type {
308c126474SMark Brown WM8904,
318c126474SMark Brown WM8912,
328c126474SMark Brown };
338c126474SMark Brown
34a91eb199SMark Brown #define WM8904_NUM_DCS_CHANNELS 4
35a91eb199SMark Brown
36a91eb199SMark Brown #define WM8904_NUM_SUPPLIES 5
37a91eb199SMark Brown static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
38a91eb199SMark Brown "DCVDD",
39a91eb199SMark Brown "DBVDD",
40a91eb199SMark Brown "AVDD",
41a91eb199SMark Brown "CPVDD",
42a91eb199SMark Brown "MICVDD",
43a91eb199SMark Brown };
44a91eb199SMark Brown
45a91eb199SMark Brown /* codec private data */
46a91eb199SMark Brown struct wm8904_priv {
4784d0d831SMark Brown struct regmap *regmap;
488b9920e3SBo Shen struct clk *mclk;
49f0fba2adSLiam Girdwood
508c126474SMark Brown enum wm8904_type devtype;
518c126474SMark Brown
52a91eb199SMark Brown struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
53a91eb199SMark Brown
54a91eb199SMark Brown struct wm8904_pdata *pdata;
55a91eb199SMark Brown
56a91eb199SMark Brown int deemph;
57a91eb199SMark Brown
58a91eb199SMark Brown /* Platform provided DRC configuration */
59a91eb199SMark Brown const char **drc_texts;
60a91eb199SMark Brown int drc_cfg;
61a91eb199SMark Brown struct soc_enum drc_enum;
62a91eb199SMark Brown
63a91eb199SMark Brown /* Platform provided ReTune mobile configuration */
64a91eb199SMark Brown int num_retune_mobile_texts;
65a91eb199SMark Brown const char **retune_mobile_texts;
66a91eb199SMark Brown int retune_mobile_cfg;
67a91eb199SMark Brown struct soc_enum retune_mobile_enum;
68a91eb199SMark Brown
69a91eb199SMark Brown /* FLL setup */
70a91eb199SMark Brown int fll_src;
71a91eb199SMark Brown int fll_fref;
72a91eb199SMark Brown int fll_fout;
73a91eb199SMark Brown
74a91eb199SMark Brown /* Clocking configuration */
75a91eb199SMark Brown unsigned int mclk_rate;
76a91eb199SMark Brown int sysclk_src;
77a91eb199SMark Brown unsigned int sysclk_rate;
78a91eb199SMark Brown
79a91eb199SMark Brown int tdm_width;
80a91eb199SMark Brown int tdm_slots;
81a91eb199SMark Brown int bclk;
82a91eb199SMark Brown int fs;
83a91eb199SMark Brown
84a91eb199SMark Brown /* DC servo configuration - cached offset values */
85a91eb199SMark Brown int dcs_state[WM8904_NUM_DCS_CHANNELS];
86a91eb199SMark Brown };
87a91eb199SMark Brown
8884d0d831SMark Brown static const struct reg_default wm8904_reg_defaults[] = {
8984d0d831SMark Brown { 4, 0x0018 }, /* R4 - Bias Control 0 */
9084d0d831SMark Brown { 5, 0x0000 }, /* R5 - VMID Control 0 */
9184d0d831SMark Brown { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
9284d0d831SMark Brown { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
9384d0d831SMark Brown { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
9484d0d831SMark Brown { 9, 0x9696 }, /* R9 - mic Filter Control */
9584d0d831SMark Brown { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
9684d0d831SMark Brown { 12, 0x0000 }, /* R12 - Power Management 0 */
9784d0d831SMark Brown { 14, 0x0000 }, /* R14 - Power Management 2 */
9884d0d831SMark Brown { 15, 0x0000 }, /* R15 - Power Management 3 */
9984d0d831SMark Brown { 18, 0x0000 }, /* R18 - Power Management 6 */
100985b11faSBo Shen { 20, 0x945E }, /* R20 - Clock Rates 0 */
10184d0d831SMark Brown { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
10284d0d831SMark Brown { 22, 0x0006 }, /* R22 - Clock Rates 2 */
10384d0d831SMark Brown { 24, 0x0050 }, /* R24 - Audio Interface 0 */
10484d0d831SMark Brown { 25, 0x000A }, /* R25 - Audio Interface 1 */
10584d0d831SMark Brown { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
10684d0d831SMark Brown { 27, 0x0040 }, /* R27 - Audio Interface 3 */
10784d0d831SMark Brown { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
10884d0d831SMark Brown { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
10984d0d831SMark Brown { 32, 0x0000 }, /* R32 - DAC Digital 0 */
11084d0d831SMark Brown { 33, 0x0008 }, /* R33 - DAC Digital 1 */
11184d0d831SMark Brown { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
11284d0d831SMark Brown { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
11384d0d831SMark Brown { 38, 0x0010 }, /* R38 - ADC Digital 0 */
11484d0d831SMark Brown { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
11584d0d831SMark Brown { 40, 0x01AF }, /* R40 - DRC 0 */
11684d0d831SMark Brown { 41, 0x3248 }, /* R41 - DRC 1 */
11784d0d831SMark Brown { 42, 0x0000 }, /* R42 - DRC 2 */
11884d0d831SMark Brown { 43, 0x0000 }, /* R43 - DRC 3 */
11984d0d831SMark Brown { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
12084d0d831SMark Brown { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
12184d0d831SMark Brown { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
12284d0d831SMark Brown { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
12384d0d831SMark Brown { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
12484d0d831SMark Brown { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
12584d0d831SMark Brown { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
12684d0d831SMark Brown { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
12784d0d831SMark Brown { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
12884d0d831SMark Brown { 67, 0x0000 }, /* R67 - DC Servo 0 */
12984d0d831SMark Brown { 69, 0xAAAA }, /* R69 - DC Servo 2 */
13084d0d831SMark Brown { 71, 0xAAAA }, /* R71 - DC Servo 4 */
13184d0d831SMark Brown { 72, 0xAAAA }, /* R72 - DC Servo 5 */
13284d0d831SMark Brown { 90, 0x0000 }, /* R90 - Analogue HP 0 */
13384d0d831SMark Brown { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
13484d0d831SMark Brown { 98, 0x0000 }, /* R98 - Charge Pump 0 */
13584d0d831SMark Brown { 104, 0x0004 }, /* R104 - Class W 0 */
13684d0d831SMark Brown { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
13784d0d831SMark Brown { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
13884d0d831SMark Brown { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
13984d0d831SMark Brown { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
14084d0d831SMark Brown { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
14184d0d831SMark Brown { 116, 0x0000 }, /* R116 - FLL Control 1 */
14284d0d831SMark Brown { 117, 0x0007 }, /* R117 - FLL Control 2 */
14384d0d831SMark Brown { 118, 0x0000 }, /* R118 - FLL Control 3 */
14484d0d831SMark Brown { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
14584d0d831SMark Brown { 120, 0x0004 }, /* R120 - FLL Control 5 */
14684d0d831SMark Brown { 121, 0x0014 }, /* R121 - GPIO Control 1 */
14784d0d831SMark Brown { 122, 0x0010 }, /* R122 - GPIO Control 2 */
14884d0d831SMark Brown { 123, 0x0010 }, /* R123 - GPIO Control 3 */
14984d0d831SMark Brown { 124, 0x0000 }, /* R124 - GPIO Control 4 */
15084d0d831SMark Brown { 126, 0x0000 }, /* R126 - Digital Pulls */
15184d0d831SMark Brown { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
15284d0d831SMark Brown { 129, 0x0000 }, /* R129 - Interrupt Polarity */
15384d0d831SMark Brown { 130, 0x0000 }, /* R130 - Interrupt Debounce */
15484d0d831SMark Brown { 134, 0x0000 }, /* R134 - EQ1 */
15584d0d831SMark Brown { 135, 0x000C }, /* R135 - EQ2 */
15684d0d831SMark Brown { 136, 0x000C }, /* R136 - EQ3 */
15784d0d831SMark Brown { 137, 0x000C }, /* R137 - EQ4 */
15884d0d831SMark Brown { 138, 0x000C }, /* R138 - EQ5 */
15984d0d831SMark Brown { 139, 0x000C }, /* R139 - EQ6 */
16084d0d831SMark Brown { 140, 0x0FCA }, /* R140 - EQ7 */
16184d0d831SMark Brown { 141, 0x0400 }, /* R141 - EQ8 */
16284d0d831SMark Brown { 142, 0x00D8 }, /* R142 - EQ9 */
16384d0d831SMark Brown { 143, 0x1EB5 }, /* R143 - EQ10 */
16484d0d831SMark Brown { 144, 0xF145 }, /* R144 - EQ11 */
16584d0d831SMark Brown { 145, 0x0B75 }, /* R145 - EQ12 */
16684d0d831SMark Brown { 146, 0x01C5 }, /* R146 - EQ13 */
16784d0d831SMark Brown { 147, 0x1C58 }, /* R147 - EQ14 */
16884d0d831SMark Brown { 148, 0xF373 }, /* R148 - EQ15 */
16984d0d831SMark Brown { 149, 0x0A54 }, /* R149 - EQ16 */
17084d0d831SMark Brown { 150, 0x0558 }, /* R150 - EQ17 */
17184d0d831SMark Brown { 151, 0x168E }, /* R151 - EQ18 */
17284d0d831SMark Brown { 152, 0xF829 }, /* R152 - EQ19 */
17384d0d831SMark Brown { 153, 0x07AD }, /* R153 - EQ20 */
17484d0d831SMark Brown { 154, 0x1103 }, /* R154 - EQ21 */
17584d0d831SMark Brown { 155, 0x0564 }, /* R155 - EQ22 */
17684d0d831SMark Brown { 156, 0x0559 }, /* R156 - EQ23 */
17784d0d831SMark Brown { 157, 0x4000 }, /* R157 - EQ24 */
17884d0d831SMark Brown { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
17984d0d831SMark Brown { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
18084d0d831SMark Brown { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
18184d0d831SMark Brown { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
182a91eb199SMark Brown };
183a91eb199SMark Brown
wm8904_volatile_register(struct device * dev,unsigned int reg)18484d0d831SMark Brown static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
185a91eb199SMark Brown {
18684d0d831SMark Brown switch (reg) {
18784d0d831SMark Brown case WM8904_SW_RESET_AND_ID:
18884d0d831SMark Brown case WM8904_REVISION:
18984d0d831SMark Brown case WM8904_DC_SERVO_1:
19084d0d831SMark Brown case WM8904_DC_SERVO_6:
19184d0d831SMark Brown case WM8904_DC_SERVO_7:
19284d0d831SMark Brown case WM8904_DC_SERVO_8:
19384d0d831SMark Brown case WM8904_DC_SERVO_9:
19484d0d831SMark Brown case WM8904_DC_SERVO_READBACK_0:
19584d0d831SMark Brown case WM8904_INTERRUPT_STATUS:
19684d0d831SMark Brown return true;
19784d0d831SMark Brown default:
19884d0d831SMark Brown return false;
19984d0d831SMark Brown }
20084d0d831SMark Brown }
20184d0d831SMark Brown
wm8904_readable_register(struct device * dev,unsigned int reg)20284d0d831SMark Brown static bool wm8904_readable_register(struct device *dev, unsigned int reg)
20384d0d831SMark Brown {
20484d0d831SMark Brown switch (reg) {
20584d0d831SMark Brown case WM8904_SW_RESET_AND_ID:
20684d0d831SMark Brown case WM8904_REVISION:
20784d0d831SMark Brown case WM8904_BIAS_CONTROL_0:
20884d0d831SMark Brown case WM8904_VMID_CONTROL_0:
20984d0d831SMark Brown case WM8904_MIC_BIAS_CONTROL_0:
21084d0d831SMark Brown case WM8904_MIC_BIAS_CONTROL_1:
21184d0d831SMark Brown case WM8904_ANALOGUE_DAC_0:
21284d0d831SMark Brown case WM8904_MIC_FILTER_CONTROL:
21384d0d831SMark Brown case WM8904_ANALOGUE_ADC_0:
21484d0d831SMark Brown case WM8904_POWER_MANAGEMENT_0:
21584d0d831SMark Brown case WM8904_POWER_MANAGEMENT_2:
21684d0d831SMark Brown case WM8904_POWER_MANAGEMENT_3:
21784d0d831SMark Brown case WM8904_POWER_MANAGEMENT_6:
21884d0d831SMark Brown case WM8904_CLOCK_RATES_0:
21984d0d831SMark Brown case WM8904_CLOCK_RATES_1:
22084d0d831SMark Brown case WM8904_CLOCK_RATES_2:
22184d0d831SMark Brown case WM8904_AUDIO_INTERFACE_0:
22284d0d831SMark Brown case WM8904_AUDIO_INTERFACE_1:
22384d0d831SMark Brown case WM8904_AUDIO_INTERFACE_2:
22484d0d831SMark Brown case WM8904_AUDIO_INTERFACE_3:
22584d0d831SMark Brown case WM8904_DAC_DIGITAL_VOLUME_LEFT:
22684d0d831SMark Brown case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
22784d0d831SMark Brown case WM8904_DAC_DIGITAL_0:
22884d0d831SMark Brown case WM8904_DAC_DIGITAL_1:
22984d0d831SMark Brown case WM8904_ADC_DIGITAL_VOLUME_LEFT:
23084d0d831SMark Brown case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
23184d0d831SMark Brown case WM8904_ADC_DIGITAL_0:
23284d0d831SMark Brown case WM8904_DIGITAL_MICROPHONE_0:
23384d0d831SMark Brown case WM8904_DRC_0:
23484d0d831SMark Brown case WM8904_DRC_1:
23584d0d831SMark Brown case WM8904_DRC_2:
23684d0d831SMark Brown case WM8904_DRC_3:
23784d0d831SMark Brown case WM8904_ANALOGUE_LEFT_INPUT_0:
23884d0d831SMark Brown case WM8904_ANALOGUE_RIGHT_INPUT_0:
23984d0d831SMark Brown case WM8904_ANALOGUE_LEFT_INPUT_1:
24084d0d831SMark Brown case WM8904_ANALOGUE_RIGHT_INPUT_1:
24184d0d831SMark Brown case WM8904_ANALOGUE_OUT1_LEFT:
24284d0d831SMark Brown case WM8904_ANALOGUE_OUT1_RIGHT:
24384d0d831SMark Brown case WM8904_ANALOGUE_OUT2_LEFT:
24484d0d831SMark Brown case WM8904_ANALOGUE_OUT2_RIGHT:
24584d0d831SMark Brown case WM8904_ANALOGUE_OUT12_ZC:
24684d0d831SMark Brown case WM8904_DC_SERVO_0:
24784d0d831SMark Brown case WM8904_DC_SERVO_1:
24884d0d831SMark Brown case WM8904_DC_SERVO_2:
24984d0d831SMark Brown case WM8904_DC_SERVO_4:
25084d0d831SMark Brown case WM8904_DC_SERVO_5:
25184d0d831SMark Brown case WM8904_DC_SERVO_6:
25284d0d831SMark Brown case WM8904_DC_SERVO_7:
25384d0d831SMark Brown case WM8904_DC_SERVO_8:
25484d0d831SMark Brown case WM8904_DC_SERVO_9:
25584d0d831SMark Brown case WM8904_DC_SERVO_READBACK_0:
25684d0d831SMark Brown case WM8904_ANALOGUE_HP_0:
25784d0d831SMark Brown case WM8904_ANALOGUE_LINEOUT_0:
25884d0d831SMark Brown case WM8904_CHARGE_PUMP_0:
25984d0d831SMark Brown case WM8904_CLASS_W_0:
26084d0d831SMark Brown case WM8904_WRITE_SEQUENCER_0:
26184d0d831SMark Brown case WM8904_WRITE_SEQUENCER_1:
26284d0d831SMark Brown case WM8904_WRITE_SEQUENCER_2:
26384d0d831SMark Brown case WM8904_WRITE_SEQUENCER_3:
26484d0d831SMark Brown case WM8904_WRITE_SEQUENCER_4:
26584d0d831SMark Brown case WM8904_FLL_CONTROL_1:
26684d0d831SMark Brown case WM8904_FLL_CONTROL_2:
26784d0d831SMark Brown case WM8904_FLL_CONTROL_3:
26884d0d831SMark Brown case WM8904_FLL_CONTROL_4:
26984d0d831SMark Brown case WM8904_FLL_CONTROL_5:
27084d0d831SMark Brown case WM8904_GPIO_CONTROL_1:
27184d0d831SMark Brown case WM8904_GPIO_CONTROL_2:
27284d0d831SMark Brown case WM8904_GPIO_CONTROL_3:
27384d0d831SMark Brown case WM8904_GPIO_CONTROL_4:
27484d0d831SMark Brown case WM8904_DIGITAL_PULLS:
27584d0d831SMark Brown case WM8904_INTERRUPT_STATUS:
27684d0d831SMark Brown case WM8904_INTERRUPT_STATUS_MASK:
27784d0d831SMark Brown case WM8904_INTERRUPT_POLARITY:
27884d0d831SMark Brown case WM8904_INTERRUPT_DEBOUNCE:
27984d0d831SMark Brown case WM8904_EQ1:
28084d0d831SMark Brown case WM8904_EQ2:
28184d0d831SMark Brown case WM8904_EQ3:
28284d0d831SMark Brown case WM8904_EQ4:
28384d0d831SMark Brown case WM8904_EQ5:
28484d0d831SMark Brown case WM8904_EQ6:
28584d0d831SMark Brown case WM8904_EQ7:
28684d0d831SMark Brown case WM8904_EQ8:
28784d0d831SMark Brown case WM8904_EQ9:
28884d0d831SMark Brown case WM8904_EQ10:
28984d0d831SMark Brown case WM8904_EQ11:
29084d0d831SMark Brown case WM8904_EQ12:
29184d0d831SMark Brown case WM8904_EQ13:
29284d0d831SMark Brown case WM8904_EQ14:
29384d0d831SMark Brown case WM8904_EQ15:
29484d0d831SMark Brown case WM8904_EQ16:
29584d0d831SMark Brown case WM8904_EQ17:
29684d0d831SMark Brown case WM8904_EQ18:
29784d0d831SMark Brown case WM8904_EQ19:
29884d0d831SMark Brown case WM8904_EQ20:
29984d0d831SMark Brown case WM8904_EQ21:
30084d0d831SMark Brown case WM8904_EQ22:
30184d0d831SMark Brown case WM8904_EQ23:
30284d0d831SMark Brown case WM8904_EQ24:
30384d0d831SMark Brown case WM8904_CONTROL_INTERFACE_TEST_1:
3049b85fc90SMark Brown case WM8904_ADC_TEST_0:
30584d0d831SMark Brown case WM8904_ANALOGUE_OUTPUT_BIAS_0:
30684d0d831SMark Brown case WM8904_FLL_NCO_TEST_0:
30784d0d831SMark Brown case WM8904_FLL_NCO_TEST_1:
30884d0d831SMark Brown return true;
30984d0d831SMark Brown default:
31028b5df18SAxel Lin return false;
31184d0d831SMark Brown }
312a91eb199SMark Brown }
313a91eb199SMark Brown
wm8904_configure_clocking(struct snd_soc_component * component)31446a9100cSKuninori Morimoto static int wm8904_configure_clocking(struct snd_soc_component *component)
315a91eb199SMark Brown {
31646a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
317a91eb199SMark Brown unsigned int clock0, clock2, rate;
318a91eb199SMark Brown
319a91eb199SMark Brown /* Gate the clock while we're updating to avoid misclocking */
3206d75dfc3SKuninori Morimoto clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
32146a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
322a91eb199SMark Brown WM8904_SYSCLK_SRC, 0);
323a91eb199SMark Brown
324a91eb199SMark Brown /* This should be done on init() for bypass paths */
325a91eb199SMark Brown switch (wm8904->sysclk_src) {
326a91eb199SMark Brown case WM8904_CLK_MCLK:
32746a9100cSKuninori Morimoto dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
328a91eb199SMark Brown
329a91eb199SMark Brown clock2 &= ~WM8904_SYSCLK_SRC;
330a91eb199SMark Brown rate = wm8904->mclk_rate;
331a91eb199SMark Brown
332a91eb199SMark Brown /* Ensure the FLL is stopped */
33346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
334a91eb199SMark Brown WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
335a91eb199SMark Brown break;
336a91eb199SMark Brown
337a91eb199SMark Brown case WM8904_CLK_FLL:
33846a9100cSKuninori Morimoto dev_dbg(component->dev, "Using %dHz FLL clock\n",
339a91eb199SMark Brown wm8904->fll_fout);
340a91eb199SMark Brown
341a91eb199SMark Brown clock2 |= WM8904_SYSCLK_SRC;
342a91eb199SMark Brown rate = wm8904->fll_fout;
343a91eb199SMark Brown break;
344a91eb199SMark Brown
345a91eb199SMark Brown default:
34646a9100cSKuninori Morimoto dev_err(component->dev, "System clock not configured\n");
347a91eb199SMark Brown return -EINVAL;
348a91eb199SMark Brown }
349a91eb199SMark Brown
350a91eb199SMark Brown /* SYSCLK shouldn't be over 13.5MHz */
351a91eb199SMark Brown if (rate > 13500000) {
352a91eb199SMark Brown clock0 = WM8904_MCLK_DIV;
353a91eb199SMark Brown wm8904->sysclk_rate = rate / 2;
354a91eb199SMark Brown } else {
355a91eb199SMark Brown clock0 = 0;
356a91eb199SMark Brown wm8904->sysclk_rate = rate;
357a91eb199SMark Brown }
358a91eb199SMark Brown
35946a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
360a91eb199SMark Brown clock0);
361a91eb199SMark Brown
36246a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
363a91eb199SMark Brown WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
364a91eb199SMark Brown
36546a9100cSKuninori Morimoto dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
366a91eb199SMark Brown
367a91eb199SMark Brown return 0;
368a91eb199SMark Brown }
369a91eb199SMark Brown
wm8904_set_drc(struct snd_soc_component * component)37046a9100cSKuninori Morimoto static void wm8904_set_drc(struct snd_soc_component *component)
371a91eb199SMark Brown {
37246a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
373a91eb199SMark Brown struct wm8904_pdata *pdata = wm8904->pdata;
374a91eb199SMark Brown int save, i;
375a91eb199SMark Brown
376a91eb199SMark Brown /* Save any enables; the configuration should clear them. */
3776d75dfc3SKuninori Morimoto save = snd_soc_component_read(component, WM8904_DRC_0);
378a91eb199SMark Brown
379a91eb199SMark Brown for (i = 0; i < WM8904_DRC_REGS; i++)
38046a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff,
381a91eb199SMark Brown pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
382a91eb199SMark Brown
383a91eb199SMark Brown /* Reenable the DRC */
38446a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_DRC_0,
385a91eb199SMark Brown WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
386a91eb199SMark Brown }
387a91eb199SMark Brown
wm8904_put_drc_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)388a91eb199SMark Brown static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
389a91eb199SMark Brown struct snd_ctl_elem_value *ucontrol)
390a91eb199SMark Brown {
39146a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
39246a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
393a91eb199SMark Brown struct wm8904_pdata *pdata = wm8904->pdata;
394c41a024cSTakashi Iwai int value = ucontrol->value.enumerated.item[0];
395a91eb199SMark Brown
396a91eb199SMark Brown if (value >= pdata->num_drc_cfgs)
397a91eb199SMark Brown return -EINVAL;
398a91eb199SMark Brown
399a91eb199SMark Brown wm8904->drc_cfg = value;
400a91eb199SMark Brown
40146a9100cSKuninori Morimoto wm8904_set_drc(component);
402a91eb199SMark Brown
403a91eb199SMark Brown return 0;
404a91eb199SMark Brown }
405a91eb199SMark Brown
wm8904_get_drc_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)406a91eb199SMark Brown static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
407a91eb199SMark Brown struct snd_ctl_elem_value *ucontrol)
408a91eb199SMark Brown {
40946a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
41046a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
411a91eb199SMark Brown
412a91eb199SMark Brown ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
413a91eb199SMark Brown
414a91eb199SMark Brown return 0;
415a91eb199SMark Brown }
416a91eb199SMark Brown
wm8904_set_retune_mobile(struct snd_soc_component * component)41746a9100cSKuninori Morimoto static void wm8904_set_retune_mobile(struct snd_soc_component *component)
418a91eb199SMark Brown {
41946a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
420a91eb199SMark Brown struct wm8904_pdata *pdata = wm8904->pdata;
421a91eb199SMark Brown int best, best_val, save, i, cfg;
422a91eb199SMark Brown
423a91eb199SMark Brown if (!pdata || !wm8904->num_retune_mobile_texts)
424a91eb199SMark Brown return;
425a91eb199SMark Brown
426a91eb199SMark Brown /* Find the version of the currently selected configuration
427a91eb199SMark Brown * with the nearest sample rate. */
428a91eb199SMark Brown cfg = wm8904->retune_mobile_cfg;
429a91eb199SMark Brown best = 0;
430a91eb199SMark Brown best_val = INT_MAX;
431a91eb199SMark Brown for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
432a91eb199SMark Brown if (strcmp(pdata->retune_mobile_cfgs[i].name,
433a91eb199SMark Brown wm8904->retune_mobile_texts[cfg]) == 0 &&
434a91eb199SMark Brown abs(pdata->retune_mobile_cfgs[i].rate
435a91eb199SMark Brown - wm8904->fs) < best_val) {
436a91eb199SMark Brown best = i;
437a91eb199SMark Brown best_val = abs(pdata->retune_mobile_cfgs[i].rate
438a91eb199SMark Brown - wm8904->fs);
439a91eb199SMark Brown }
440a91eb199SMark Brown }
441a91eb199SMark Brown
44246a9100cSKuninori Morimoto dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
443a91eb199SMark Brown pdata->retune_mobile_cfgs[best].name,
444a91eb199SMark Brown pdata->retune_mobile_cfgs[best].rate,
445a91eb199SMark Brown wm8904->fs);
446a91eb199SMark Brown
447a91eb199SMark Brown /* The EQ will be disabled while reconfiguring it, remember the
448a91eb199SMark Brown * current configuration.
449a91eb199SMark Brown */
4506d75dfc3SKuninori Morimoto save = snd_soc_component_read(component, WM8904_EQ1);
451a91eb199SMark Brown
452a91eb199SMark Brown for (i = 0; i < WM8904_EQ_REGS; i++)
45346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff,
454a91eb199SMark Brown pdata->retune_mobile_cfgs[best].regs[i]);
455a91eb199SMark Brown
45646a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save);
457a91eb199SMark Brown }
458a91eb199SMark Brown
wm8904_put_retune_mobile_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)459a91eb199SMark Brown static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
460a91eb199SMark Brown struct snd_ctl_elem_value *ucontrol)
461a91eb199SMark Brown {
46246a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
46346a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
464a91eb199SMark Brown struct wm8904_pdata *pdata = wm8904->pdata;
465c41a024cSTakashi Iwai int value = ucontrol->value.enumerated.item[0];
466a91eb199SMark Brown
467a91eb199SMark Brown if (value >= pdata->num_retune_mobile_cfgs)
468a91eb199SMark Brown return -EINVAL;
469a91eb199SMark Brown
470a91eb199SMark Brown wm8904->retune_mobile_cfg = value;
471a91eb199SMark Brown
47246a9100cSKuninori Morimoto wm8904_set_retune_mobile(component);
473a91eb199SMark Brown
474a91eb199SMark Brown return 0;
475a91eb199SMark Brown }
476a91eb199SMark Brown
wm8904_get_retune_mobile_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)477a91eb199SMark Brown static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
478a91eb199SMark Brown struct snd_ctl_elem_value *ucontrol)
479a91eb199SMark Brown {
48046a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
48146a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
482a91eb199SMark Brown
483a91eb199SMark Brown ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
484a91eb199SMark Brown
485a91eb199SMark Brown return 0;
486a91eb199SMark Brown }
487a91eb199SMark Brown
488a91eb199SMark Brown static int deemph_settings[] = { 0, 32000, 44100, 48000 };
489a91eb199SMark Brown
wm8904_set_deemph(struct snd_soc_component * component)49046a9100cSKuninori Morimoto static int wm8904_set_deemph(struct snd_soc_component *component)
491a91eb199SMark Brown {
49246a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
493a91eb199SMark Brown int val, i, best;
494a91eb199SMark Brown
495a91eb199SMark Brown /* If we're using deemphasis select the nearest available sample
496a91eb199SMark Brown * rate.
497a91eb199SMark Brown */
498a91eb199SMark Brown if (wm8904->deemph) {
499a91eb199SMark Brown best = 1;
500a91eb199SMark Brown for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
501a91eb199SMark Brown if (abs(deemph_settings[i] - wm8904->fs) <
502a91eb199SMark Brown abs(deemph_settings[best] - wm8904->fs))
503a91eb199SMark Brown best = i;
504a91eb199SMark Brown }
505a91eb199SMark Brown
506a91eb199SMark Brown val = best << WM8904_DEEMPH_SHIFT;
507a91eb199SMark Brown } else {
508a91eb199SMark Brown val = 0;
509a91eb199SMark Brown }
510a91eb199SMark Brown
51146a9100cSKuninori Morimoto dev_dbg(component->dev, "Set deemphasis %d\n", val);
512a91eb199SMark Brown
51346a9100cSKuninori Morimoto return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
514a91eb199SMark Brown WM8904_DEEMPH_MASK, val);
515a91eb199SMark Brown }
516a91eb199SMark Brown
wm8904_get_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)517a91eb199SMark Brown static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
518a91eb199SMark Brown struct snd_ctl_elem_value *ucontrol)
519a91eb199SMark Brown {
52046a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
52146a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
522a91eb199SMark Brown
523eaddf6fdSTakashi Iwai ucontrol->value.integer.value[0] = wm8904->deemph;
5243f343f85SDmitry Artamonow return 0;
525a91eb199SMark Brown }
526a91eb199SMark Brown
wm8904_put_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)527a91eb199SMark Brown static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
528a91eb199SMark Brown struct snd_ctl_elem_value *ucontrol)
529a91eb199SMark Brown {
53046a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
53146a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
532931dfa69SDan Carpenter unsigned int deemph = ucontrol->value.integer.value[0];
533a91eb199SMark Brown
534a91eb199SMark Brown if (deemph > 1)
535a91eb199SMark Brown return -EINVAL;
536a91eb199SMark Brown
537a91eb199SMark Brown wm8904->deemph = deemph;
538a91eb199SMark Brown
53946a9100cSKuninori Morimoto return wm8904_set_deemph(component);
540a91eb199SMark Brown }
541a91eb199SMark Brown
542a91eb199SMark Brown static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
543a91eb199SMark Brown static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
544a91eb199SMark Brown static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
545a91eb199SMark Brown static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
546a91eb199SMark Brown static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
547a91eb199SMark Brown
548a91eb199SMark Brown static const char *hpf_mode_text[] = {
549a91eb199SMark Brown "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
550a91eb199SMark Brown };
551a91eb199SMark Brown
552d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
553d12bfd62STakashi Iwai hpf_mode_text);
554a91eb199SMark Brown
wm8904_adc_osr_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5559b85fc90SMark Brown static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
5569b85fc90SMark Brown struct snd_ctl_elem_value *ucontrol)
5579b85fc90SMark Brown {
55846a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
5599b85fc90SMark Brown unsigned int val;
5609b85fc90SMark Brown int ret;
5619b85fc90SMark Brown
5629b85fc90SMark Brown ret = snd_soc_put_volsw(kcontrol, ucontrol);
5639b85fc90SMark Brown if (ret < 0)
5649b85fc90SMark Brown return ret;
5659b85fc90SMark Brown
5669b85fc90SMark Brown if (ucontrol->value.integer.value[0])
5679b85fc90SMark Brown val = 0;
5689b85fc90SMark Brown else
5699b85fc90SMark Brown val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
5709b85fc90SMark Brown
57146a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_ADC_TEST_0,
5729b85fc90SMark Brown WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
5739b85fc90SMark Brown val);
5749b85fc90SMark Brown
5759b85fc90SMark Brown return ret;
5769b85fc90SMark Brown }
5779b85fc90SMark Brown
578a91eb199SMark Brown static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
579a91eb199SMark Brown SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
580a91eb199SMark Brown WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
581a91eb199SMark Brown
582a91eb199SMark Brown /* No TLV since it depends on mode */
583a91eb199SMark Brown SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
584a91eb199SMark Brown WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
585a91eb199SMark Brown SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
5865a7c5f26SHong Xu WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
587a91eb199SMark Brown
588a91eb199SMark Brown SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
589a91eb199SMark Brown SOC_ENUM("High Pass Filter Mode", hpf_mode),
5905a68bae2SLars-Peter Clausen SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
5915a68bae2SLars-Peter Clausen snd_soc_get_volsw, wm8904_adc_osr_put),
592a91eb199SMark Brown };
593a91eb199SMark Brown
594a91eb199SMark Brown static const char *drc_path_text[] = {
595a91eb199SMark Brown "ADC", "DAC"
596a91eb199SMark Brown };
597a91eb199SMark Brown
598d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
599a91eb199SMark Brown
600a91eb199SMark Brown static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
601a91eb199SMark Brown SOC_SINGLE_TLV("Digital Playback Boost Volume",
602a91eb199SMark Brown WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
603a91eb199SMark Brown SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
604a91eb199SMark Brown WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
605a91eb199SMark Brown
606a91eb199SMark Brown SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
607a91eb199SMark Brown WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
608a91eb199SMark Brown SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
609a91eb199SMark Brown WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
610a91eb199SMark Brown SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
611a91eb199SMark Brown WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
612a91eb199SMark Brown
613a91eb199SMark Brown SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
614a91eb199SMark Brown WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
615a91eb199SMark Brown SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
616a91eb199SMark Brown WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
617a91eb199SMark Brown SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
618a91eb199SMark Brown WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
619a91eb199SMark Brown
620a91eb199SMark Brown SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
621a91eb199SMark Brown SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
622a91eb199SMark Brown SOC_ENUM("DRC Path", drc_path),
623a91eb199SMark Brown SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
624a91eb199SMark Brown SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
625a91eb199SMark Brown wm8904_get_deemph, wm8904_put_deemph),
626a91eb199SMark Brown };
627a91eb199SMark Brown
628a91eb199SMark Brown static const struct snd_kcontrol_new wm8904_snd_controls[] = {
629a91eb199SMark Brown SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
630a91eb199SMark Brown sidetone_tlv),
631a91eb199SMark Brown };
632a91eb199SMark Brown
633a91eb199SMark Brown static const struct snd_kcontrol_new wm8904_eq_controls[] = {
634a91eb199SMark Brown SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
635a91eb199SMark Brown SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
636a91eb199SMark Brown SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
637a91eb199SMark Brown SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
638a91eb199SMark Brown SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
639a91eb199SMark Brown };
640a91eb199SMark Brown
cp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)641a91eb199SMark Brown static int cp_event(struct snd_soc_dapm_widget *w,
642a91eb199SMark Brown struct snd_kcontrol *kcontrol, int event)
643a91eb199SMark Brown {
6444c8d620aSTakashi Iwai if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
6454c8d620aSTakashi Iwai return -EINVAL;
646a91eb199SMark Brown
647a91eb199SMark Brown /* Maximum startup time */
648a91eb199SMark Brown udelay(500);
649a91eb199SMark Brown
650a91eb199SMark Brown return 0;
651a91eb199SMark Brown }
652a91eb199SMark Brown
sysclk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)653a91eb199SMark Brown static int sysclk_event(struct snd_soc_dapm_widget *w,
654a91eb199SMark Brown struct snd_kcontrol *kcontrol, int event)
655a91eb199SMark Brown {
65646a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
65746a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
658a91eb199SMark Brown
659a91eb199SMark Brown switch (event) {
660a91eb199SMark Brown case SND_SOC_DAPM_PRE_PMU:
661a91eb199SMark Brown /* If we're using the FLL then we only start it when
662a91eb199SMark Brown * required; we assume that the configuration has been
663a91eb199SMark Brown * done previously and all we need to do is kick it
664a91eb199SMark Brown * off.
665a91eb199SMark Brown */
666a91eb199SMark Brown switch (wm8904->sysclk_src) {
667a91eb199SMark Brown case WM8904_CLK_FLL:
66846a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
669a91eb199SMark Brown WM8904_FLL_OSC_ENA,
670a91eb199SMark Brown WM8904_FLL_OSC_ENA);
671a91eb199SMark Brown
67246a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
673a91eb199SMark Brown WM8904_FLL_ENA,
674a91eb199SMark Brown WM8904_FLL_ENA);
675a91eb199SMark Brown break;
676a91eb199SMark Brown
677a91eb199SMark Brown default:
678a91eb199SMark Brown break;
679a91eb199SMark Brown }
680a91eb199SMark Brown break;
681a91eb199SMark Brown
682a91eb199SMark Brown case SND_SOC_DAPM_POST_PMD:
68346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
684a91eb199SMark Brown WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
685a91eb199SMark Brown break;
686a91eb199SMark Brown }
687a91eb199SMark Brown
688a91eb199SMark Brown return 0;
689a91eb199SMark Brown }
690a91eb199SMark Brown
out_pga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)691a91eb199SMark Brown static int out_pga_event(struct snd_soc_dapm_widget *w,
692a91eb199SMark Brown struct snd_kcontrol *kcontrol, int event)
693a91eb199SMark Brown {
69446a9100cSKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
69546a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
696a91eb199SMark Brown int reg, val;
697a91eb199SMark Brown int dcs_mask;
698a91eb199SMark Brown int dcs_l, dcs_r;
699a91eb199SMark Brown int dcs_l_reg, dcs_r_reg;
700472a6309SEmanuele Ghidoli int an_out_reg;
701a91eb199SMark Brown int timeout;
702e4bc6696SMark Brown int pwr_reg;
703a91eb199SMark Brown
704a91eb199SMark Brown /* This code is shared between HP and LINEOUT; we do all our
705a91eb199SMark Brown * power management in stereo pairs to avoid latency issues so
706a91eb199SMark Brown * we reuse shift to identify which rather than strcmp() the
707a91eb199SMark Brown * name. */
708a91eb199SMark Brown reg = w->shift;
709a91eb199SMark Brown
710a91eb199SMark Brown switch (reg) {
711a91eb199SMark Brown case WM8904_ANALOGUE_HP_0:
712e4bc6696SMark Brown pwr_reg = WM8904_POWER_MANAGEMENT_2;
713a91eb199SMark Brown dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
714a91eb199SMark Brown dcs_r_reg = WM8904_DC_SERVO_8;
715a91eb199SMark Brown dcs_l_reg = WM8904_DC_SERVO_9;
716472a6309SEmanuele Ghidoli an_out_reg = WM8904_ANALOGUE_OUT1_LEFT;
717a91eb199SMark Brown dcs_l = 0;
718a91eb199SMark Brown dcs_r = 1;
719a91eb199SMark Brown break;
720a91eb199SMark Brown case WM8904_ANALOGUE_LINEOUT_0:
721e4bc6696SMark Brown pwr_reg = WM8904_POWER_MANAGEMENT_3;
722a91eb199SMark Brown dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
723a91eb199SMark Brown dcs_r_reg = WM8904_DC_SERVO_6;
724a91eb199SMark Brown dcs_l_reg = WM8904_DC_SERVO_7;
725472a6309SEmanuele Ghidoli an_out_reg = WM8904_ANALOGUE_OUT2_LEFT;
726a91eb199SMark Brown dcs_l = 2;
727a91eb199SMark Brown dcs_r = 3;
728a91eb199SMark Brown break;
729a91eb199SMark Brown default:
7308d8bb1adSTakashi Iwai WARN(1, "Invalid reg %d\n", reg);
731a91eb199SMark Brown return -EINVAL;
732a91eb199SMark Brown }
733a91eb199SMark Brown
734a91eb199SMark Brown switch (event) {
735e4bc6696SMark Brown case SND_SOC_DAPM_PRE_PMU:
736e4bc6696SMark Brown /* Power on the PGAs */
73746a9100cSKuninori Morimoto snd_soc_component_update_bits(component, pwr_reg,
738e4bc6696SMark Brown WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
739e4bc6696SMark Brown WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
740e4bc6696SMark Brown
741a91eb199SMark Brown /* Power on the amplifier */
74246a9100cSKuninori Morimoto snd_soc_component_update_bits(component, reg,
743a91eb199SMark Brown WM8904_HPL_ENA | WM8904_HPR_ENA,
744a91eb199SMark Brown WM8904_HPL_ENA | WM8904_HPR_ENA);
745a91eb199SMark Brown
746e4bc6696SMark Brown
747a91eb199SMark Brown /* Enable the first stage */
74846a9100cSKuninori Morimoto snd_soc_component_update_bits(component, reg,
749a91eb199SMark Brown WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
750a91eb199SMark Brown WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
751a91eb199SMark Brown
752a91eb199SMark Brown /* Power up the DC servo */
75346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
754a91eb199SMark Brown dcs_mask, dcs_mask);
755a91eb199SMark Brown
756a91eb199SMark Brown /* Either calibrate the DC servo or restore cached state
757a91eb199SMark Brown * if we have that.
758a91eb199SMark Brown */
759a91eb199SMark Brown if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
76046a9100cSKuninori Morimoto dev_dbg(component->dev, "Restoring DC servo state\n");
761a91eb199SMark Brown
76246a9100cSKuninori Morimoto snd_soc_component_write(component, dcs_l_reg,
763a91eb199SMark Brown wm8904->dcs_state[dcs_l]);
76446a9100cSKuninori Morimoto snd_soc_component_write(component, dcs_r_reg,
765a91eb199SMark Brown wm8904->dcs_state[dcs_r]);
766a91eb199SMark Brown
76746a9100cSKuninori Morimoto snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask);
768a91eb199SMark Brown
769a91eb199SMark Brown timeout = 20;
770a91eb199SMark Brown } else {
77146a9100cSKuninori Morimoto dev_dbg(component->dev, "Calibrating DC servo\n");
772a91eb199SMark Brown
77346a9100cSKuninori Morimoto snd_soc_component_write(component, WM8904_DC_SERVO_1,
774a91eb199SMark Brown dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
775a91eb199SMark Brown
776a91eb199SMark Brown timeout = 500;
777a91eb199SMark Brown }
778a91eb199SMark Brown
779a91eb199SMark Brown /* Wait for DC servo to complete */
780a91eb199SMark Brown dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
781a91eb199SMark Brown do {
7826d75dfc3SKuninori Morimoto val = snd_soc_component_read(component, WM8904_DC_SERVO_READBACK_0);
783a91eb199SMark Brown if ((val & dcs_mask) == dcs_mask)
784a91eb199SMark Brown break;
785a91eb199SMark Brown
786a91eb199SMark Brown msleep(1);
787a91eb199SMark Brown } while (--timeout);
788a91eb199SMark Brown
789a91eb199SMark Brown if ((val & dcs_mask) != dcs_mask)
79046a9100cSKuninori Morimoto dev_warn(component->dev, "DC servo timed out\n");
791a91eb199SMark Brown else
79246a9100cSKuninori Morimoto dev_dbg(component->dev, "DC servo ready\n");
793a91eb199SMark Brown
794a91eb199SMark Brown /* Enable the output stage */
79546a9100cSKuninori Morimoto snd_soc_component_update_bits(component, reg,
796a91eb199SMark Brown WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
797a91eb199SMark Brown WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
798472a6309SEmanuele Ghidoli
799472a6309SEmanuele Ghidoli /* Update volume, requires PGA to be powered */
800472a6309SEmanuele Ghidoli val = snd_soc_component_read(component, an_out_reg);
801472a6309SEmanuele Ghidoli snd_soc_component_write(component, an_out_reg, val);
802e4bc6696SMark Brown break;
803a91eb199SMark Brown
804e4bc6696SMark Brown case SND_SOC_DAPM_POST_PMU:
805a91eb199SMark Brown /* Unshort the output itself */
80646a9100cSKuninori Morimoto snd_soc_component_update_bits(component, reg,
807a91eb199SMark Brown WM8904_HPL_RMV_SHORT |
808a91eb199SMark Brown WM8904_HPR_RMV_SHORT,
809a91eb199SMark Brown WM8904_HPL_RMV_SHORT |
810a91eb199SMark Brown WM8904_HPR_RMV_SHORT);
811a91eb199SMark Brown
812a91eb199SMark Brown break;
813a91eb199SMark Brown
814a91eb199SMark Brown case SND_SOC_DAPM_PRE_PMD:
815a91eb199SMark Brown /* Short the output */
81646a9100cSKuninori Morimoto snd_soc_component_update_bits(component, reg,
817a91eb199SMark Brown WM8904_HPL_RMV_SHORT |
818a91eb199SMark Brown WM8904_HPR_RMV_SHORT, 0);
819e4bc6696SMark Brown break;
820a91eb199SMark Brown
821e4bc6696SMark Brown case SND_SOC_DAPM_POST_PMD:
822a91eb199SMark Brown /* Cache the DC servo configuration; this will be
823a91eb199SMark Brown * invalidated if we change the configuration. */
8246d75dfc3SKuninori Morimoto wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg);
8256d75dfc3SKuninori Morimoto wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg);
826a91eb199SMark Brown
82746a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
828a91eb199SMark Brown dcs_mask, 0);
829a91eb199SMark Brown
830a91eb199SMark Brown /* Disable the amplifier input and output stages */
83146a9100cSKuninori Morimoto snd_soc_component_update_bits(component, reg,
832a91eb199SMark Brown WM8904_HPL_ENA | WM8904_HPR_ENA |
833a91eb199SMark Brown WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
834a91eb199SMark Brown WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
835a91eb199SMark Brown 0);
836e4bc6696SMark Brown
837e4bc6696SMark Brown /* PGAs too */
83846a9100cSKuninori Morimoto snd_soc_component_update_bits(component, pwr_reg,
839e4bc6696SMark Brown WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
840e4bc6696SMark Brown 0);
841a91eb199SMark Brown break;
842a91eb199SMark Brown }
843a91eb199SMark Brown
844a91eb199SMark Brown return 0;
845a91eb199SMark Brown }
846a91eb199SMark Brown
8470a05f2e8SMichał Mirosław static const char *input_mode_text[] = {
8480a05f2e8SMichał Mirosław "Single-Ended", "Differential Line", "Differential Mic"
8490a05f2e8SMichał Mirosław };
8500a05f2e8SMichał Mirosław
851a91eb199SMark Brown static const char *lin_text[] = {
852a91eb199SMark Brown "IN1L", "IN2L", "IN3L"
853a91eb199SMark Brown };
854a91eb199SMark Brown
855d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
856d12bfd62STakashi Iwai lin_text);
857a91eb199SMark Brown
858a91eb199SMark Brown static const struct snd_kcontrol_new lin_mux =
859a91eb199SMark Brown SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
860a91eb199SMark Brown
861d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
862d12bfd62STakashi Iwai lin_text);
863a91eb199SMark Brown
864a91eb199SMark Brown static const struct snd_kcontrol_new lin_inv_mux =
86522afe624SMichał Mirosław SOC_DAPM_ENUM("Left Capture Inverting Mux", lin_inv_enum);
866a91eb199SMark Brown
8670a05f2e8SMichał Mirosław static SOC_ENUM_SINGLE_DECL(lin_mode_enum,
8680a05f2e8SMichał Mirosław WM8904_ANALOGUE_LEFT_INPUT_1, 0,
8690a05f2e8SMichał Mirosław input_mode_text);
8700a05f2e8SMichał Mirosław
8710a05f2e8SMichał Mirosław static const struct snd_kcontrol_new lin_mode =
8720a05f2e8SMichał Mirosław SOC_DAPM_ENUM("Left Capture Mode", lin_mode_enum);
8730a05f2e8SMichał Mirosław
874a91eb199SMark Brown static const char *rin_text[] = {
875a91eb199SMark Brown "IN1R", "IN2R", "IN3R"
876a91eb199SMark Brown };
877a91eb199SMark Brown
878d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
879d12bfd62STakashi Iwai rin_text);
880a91eb199SMark Brown
881a91eb199SMark Brown static const struct snd_kcontrol_new rin_mux =
882a91eb199SMark Brown SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
883a91eb199SMark Brown
884d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
885d12bfd62STakashi Iwai rin_text);
886a91eb199SMark Brown
887a91eb199SMark Brown static const struct snd_kcontrol_new rin_inv_mux =
88822afe624SMichał Mirosław SOC_DAPM_ENUM("Right Capture Inverting Mux", rin_inv_enum);
889a91eb199SMark Brown
8900a05f2e8SMichał Mirosław static SOC_ENUM_SINGLE_DECL(rin_mode_enum,
8910a05f2e8SMichał Mirosław WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
8920a05f2e8SMichał Mirosław input_mode_text);
8930a05f2e8SMichał Mirosław
8940a05f2e8SMichał Mirosław static const struct snd_kcontrol_new rin_mode =
8950a05f2e8SMichał Mirosław SOC_DAPM_ENUM("Right Capture Mode", rin_mode_enum);
8960a05f2e8SMichał Mirosław
897a91eb199SMark Brown static const char *aif_text[] = {
898a91eb199SMark Brown "Left", "Right"
899a91eb199SMark Brown };
900a91eb199SMark Brown
901d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
902d12bfd62STakashi Iwai aif_text);
903a91eb199SMark Brown
904a91eb199SMark Brown static const struct snd_kcontrol_new aifoutl_mux =
905a91eb199SMark Brown SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
906a91eb199SMark Brown
907d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
908d12bfd62STakashi Iwai aif_text);
909a91eb199SMark Brown
910a91eb199SMark Brown static const struct snd_kcontrol_new aifoutr_mux =
911a91eb199SMark Brown SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
912a91eb199SMark Brown
913d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
914d12bfd62STakashi Iwai aif_text);
915a91eb199SMark Brown
916a91eb199SMark Brown static const struct snd_kcontrol_new aifinl_mux =
917a91eb199SMark Brown SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
918a91eb199SMark Brown
919d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
920d12bfd62STakashi Iwai aif_text);
921a91eb199SMark Brown
922a91eb199SMark Brown static const struct snd_kcontrol_new aifinr_mux =
923a91eb199SMark Brown SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
924a91eb199SMark Brown
925a91eb199SMark Brown static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
926a91eb199SMark Brown SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
927a91eb199SMark Brown SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
928a91eb199SMark Brown SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
929a91eb199SMark Brown SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
930a91eb199SMark Brown };
931a91eb199SMark Brown
932a91eb199SMark Brown static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
933a91eb199SMark Brown SND_SOC_DAPM_INPUT("IN1L"),
934a91eb199SMark Brown SND_SOC_DAPM_INPUT("IN1R"),
935a91eb199SMark Brown SND_SOC_DAPM_INPUT("IN2L"),
936a91eb199SMark Brown SND_SOC_DAPM_INPUT("IN2R"),
937a91eb199SMark Brown SND_SOC_DAPM_INPUT("IN3L"),
938a91eb199SMark Brown SND_SOC_DAPM_INPUT("IN3R"),
939a91eb199SMark Brown
940dcd658c5SMark Brown SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
941a91eb199SMark Brown
942a91eb199SMark Brown SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
943a91eb199SMark Brown SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
944a91eb199SMark Brown &lin_inv_mux),
9450a05f2e8SMichał Mirosław SND_SOC_DAPM_MUX("Left Capture Mode", SND_SOC_NOPM, 0, 0, &lin_mode),
946a91eb199SMark Brown SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
947a91eb199SMark Brown SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
948a91eb199SMark Brown &rin_inv_mux),
9490a05f2e8SMichał Mirosław SND_SOC_DAPM_MUX("Right Capture Mode", SND_SOC_NOPM, 0, 0, &rin_mode),
950a91eb199SMark Brown
951a91eb199SMark Brown SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
952a91eb199SMark Brown NULL, 0),
953a91eb199SMark Brown SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
954a91eb199SMark Brown NULL, 0),
955a91eb199SMark Brown
956a91eb199SMark Brown SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
957a91eb199SMark Brown SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
958a91eb199SMark Brown
959a91eb199SMark Brown SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
960a91eb199SMark Brown SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
961a91eb199SMark Brown
962a91eb199SMark Brown SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
963a91eb199SMark Brown SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
964a91eb199SMark Brown };
965a91eb199SMark Brown
966a91eb199SMark Brown static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
967a91eb199SMark Brown SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
968a91eb199SMark Brown SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
969a91eb199SMark Brown
970a91eb199SMark Brown SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
971a91eb199SMark Brown SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
972a91eb199SMark Brown
973a91eb199SMark Brown SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
974a91eb199SMark Brown SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
975a91eb199SMark Brown
976a91eb199SMark Brown SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
977a91eb199SMark Brown SND_SOC_DAPM_POST_PMU),
978a91eb199SMark Brown
979e4bc6696SMark Brown SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
980e4bc6696SMark Brown SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
981a91eb199SMark Brown
982e4bc6696SMark Brown SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
983e4bc6696SMark Brown SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
984a91eb199SMark Brown
985a91eb199SMark Brown SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
986a91eb199SMark Brown 0, NULL, 0, out_pga_event,
987e4bc6696SMark Brown SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
988e4bc6696SMark Brown SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
989a91eb199SMark Brown SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
990a91eb199SMark Brown 0, NULL, 0, out_pga_event,
991e4bc6696SMark Brown SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
992e4bc6696SMark Brown SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
993a91eb199SMark Brown
994a91eb199SMark Brown SND_SOC_DAPM_OUTPUT("HPOUTL"),
995a91eb199SMark Brown SND_SOC_DAPM_OUTPUT("HPOUTR"),
996a91eb199SMark Brown SND_SOC_DAPM_OUTPUT("LINEOUTL"),
997a91eb199SMark Brown SND_SOC_DAPM_OUTPUT("LINEOUTR"),
998a91eb199SMark Brown };
999a91eb199SMark Brown
1000a91eb199SMark Brown static const char *out_mux_text[] = {
1001a91eb199SMark Brown "DAC", "Bypass"
1002a91eb199SMark Brown };
1003a91eb199SMark Brown
1004d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
1005d12bfd62STakashi Iwai out_mux_text);
1006a91eb199SMark Brown
1007a91eb199SMark Brown static const struct snd_kcontrol_new hpl_mux =
1008a91eb199SMark Brown SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1009a91eb199SMark Brown
1010d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
1011d12bfd62STakashi Iwai out_mux_text);
1012a91eb199SMark Brown
1013a91eb199SMark Brown static const struct snd_kcontrol_new hpr_mux =
1014a91eb199SMark Brown SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1015a91eb199SMark Brown
1016d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
1017d12bfd62STakashi Iwai out_mux_text);
1018a91eb199SMark Brown
1019a91eb199SMark Brown static const struct snd_kcontrol_new linel_mux =
1020a91eb199SMark Brown SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1021a91eb199SMark Brown
1022d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
1023d12bfd62STakashi Iwai out_mux_text);
1024a91eb199SMark Brown
1025a91eb199SMark Brown static const struct snd_kcontrol_new liner_mux =
1026e94a093cSBo Shen SOC_DAPM_ENUM("LINER Mux", liner_enum);
1027a91eb199SMark Brown
1028a91eb199SMark Brown static const char *sidetone_text[] = {
1029a91eb199SMark Brown "None", "Left", "Right"
1030a91eb199SMark Brown };
1031a91eb199SMark Brown
1032d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
1033d12bfd62STakashi Iwai sidetone_text);
1034a91eb199SMark Brown
1035a91eb199SMark Brown static const struct snd_kcontrol_new dacl_sidetone_mux =
1036a91eb199SMark Brown SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1037a91eb199SMark Brown
1038d12bfd62STakashi Iwai static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
1039d12bfd62STakashi Iwai sidetone_text);
1040a91eb199SMark Brown
1041a91eb199SMark Brown static const struct snd_kcontrol_new dacr_sidetone_mux =
1042a91eb199SMark Brown SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1043a91eb199SMark Brown
1044a91eb199SMark Brown static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1045a91eb199SMark Brown SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1046a91eb199SMark Brown SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1047a91eb199SMark Brown SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1048a91eb199SMark Brown
1049a91eb199SMark Brown SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1050a91eb199SMark Brown SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1051a91eb199SMark Brown
1052a91eb199SMark Brown SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1053a91eb199SMark Brown SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1054a91eb199SMark Brown SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1055a91eb199SMark Brown SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1056a91eb199SMark Brown };
1057a91eb199SMark Brown
1058a91eb199SMark Brown static const struct snd_soc_dapm_route core_intercon[] = {
1059a91eb199SMark Brown { "CLK_DSP", NULL, "SYSCLK" },
1060a91eb199SMark Brown { "TOCLK", NULL, "SYSCLK" },
1061a91eb199SMark Brown };
1062a91eb199SMark Brown
1063a91eb199SMark Brown static const struct snd_soc_dapm_route adc_intercon[] = {
1064a91eb199SMark Brown { "Left Capture Mux", "IN1L", "IN1L" },
1065a91eb199SMark Brown { "Left Capture Mux", "IN2L", "IN2L" },
1066a91eb199SMark Brown { "Left Capture Mux", "IN3L", "IN3L" },
1067a91eb199SMark Brown
1068a91eb199SMark Brown { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1069a91eb199SMark Brown { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1070a91eb199SMark Brown { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1071a91eb199SMark Brown
10720a05f2e8SMichał Mirosław { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" },
10730a05f2e8SMichał Mirosław { "Left Capture Mode", "Differential Line", "Left Capture Mux" },
10740a05f2e8SMichał Mirosław { "Left Capture Mode", "Differential Line", "Left Capture Inverting Mux" },
10750a05f2e8SMichał Mirosław { "Left Capture Mode", "Differential Mic", "Left Capture Mux" },
10760a05f2e8SMichał Mirosław { "Left Capture Mode", "Differential Mic", "Left Capture Inverting Mux" },
10770a05f2e8SMichał Mirosław
1078a91eb199SMark Brown { "Right Capture Mux", "IN1R", "IN1R" },
1079a91eb199SMark Brown { "Right Capture Mux", "IN2R", "IN2R" },
1080a91eb199SMark Brown { "Right Capture Mux", "IN3R", "IN3R" },
1081a91eb199SMark Brown
1082a91eb199SMark Brown { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1083a91eb199SMark Brown { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1084a91eb199SMark Brown { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1085a91eb199SMark Brown
10860a05f2e8SMichał Mirosław { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" },
10870a05f2e8SMichał Mirosław { "Right Capture Mode", "Differential Line", "Right Capture Mux" },
10880a05f2e8SMichał Mirosław { "Right Capture Mode", "Differential Line", "Right Capture Inverting Mux" },
10890a05f2e8SMichał Mirosław { "Right Capture Mode", "Differential Mic", "Right Capture Mux" },
10900a05f2e8SMichał Mirosław { "Right Capture Mode", "Differential Mic", "Right Capture Inverting Mux" },
1091a91eb199SMark Brown
10920a05f2e8SMichał Mirosław { "Left Capture PGA", NULL, "Left Capture Mode" },
10930a05f2e8SMichał Mirosław { "Right Capture PGA", NULL, "Right Capture Mode" },
1094a91eb199SMark Brown
1095a30c188bSBo Shen { "AIFOUTL Mux", "Left", "ADCL" },
1096a30c188bSBo Shen { "AIFOUTL Mux", "Right", "ADCR" },
1097a30c188bSBo Shen { "AIFOUTR Mux", "Left", "ADCL" },
1098a30c188bSBo Shen { "AIFOUTR Mux", "Right", "ADCR" },
1099a30c188bSBo Shen
1100a30c188bSBo Shen { "AIFOUTL", NULL, "AIFOUTL Mux" },
1101a30c188bSBo Shen { "AIFOUTR", NULL, "AIFOUTR Mux" },
1102a91eb199SMark Brown
1103a91eb199SMark Brown { "ADCL", NULL, "CLK_DSP" },
1104a91eb199SMark Brown { "ADCL", NULL, "Left Capture PGA" },
1105a91eb199SMark Brown
1106a91eb199SMark Brown { "ADCR", NULL, "CLK_DSP" },
1107a91eb199SMark Brown { "ADCR", NULL, "Right Capture PGA" },
1108a91eb199SMark Brown };
1109a91eb199SMark Brown
1110a91eb199SMark Brown static const struct snd_soc_dapm_route dac_intercon[] = {
1111a30c188bSBo Shen { "DACL Mux", "Left", "AIFINL" },
1112a30c188bSBo Shen { "DACL Mux", "Right", "AIFINR" },
1113a30c188bSBo Shen
1114a30c188bSBo Shen { "DACR Mux", "Left", "AIFINL" },
1115a30c188bSBo Shen { "DACR Mux", "Right", "AIFINR" },
1116a30c188bSBo Shen
1117a30c188bSBo Shen { "DACL", NULL, "DACL Mux" },
1118a91eb199SMark Brown { "DACL", NULL, "CLK_DSP" },
1119a91eb199SMark Brown
1120a30c188bSBo Shen { "DACR", NULL, "DACR Mux" },
1121a91eb199SMark Brown { "DACR", NULL, "CLK_DSP" },
1122a91eb199SMark Brown
1123a91eb199SMark Brown { "Charge pump", NULL, "SYSCLK" },
1124a91eb199SMark Brown
1125a91eb199SMark Brown { "Headphone Output", NULL, "HPL PGA" },
1126a91eb199SMark Brown { "Headphone Output", NULL, "HPR PGA" },
1127a91eb199SMark Brown { "Headphone Output", NULL, "Charge pump" },
1128a91eb199SMark Brown { "Headphone Output", NULL, "TOCLK" },
1129a91eb199SMark Brown
1130a91eb199SMark Brown { "Line Output", NULL, "LINEL PGA" },
1131a91eb199SMark Brown { "Line Output", NULL, "LINER PGA" },
1132a91eb199SMark Brown { "Line Output", NULL, "Charge pump" },
1133a91eb199SMark Brown { "Line Output", NULL, "TOCLK" },
1134a91eb199SMark Brown
1135a91eb199SMark Brown { "HPOUTL", NULL, "Headphone Output" },
1136a91eb199SMark Brown { "HPOUTR", NULL, "Headphone Output" },
1137a91eb199SMark Brown
1138a91eb199SMark Brown { "LINEOUTL", NULL, "Line Output" },
1139a91eb199SMark Brown { "LINEOUTR", NULL, "Line Output" },
1140a91eb199SMark Brown };
1141a91eb199SMark Brown
1142a91eb199SMark Brown static const struct snd_soc_dapm_route wm8904_intercon[] = {
1143a91eb199SMark Brown { "Left Sidetone", "Left", "ADCL" },
1144a91eb199SMark Brown { "Left Sidetone", "Right", "ADCR" },
1145a91eb199SMark Brown { "DACL", NULL, "Left Sidetone" },
1146a91eb199SMark Brown
1147a91eb199SMark Brown { "Right Sidetone", "Left", "ADCL" },
1148a91eb199SMark Brown { "Right Sidetone", "Right", "ADCR" },
1149a91eb199SMark Brown { "DACR", NULL, "Right Sidetone" },
1150a91eb199SMark Brown
1151a91eb199SMark Brown { "Left Bypass", NULL, "Class G" },
1152a91eb199SMark Brown { "Left Bypass", NULL, "Left Capture PGA" },
1153a91eb199SMark Brown
1154a91eb199SMark Brown { "Right Bypass", NULL, "Class G" },
1155a91eb199SMark Brown { "Right Bypass", NULL, "Right Capture PGA" },
1156a91eb199SMark Brown
1157a91eb199SMark Brown { "HPL Mux", "DAC", "DACL" },
1158a91eb199SMark Brown { "HPL Mux", "Bypass", "Left Bypass" },
1159a91eb199SMark Brown
1160a91eb199SMark Brown { "HPR Mux", "DAC", "DACR" },
1161a91eb199SMark Brown { "HPR Mux", "Bypass", "Right Bypass" },
1162a91eb199SMark Brown
1163a91eb199SMark Brown { "LINEL Mux", "DAC", "DACL" },
1164a91eb199SMark Brown { "LINEL Mux", "Bypass", "Left Bypass" },
1165a91eb199SMark Brown
1166a91eb199SMark Brown { "LINER Mux", "DAC", "DACR" },
1167a91eb199SMark Brown { "LINER Mux", "Bypass", "Right Bypass" },
1168a91eb199SMark Brown
1169a91eb199SMark Brown { "HPL PGA", NULL, "HPL Mux" },
1170a91eb199SMark Brown { "HPR PGA", NULL, "HPR Mux" },
1171a91eb199SMark Brown
1172a91eb199SMark Brown { "LINEL PGA", NULL, "LINEL Mux" },
1173a91eb199SMark Brown { "LINER PGA", NULL, "LINER Mux" },
1174a91eb199SMark Brown };
1175a91eb199SMark Brown
11768c126474SMark Brown static const struct snd_soc_dapm_route wm8912_intercon[] = {
11778c126474SMark Brown { "HPL PGA", NULL, "DACL" },
11788c126474SMark Brown { "HPR PGA", NULL, "DACR" },
11798c126474SMark Brown
11808c126474SMark Brown { "LINEL PGA", NULL, "DACL" },
11818c126474SMark Brown { "LINER PGA", NULL, "DACR" },
11828c126474SMark Brown };
11838c126474SMark Brown
wm8904_add_widgets(struct snd_soc_component * component)118446a9100cSKuninori Morimoto static int wm8904_add_widgets(struct snd_soc_component *component)
1185a91eb199SMark Brown {
118646a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
118746a9100cSKuninori Morimoto struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
11888c126474SMark Brown
1189ce6120ccSLiam Girdwood snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
11908c126474SMark Brown ARRAY_SIZE(wm8904_core_dapm_widgets));
1191ce6120ccSLiam Girdwood snd_soc_dapm_add_routes(dapm, core_intercon,
11928c126474SMark Brown ARRAY_SIZE(core_intercon));
11938c126474SMark Brown
11948c126474SMark Brown switch (wm8904->devtype) {
11958c126474SMark Brown case WM8904:
119646a9100cSKuninori Morimoto snd_soc_add_component_controls(component, wm8904_adc_snd_controls,
1197a91eb199SMark Brown ARRAY_SIZE(wm8904_adc_snd_controls));
119846a9100cSKuninori Morimoto snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
1199a91eb199SMark Brown ARRAY_SIZE(wm8904_dac_snd_controls));
120046a9100cSKuninori Morimoto snd_soc_add_component_controls(component, wm8904_snd_controls,
1201a91eb199SMark Brown ARRAY_SIZE(wm8904_snd_controls));
1202a91eb199SMark Brown
1203ce6120ccSLiam Girdwood snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
1204a91eb199SMark Brown ARRAY_SIZE(wm8904_adc_dapm_widgets));
1205ce6120ccSLiam Girdwood snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1206a91eb199SMark Brown ARRAY_SIZE(wm8904_dac_dapm_widgets));
1207ce6120ccSLiam Girdwood snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
1208a91eb199SMark Brown ARRAY_SIZE(wm8904_dapm_widgets));
1209a91eb199SMark Brown
1210ce6120ccSLiam Girdwood snd_soc_dapm_add_routes(dapm, adc_intercon,
12118c126474SMark Brown ARRAY_SIZE(adc_intercon));
1212ce6120ccSLiam Girdwood snd_soc_dapm_add_routes(dapm, dac_intercon,
12138c126474SMark Brown ARRAY_SIZE(dac_intercon));
1214ce6120ccSLiam Girdwood snd_soc_dapm_add_routes(dapm, wm8904_intercon,
1215a91eb199SMark Brown ARRAY_SIZE(wm8904_intercon));
12168c126474SMark Brown break;
12178c126474SMark Brown
12188c126474SMark Brown case WM8912:
121946a9100cSKuninori Morimoto snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
12208c126474SMark Brown ARRAY_SIZE(wm8904_dac_snd_controls));
12218c126474SMark Brown
1222ce6120ccSLiam Girdwood snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
12238c126474SMark Brown ARRAY_SIZE(wm8904_dac_dapm_widgets));
12248c126474SMark Brown
1225ce6120ccSLiam Girdwood snd_soc_dapm_add_routes(dapm, dac_intercon,
12268c126474SMark Brown ARRAY_SIZE(dac_intercon));
1227ce6120ccSLiam Girdwood snd_soc_dapm_add_routes(dapm, wm8912_intercon,
12288c126474SMark Brown ARRAY_SIZE(wm8912_intercon));
12298c126474SMark Brown break;
12308c126474SMark Brown }
1231a91eb199SMark Brown
1232a91eb199SMark Brown return 0;
1233a91eb199SMark Brown }
1234a91eb199SMark Brown
1235a91eb199SMark Brown static struct {
1236a91eb199SMark Brown int ratio;
1237a91eb199SMark Brown unsigned int clk_sys_rate;
1238a91eb199SMark Brown } clk_sys_rates[] = {
1239a91eb199SMark Brown { 64, 0 },
1240a91eb199SMark Brown { 128, 1 },
1241a91eb199SMark Brown { 192, 2 },
1242a91eb199SMark Brown { 256, 3 },
1243a91eb199SMark Brown { 384, 4 },
1244a91eb199SMark Brown { 512, 5 },
1245a91eb199SMark Brown { 786, 6 },
1246a91eb199SMark Brown { 1024, 7 },
1247a91eb199SMark Brown { 1408, 8 },
1248a91eb199SMark Brown { 1536, 9 },
1249a91eb199SMark Brown };
1250a91eb199SMark Brown
1251a91eb199SMark Brown static struct {
1252a91eb199SMark Brown int rate;
1253a91eb199SMark Brown int sample_rate;
1254a91eb199SMark Brown } sample_rates[] = {
1255a91eb199SMark Brown { 8000, 0 },
1256a91eb199SMark Brown { 11025, 1 },
1257a91eb199SMark Brown { 12000, 1 },
1258a91eb199SMark Brown { 16000, 2 },
1259a91eb199SMark Brown { 22050, 3 },
1260a91eb199SMark Brown { 24000, 3 },
1261a91eb199SMark Brown { 32000, 4 },
1262a91eb199SMark Brown { 44100, 5 },
1263a91eb199SMark Brown { 48000, 5 },
1264a91eb199SMark Brown };
1265a91eb199SMark Brown
1266a91eb199SMark Brown static struct {
1267a91eb199SMark Brown int div; /* *10 due to .5s */
1268a91eb199SMark Brown int bclk_div;
1269a91eb199SMark Brown } bclk_divs[] = {
1270a91eb199SMark Brown { 10, 0 },
1271a91eb199SMark Brown { 15, 1 },
1272a91eb199SMark Brown { 20, 2 },
1273a91eb199SMark Brown { 30, 3 },
1274a91eb199SMark Brown { 40, 4 },
1275a91eb199SMark Brown { 50, 5 },
1276a91eb199SMark Brown { 55, 6 },
1277a91eb199SMark Brown { 60, 7 },
1278a91eb199SMark Brown { 80, 8 },
1279a91eb199SMark Brown { 100, 9 },
1280a91eb199SMark Brown { 110, 10 },
1281a91eb199SMark Brown { 120, 11 },
1282a91eb199SMark Brown { 160, 12 },
1283a91eb199SMark Brown { 200, 13 },
1284a91eb199SMark Brown { 220, 14 },
1285a91eb199SMark Brown { 240, 16 },
1286a91eb199SMark Brown { 200, 17 },
1287a91eb199SMark Brown { 320, 18 },
1288a91eb199SMark Brown { 440, 19 },
1289a91eb199SMark Brown { 480, 20 },
1290a91eb199SMark Brown };
1291a91eb199SMark Brown
1292a91eb199SMark Brown
wm8904_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1293a91eb199SMark Brown static int wm8904_hw_params(struct snd_pcm_substream *substream,
1294a91eb199SMark Brown struct snd_pcm_hw_params *params,
1295a91eb199SMark Brown struct snd_soc_dai *dai)
1296a91eb199SMark Brown {
129746a9100cSKuninori Morimoto struct snd_soc_component *component = dai->component;
129846a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1299a91eb199SMark Brown int ret, i, best, best_val, cur_val;
1300a91eb199SMark Brown unsigned int aif1 = 0;
1301a91eb199SMark Brown unsigned int aif2 = 0;
1302a91eb199SMark Brown unsigned int aif3 = 0;
1303a91eb199SMark Brown unsigned int clock1 = 0;
1304a91eb199SMark Brown unsigned int dac_digital1 = 0;
1305a91eb199SMark Brown
1306a91eb199SMark Brown /* What BCLK do we need? */
1307a91eb199SMark Brown wm8904->fs = params_rate(params);
1308a91eb199SMark Brown if (wm8904->tdm_slots) {
130946a9100cSKuninori Morimoto dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
1310a91eb199SMark Brown wm8904->tdm_slots, wm8904->tdm_width);
1311a91eb199SMark Brown wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1312a91eb199SMark Brown wm8904->tdm_width, 2,
1313a91eb199SMark Brown wm8904->tdm_slots);
1314a91eb199SMark Brown } else {
1315a91eb199SMark Brown wm8904->bclk = snd_soc_params_to_bclk(params);
1316a91eb199SMark Brown }
1317a91eb199SMark Brown
13182f44b043SMark Brown switch (params_width(params)) {
13192f44b043SMark Brown case 16:
132056927eb0SMark Brown break;
13212f44b043SMark Brown case 20:
132256927eb0SMark Brown aif1 |= 0x40;
132356927eb0SMark Brown break;
13242f44b043SMark Brown case 24:
132556927eb0SMark Brown aif1 |= 0x80;
132656927eb0SMark Brown break;
13272f44b043SMark Brown case 32:
132856927eb0SMark Brown aif1 |= 0xc0;
132956927eb0SMark Brown break;
133056927eb0SMark Brown default:
133156927eb0SMark Brown return -EINVAL;
133256927eb0SMark Brown }
133356927eb0SMark Brown
133456927eb0SMark Brown
133546a9100cSKuninori Morimoto dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1336a91eb199SMark Brown
133746a9100cSKuninori Morimoto ret = wm8904_configure_clocking(component);
1338a91eb199SMark Brown if (ret != 0)
1339a91eb199SMark Brown return ret;
1340a91eb199SMark Brown
1341a91eb199SMark Brown /* Select nearest CLK_SYS_RATE */
1342a91eb199SMark Brown best = 0;
1343a91eb199SMark Brown best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1344a91eb199SMark Brown - wm8904->fs);
1345a91eb199SMark Brown for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1346a91eb199SMark Brown cur_val = abs((wm8904->sysclk_rate /
1347ef995e3aSJoe Perches clk_sys_rates[i].ratio) - wm8904->fs);
1348a91eb199SMark Brown if (cur_val < best_val) {
1349a91eb199SMark Brown best = i;
1350a91eb199SMark Brown best_val = cur_val;
1351a91eb199SMark Brown }
1352a91eb199SMark Brown }
135346a9100cSKuninori Morimoto dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1354a91eb199SMark Brown clk_sys_rates[best].ratio);
1355a91eb199SMark Brown clock1 |= (clk_sys_rates[best].clk_sys_rate
1356a91eb199SMark Brown << WM8904_CLK_SYS_RATE_SHIFT);
1357a91eb199SMark Brown
1358a91eb199SMark Brown /* SAMPLE_RATE */
1359a91eb199SMark Brown best = 0;
1360a91eb199SMark Brown best_val = abs(wm8904->fs - sample_rates[0].rate);
1361a91eb199SMark Brown for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1362a91eb199SMark Brown /* Closest match */
1363a91eb199SMark Brown cur_val = abs(wm8904->fs - sample_rates[i].rate);
1364a91eb199SMark Brown if (cur_val < best_val) {
1365a91eb199SMark Brown best = i;
1366a91eb199SMark Brown best_val = cur_val;
1367a91eb199SMark Brown }
1368a91eb199SMark Brown }
136946a9100cSKuninori Morimoto dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1370a91eb199SMark Brown sample_rates[best].rate);
1371a91eb199SMark Brown clock1 |= (sample_rates[best].sample_rate
1372a91eb199SMark Brown << WM8904_SAMPLE_RATE_SHIFT);
1373a91eb199SMark Brown
1374a91eb199SMark Brown /* Enable sloping stopband filter for low sample rates */
1375a91eb199SMark Brown if (wm8904->fs <= 24000)
1376a91eb199SMark Brown dac_digital1 |= WM8904_DAC_SB_FILT;
1377a91eb199SMark Brown
1378a91eb199SMark Brown /* BCLK_DIV */
1379a91eb199SMark Brown best = 0;
1380a91eb199SMark Brown best_val = INT_MAX;
1381a91eb199SMark Brown for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1382a91eb199SMark Brown cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1383a91eb199SMark Brown - wm8904->bclk;
1384a91eb199SMark Brown if (cur_val < 0) /* Table is sorted */
1385a91eb199SMark Brown break;
1386a91eb199SMark Brown if (cur_val < best_val) {
1387a91eb199SMark Brown best = i;
1388a91eb199SMark Brown best_val = cur_val;
1389a91eb199SMark Brown }
1390a91eb199SMark Brown }
1391a91eb199SMark Brown wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
139246a9100cSKuninori Morimoto dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1393a91eb199SMark Brown bclk_divs[best].div, wm8904->bclk);
1394a91eb199SMark Brown aif2 |= bclk_divs[best].bclk_div;
1395a91eb199SMark Brown
1396a91eb199SMark Brown /* LRCLK is a simple fraction of BCLK */
139746a9100cSKuninori Morimoto dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1398a91eb199SMark Brown aif3 |= wm8904->bclk / wm8904->fs;
1399a91eb199SMark Brown
1400a91eb199SMark Brown /* Apply the settings */
140146a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
1402a91eb199SMark Brown WM8904_DAC_SB_FILT, dac_digital1);
140346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1404a91eb199SMark Brown WM8904_AIF_WL_MASK, aif1);
140546a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2,
1406a91eb199SMark Brown WM8904_BCLK_DIV_MASK, aif2);
140746a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
1408a91eb199SMark Brown WM8904_LRCLK_RATE_MASK, aif3);
140946a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1,
1410a91eb199SMark Brown WM8904_SAMPLE_RATE_MASK |
1411a91eb199SMark Brown WM8904_CLK_SYS_RATE_MASK, clock1);
1412a91eb199SMark Brown
1413a91eb199SMark Brown /* Update filters for the new settings */
141446a9100cSKuninori Morimoto wm8904_set_retune_mobile(component);
141546a9100cSKuninori Morimoto wm8904_set_deemph(component);
1416a91eb199SMark Brown
1417a91eb199SMark Brown return 0;
1418a91eb199SMark Brown }
1419a91eb199SMark Brown
wm8904_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)1420a91eb199SMark Brown static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1421a91eb199SMark Brown {
142246a9100cSKuninori Morimoto struct snd_soc_component *component = dai->component;
1423a91eb199SMark Brown unsigned int aif1 = 0;
1424a91eb199SMark Brown unsigned int aif3 = 0;
1425a91eb199SMark Brown
1426a91eb199SMark Brown switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1427a91eb199SMark Brown case SND_SOC_DAIFMT_CBS_CFS:
1428a91eb199SMark Brown break;
1429a91eb199SMark Brown case SND_SOC_DAIFMT_CBS_CFM:
1430a91eb199SMark Brown aif3 |= WM8904_LRCLK_DIR;
1431a91eb199SMark Brown break;
1432a91eb199SMark Brown case SND_SOC_DAIFMT_CBM_CFS:
1433a91eb199SMark Brown aif1 |= WM8904_BCLK_DIR;
1434a91eb199SMark Brown break;
1435a91eb199SMark Brown case SND_SOC_DAIFMT_CBM_CFM:
1436a91eb199SMark Brown aif1 |= WM8904_BCLK_DIR;
1437a91eb199SMark Brown aif3 |= WM8904_LRCLK_DIR;
1438a91eb199SMark Brown break;
1439a91eb199SMark Brown default:
1440a91eb199SMark Brown return -EINVAL;
1441a91eb199SMark Brown }
1442a91eb199SMark Brown
1443a91eb199SMark Brown switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1444a91eb199SMark Brown case SND_SOC_DAIFMT_DSP_B:
1445f0199bc5SBo Shen aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
14463e146b55SGustavo A. R. Silva fallthrough;
1447a91eb199SMark Brown case SND_SOC_DAIFMT_DSP_A:
1448a91eb199SMark Brown aif1 |= 0x3;
1449a91eb199SMark Brown break;
1450a91eb199SMark Brown case SND_SOC_DAIFMT_I2S:
1451a91eb199SMark Brown aif1 |= 0x2;
1452a91eb199SMark Brown break;
1453a91eb199SMark Brown case SND_SOC_DAIFMT_RIGHT_J:
1454a91eb199SMark Brown break;
1455a91eb199SMark Brown case SND_SOC_DAIFMT_LEFT_J:
1456a91eb199SMark Brown aif1 |= 0x1;
1457a91eb199SMark Brown break;
1458a91eb199SMark Brown default:
1459a91eb199SMark Brown return -EINVAL;
1460a91eb199SMark Brown }
1461a91eb199SMark Brown
1462a91eb199SMark Brown switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1463a91eb199SMark Brown case SND_SOC_DAIFMT_DSP_A:
1464a91eb199SMark Brown case SND_SOC_DAIFMT_DSP_B:
1465a91eb199SMark Brown /* frame inversion not valid for DSP modes */
1466a91eb199SMark Brown switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1467a91eb199SMark Brown case SND_SOC_DAIFMT_NB_NF:
1468a91eb199SMark Brown break;
1469a91eb199SMark Brown case SND_SOC_DAIFMT_IB_NF:
1470a91eb199SMark Brown aif1 |= WM8904_AIF_BCLK_INV;
1471a91eb199SMark Brown break;
1472a91eb199SMark Brown default:
1473a91eb199SMark Brown return -EINVAL;
1474a91eb199SMark Brown }
1475a91eb199SMark Brown break;
1476a91eb199SMark Brown
1477a91eb199SMark Brown case SND_SOC_DAIFMT_I2S:
1478a91eb199SMark Brown case SND_SOC_DAIFMT_RIGHT_J:
1479a91eb199SMark Brown case SND_SOC_DAIFMT_LEFT_J:
1480a91eb199SMark Brown switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1481a91eb199SMark Brown case SND_SOC_DAIFMT_NB_NF:
1482a91eb199SMark Brown break;
1483a91eb199SMark Brown case SND_SOC_DAIFMT_IB_IF:
1484a91eb199SMark Brown aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1485a91eb199SMark Brown break;
1486a91eb199SMark Brown case SND_SOC_DAIFMT_IB_NF:
1487a91eb199SMark Brown aif1 |= WM8904_AIF_BCLK_INV;
1488a91eb199SMark Brown break;
1489a91eb199SMark Brown case SND_SOC_DAIFMT_NB_IF:
1490a91eb199SMark Brown aif1 |= WM8904_AIF_LRCLK_INV;
1491a91eb199SMark Brown break;
1492a91eb199SMark Brown default:
1493a91eb199SMark Brown return -EINVAL;
1494a91eb199SMark Brown }
1495a91eb199SMark Brown break;
1496a91eb199SMark Brown default:
1497a91eb199SMark Brown return -EINVAL;
1498a91eb199SMark Brown }
1499a91eb199SMark Brown
150046a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1501a91eb199SMark Brown WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1502a91eb199SMark Brown WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
150346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
1504a91eb199SMark Brown WM8904_LRCLK_DIR, aif3);
1505a91eb199SMark Brown
1506a91eb199SMark Brown return 0;
1507a91eb199SMark Brown }
1508a91eb199SMark Brown
1509a91eb199SMark Brown
wm8904_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1510a91eb199SMark Brown static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1511a91eb199SMark Brown unsigned int rx_mask, int slots, int slot_width)
1512a91eb199SMark Brown {
151346a9100cSKuninori Morimoto struct snd_soc_component *component = dai->component;
151446a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1515a91eb199SMark Brown int aif1 = 0;
1516a91eb199SMark Brown
1517a91eb199SMark Brown /* Don't need to validate anything if we're turning off TDM */
1518a91eb199SMark Brown if (slots == 0)
1519a91eb199SMark Brown goto out;
1520a91eb199SMark Brown
1521a91eb199SMark Brown /* Note that we allow configurations we can't handle ourselves -
1522a91eb199SMark Brown * for example, we can generate clocks for slots 2 and up even if
1523a91eb199SMark Brown * we can't use those slots ourselves.
1524a91eb199SMark Brown */
1525a91eb199SMark Brown aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1526a91eb199SMark Brown
1527a91eb199SMark Brown switch (rx_mask) {
1528a91eb199SMark Brown case 3:
1529a91eb199SMark Brown break;
1530a91eb199SMark Brown case 0xc:
1531a91eb199SMark Brown aif1 |= WM8904_AIFADC_TDM_CHAN;
1532a91eb199SMark Brown break;
1533a91eb199SMark Brown default:
1534a91eb199SMark Brown return -EINVAL;
1535a91eb199SMark Brown }
1536a91eb199SMark Brown
1537a91eb199SMark Brown
1538a91eb199SMark Brown switch (tx_mask) {
1539a91eb199SMark Brown case 3:
1540a91eb199SMark Brown break;
1541a91eb199SMark Brown case 0xc:
1542a91eb199SMark Brown aif1 |= WM8904_AIFDAC_TDM_CHAN;
1543a91eb199SMark Brown break;
1544a91eb199SMark Brown default:
1545a91eb199SMark Brown return -EINVAL;
1546a91eb199SMark Brown }
1547a91eb199SMark Brown
1548a91eb199SMark Brown out:
1549a91eb199SMark Brown wm8904->tdm_width = slot_width;
1550a91eb199SMark Brown wm8904->tdm_slots = slots / 2;
1551a91eb199SMark Brown
155246a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1553a91eb199SMark Brown WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1554a91eb199SMark Brown WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1555a91eb199SMark Brown
1556a91eb199SMark Brown return 0;
1557a91eb199SMark Brown }
1558a91eb199SMark Brown
1559a91eb199SMark Brown struct _fll_div {
1560a91eb199SMark Brown u16 fll_fratio;
1561a91eb199SMark Brown u16 fll_outdiv;
1562a91eb199SMark Brown u16 fll_clk_ref_div;
1563a91eb199SMark Brown u16 n;
1564a91eb199SMark Brown u16 k;
1565a91eb199SMark Brown };
1566a91eb199SMark Brown
1567a91eb199SMark Brown /* The size in bits of the FLL divide multiplied by 10
1568a91eb199SMark Brown * to allow rounding later */
1569a91eb199SMark Brown #define FIXED_FLL_SIZE ((1 << 16) * 10)
1570a91eb199SMark Brown
1571a91eb199SMark Brown static struct {
1572a91eb199SMark Brown unsigned int min;
1573a91eb199SMark Brown unsigned int max;
1574a91eb199SMark Brown u16 fll_fratio;
1575a91eb199SMark Brown int ratio;
1576a91eb199SMark Brown } fll_fratios[] = {
1577a91eb199SMark Brown { 0, 64000, 4, 16 },
1578a91eb199SMark Brown { 64000, 128000, 3, 8 },
1579a91eb199SMark Brown { 128000, 256000, 2, 4 },
1580a91eb199SMark Brown { 256000, 1000000, 1, 2 },
1581a91eb199SMark Brown { 1000000, 13500000, 0, 1 },
1582a91eb199SMark Brown };
1583a91eb199SMark Brown
fll_factors(struct _fll_div * fll_div,unsigned int Fref,unsigned int Fout)1584a91eb199SMark Brown static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1585a91eb199SMark Brown unsigned int Fout)
1586a91eb199SMark Brown {
1587a91eb199SMark Brown u64 Kpart;
1588a91eb199SMark Brown unsigned int K, Ndiv, Nmod, target;
1589a91eb199SMark Brown unsigned int div;
1590a91eb199SMark Brown int i;
1591a91eb199SMark Brown
1592a91eb199SMark Brown /* Fref must be <=13.5MHz */
1593a91eb199SMark Brown div = 1;
1594a91eb199SMark Brown fll_div->fll_clk_ref_div = 0;
1595a91eb199SMark Brown while ((Fref / div) > 13500000) {
1596a91eb199SMark Brown div *= 2;
1597a91eb199SMark Brown fll_div->fll_clk_ref_div++;
1598a91eb199SMark Brown
1599a91eb199SMark Brown if (div > 8) {
1600a91eb199SMark Brown pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1601a91eb199SMark Brown Fref);
1602a91eb199SMark Brown return -EINVAL;
1603a91eb199SMark Brown }
1604a91eb199SMark Brown }
1605a91eb199SMark Brown
1606a91eb199SMark Brown pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1607a91eb199SMark Brown
1608a91eb199SMark Brown /* Apply the division for our remaining calculations */
1609a91eb199SMark Brown Fref /= div;
1610a91eb199SMark Brown
1611a91eb199SMark Brown /* Fvco should be 90-100MHz; don't check the upper bound */
1612a91eb199SMark Brown div = 4;
1613a91eb199SMark Brown while (Fout * div < 90000000) {
1614a91eb199SMark Brown div++;
1615a91eb199SMark Brown if (div > 64) {
1616a91eb199SMark Brown pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1617a91eb199SMark Brown Fout);
1618a91eb199SMark Brown return -EINVAL;
1619a91eb199SMark Brown }
1620a91eb199SMark Brown }
1621a91eb199SMark Brown target = Fout * div;
1622a91eb199SMark Brown fll_div->fll_outdiv = div - 1;
1623a91eb199SMark Brown
1624a91eb199SMark Brown pr_debug("Fvco=%dHz\n", target);
1625a91eb199SMark Brown
162625985edcSLucas De Marchi /* Find an appropriate FLL_FRATIO and factor it out of the target */
1627a91eb199SMark Brown for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1628a91eb199SMark Brown if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1629a91eb199SMark Brown fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1630a91eb199SMark Brown target /= fll_fratios[i].ratio;
1631a91eb199SMark Brown break;
1632a91eb199SMark Brown }
1633a91eb199SMark Brown }
1634a91eb199SMark Brown if (i == ARRAY_SIZE(fll_fratios)) {
1635a91eb199SMark Brown pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1636a91eb199SMark Brown return -EINVAL;
1637a91eb199SMark Brown }
1638a91eb199SMark Brown
1639a91eb199SMark Brown /* Now, calculate N.K */
1640a91eb199SMark Brown Ndiv = target / Fref;
1641a91eb199SMark Brown
1642a91eb199SMark Brown fll_div->n = Ndiv;
1643a91eb199SMark Brown Nmod = target % Fref;
1644a91eb199SMark Brown pr_debug("Nmod=%d\n", Nmod);
1645a91eb199SMark Brown
1646a91eb199SMark Brown /* Calculate fractional part - scale up so we can round. */
1647a91eb199SMark Brown Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1648a91eb199SMark Brown
1649a91eb199SMark Brown do_div(Kpart, Fref);
1650a91eb199SMark Brown
1651a91eb199SMark Brown K = Kpart & 0xFFFFFFFF;
1652a91eb199SMark Brown
1653a91eb199SMark Brown if ((K % 10) >= 5)
1654a91eb199SMark Brown K += 5;
1655a91eb199SMark Brown
1656a91eb199SMark Brown /* Move down to proper range now rounding is done */
1657a91eb199SMark Brown fll_div->k = K / 10;
1658a91eb199SMark Brown
1659a91eb199SMark Brown pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1660a91eb199SMark Brown fll_div->n, fll_div->k,
1661a91eb199SMark Brown fll_div->fll_fratio, fll_div->fll_outdiv,
1662a91eb199SMark Brown fll_div->fll_clk_ref_div);
1663a91eb199SMark Brown
1664a91eb199SMark Brown return 0;
1665a91eb199SMark Brown }
1666a91eb199SMark Brown
wm8904_set_fll(struct snd_soc_dai * dai,int fll_id,int source,unsigned int Fref,unsigned int Fout)1667a91eb199SMark Brown static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1668a91eb199SMark Brown unsigned int Fref, unsigned int Fout)
1669a91eb199SMark Brown {
167046a9100cSKuninori Morimoto struct snd_soc_component *component = dai->component;
167146a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1672a91eb199SMark Brown struct _fll_div fll_div;
1673a91eb199SMark Brown int ret, val;
1674a91eb199SMark Brown int clock2, fll1;
1675a91eb199SMark Brown
1676a91eb199SMark Brown /* Any change? */
1677a91eb199SMark Brown if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1678a91eb199SMark Brown Fout == wm8904->fll_fout)
1679a91eb199SMark Brown return 0;
1680a91eb199SMark Brown
16816d75dfc3SKuninori Morimoto clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
168218240b67SMark Brown
1683a91eb199SMark Brown if (Fout == 0) {
168446a9100cSKuninori Morimoto dev_dbg(component->dev, "FLL disabled\n");
1685a91eb199SMark Brown
1686a91eb199SMark Brown wm8904->fll_fref = 0;
1687a91eb199SMark Brown wm8904->fll_fout = 0;
1688a91eb199SMark Brown
1689a91eb199SMark Brown /* Gate SYSCLK to avoid glitches */
169046a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1691a91eb199SMark Brown WM8904_CLK_SYS_ENA, 0);
1692a91eb199SMark Brown
169346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1694a91eb199SMark Brown WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1695a91eb199SMark Brown
1696a91eb199SMark Brown goto out;
1697a91eb199SMark Brown }
1698a91eb199SMark Brown
1699a91eb199SMark Brown /* Validate the FLL ID */
1700a91eb199SMark Brown switch (source) {
1701a91eb199SMark Brown case WM8904_FLL_MCLK:
1702a91eb199SMark Brown case WM8904_FLL_LRCLK:
1703a91eb199SMark Brown case WM8904_FLL_BCLK:
1704a91eb199SMark Brown ret = fll_factors(&fll_div, Fref, Fout);
1705a91eb199SMark Brown if (ret != 0)
1706a91eb199SMark Brown return ret;
1707a91eb199SMark Brown break;
1708a91eb199SMark Brown
1709a91eb199SMark Brown case WM8904_FLL_FREE_RUNNING:
171046a9100cSKuninori Morimoto dev_dbg(component->dev, "Using free running FLL\n");
1711a91eb199SMark Brown /* Force 12MHz and output/4 for now */
1712a91eb199SMark Brown Fout = 12000000;
1713a91eb199SMark Brown Fref = 12000000;
1714a91eb199SMark Brown
1715a91eb199SMark Brown memset(&fll_div, 0, sizeof(fll_div));
1716a91eb199SMark Brown fll_div.fll_outdiv = 3;
1717a91eb199SMark Brown break;
1718a91eb199SMark Brown
1719a91eb199SMark Brown default:
172046a9100cSKuninori Morimoto dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
1721a91eb199SMark Brown return -EINVAL;
1722a91eb199SMark Brown }
1723a91eb199SMark Brown
1724a91eb199SMark Brown /* Save current state then disable the FLL and SYSCLK to avoid
1725a91eb199SMark Brown * misclocking */
17266d75dfc3SKuninori Morimoto fll1 = snd_soc_component_read(component, WM8904_FLL_CONTROL_1);
172746a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1728a91eb199SMark Brown WM8904_CLK_SYS_ENA, 0);
172946a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1730a91eb199SMark Brown WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1731a91eb199SMark Brown
1732a91eb199SMark Brown /* Unlock forced oscilator control to switch it on/off */
173346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
1734a91eb199SMark Brown WM8904_USER_KEY, WM8904_USER_KEY);
1735a91eb199SMark Brown
1736a91eb199SMark Brown if (fll_id == WM8904_FLL_FREE_RUNNING) {
1737a91eb199SMark Brown val = WM8904_FLL_FRC_NCO;
1738a91eb199SMark Brown } else {
1739a91eb199SMark Brown val = 0;
1740a91eb199SMark Brown }
1741a91eb199SMark Brown
174246a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1743a91eb199SMark Brown val);
174446a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
1745a91eb199SMark Brown WM8904_USER_KEY, 0);
1746a91eb199SMark Brown
1747a91eb199SMark Brown switch (fll_id) {
1748a91eb199SMark Brown case WM8904_FLL_MCLK:
174946a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1750a91eb199SMark Brown WM8904_FLL_CLK_REF_SRC_MASK, 0);
1751a91eb199SMark Brown break;
1752a91eb199SMark Brown
1753a91eb199SMark Brown case WM8904_FLL_LRCLK:
175446a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1755a91eb199SMark Brown WM8904_FLL_CLK_REF_SRC_MASK, 1);
1756a91eb199SMark Brown break;
1757a91eb199SMark Brown
1758a91eb199SMark Brown case WM8904_FLL_BCLK:
175946a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1760a91eb199SMark Brown WM8904_FLL_CLK_REF_SRC_MASK, 2);
1761a91eb199SMark Brown break;
1762a91eb199SMark Brown }
1763a91eb199SMark Brown
1764a91eb199SMark Brown if (fll_div.k)
1765a91eb199SMark Brown val = WM8904_FLL_FRACN_ENA;
1766a91eb199SMark Brown else
1767a91eb199SMark Brown val = 0;
176846a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1769a91eb199SMark Brown WM8904_FLL_FRACN_ENA, val);
1770a91eb199SMark Brown
177146a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2,
1772a91eb199SMark Brown WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1773a91eb199SMark Brown (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1774a91eb199SMark Brown (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1775a91eb199SMark Brown
177646a9100cSKuninori Morimoto snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k);
1777a91eb199SMark Brown
177846a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1779a91eb199SMark Brown fll_div.n << WM8904_FLL_N_SHIFT);
1780a91eb199SMark Brown
178146a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1782a91eb199SMark Brown WM8904_FLL_CLK_REF_DIV_MASK,
1783a91eb199SMark Brown fll_div.fll_clk_ref_div
1784a91eb199SMark Brown << WM8904_FLL_CLK_REF_DIV_SHIFT);
1785a91eb199SMark Brown
178646a9100cSKuninori Morimoto dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1787a91eb199SMark Brown
1788a91eb199SMark Brown wm8904->fll_fref = Fref;
1789a91eb199SMark Brown wm8904->fll_fout = Fout;
1790a91eb199SMark Brown wm8904->fll_src = source;
1791a91eb199SMark Brown
1792a91eb199SMark Brown /* Enable the FLL if it was previously active */
179346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1794a91eb199SMark Brown WM8904_FLL_OSC_ENA, fll1);
179546a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1796a91eb199SMark Brown WM8904_FLL_ENA, fll1);
1797a91eb199SMark Brown
1798a91eb199SMark Brown out:
1799a91eb199SMark Brown /* Reenable SYSCLK if it was previously active */
180046a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1801a91eb199SMark Brown WM8904_CLK_SYS_ENA, clock2);
1802a91eb199SMark Brown
1803a91eb199SMark Brown return 0;
1804a91eb199SMark Brown }
1805a91eb199SMark Brown
wm8904_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)180613409d27SMichael Walle static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
180713409d27SMichael Walle unsigned int freq, int dir)
180813409d27SMichael Walle {
180913409d27SMichael Walle struct snd_soc_component *component = dai->component;
181013409d27SMichael Walle struct wm8904_priv *priv = snd_soc_component_get_drvdata(component);
181113409d27SMichael Walle unsigned long mclk_freq;
181213409d27SMichael Walle int ret;
181313409d27SMichael Walle
181413409d27SMichael Walle switch (clk_id) {
181513409d27SMichael Walle case WM8904_CLK_AUTO:
18162a0bda27SMichael Walle /* We don't have any rate constraints, so just ignore the
18172a0bda27SMichael Walle * request to disable constraining.
18182a0bda27SMichael Walle */
18192a0bda27SMichael Walle if (!freq)
18202a0bda27SMichael Walle return 0;
18212a0bda27SMichael Walle
182213409d27SMichael Walle mclk_freq = clk_get_rate(priv->mclk);
182313409d27SMichael Walle /* enable FLL if a different sysclk is desired */
182413409d27SMichael Walle if (mclk_freq != freq) {
182513409d27SMichael Walle priv->sysclk_src = WM8904_CLK_FLL;
182613409d27SMichael Walle ret = wm8904_set_fll(dai, WM8904_FLL_MCLK,
182713409d27SMichael Walle WM8904_FLL_MCLK,
182813409d27SMichael Walle mclk_freq, freq);
182913409d27SMichael Walle if (ret)
183013409d27SMichael Walle return ret;
183113409d27SMichael Walle break;
183213409d27SMichael Walle }
183313409d27SMichael Walle clk_id = WM8904_CLK_MCLK;
18343e146b55SGustavo A. R. Silva fallthrough;
183513409d27SMichael Walle
183613409d27SMichael Walle case WM8904_CLK_MCLK:
183713409d27SMichael Walle priv->sysclk_src = clk_id;
183813409d27SMichael Walle priv->mclk_rate = freq;
183913409d27SMichael Walle break;
184013409d27SMichael Walle
184113409d27SMichael Walle case WM8904_CLK_FLL:
184213409d27SMichael Walle priv->sysclk_src = clk_id;
184313409d27SMichael Walle break;
184413409d27SMichael Walle
184513409d27SMichael Walle default:
184613409d27SMichael Walle return -EINVAL;
184713409d27SMichael Walle }
184813409d27SMichael Walle
184913409d27SMichael Walle dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
185013409d27SMichael Walle
185113409d27SMichael Walle wm8904_configure_clocking(component);
185213409d27SMichael Walle
185313409d27SMichael Walle return 0;
185413409d27SMichael Walle }
185513409d27SMichael Walle
wm8904_mute(struct snd_soc_dai * codec_dai,int mute,int direction)185626d3c16eSKuninori Morimoto static int wm8904_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1857a91eb199SMark Brown {
185846a9100cSKuninori Morimoto struct snd_soc_component *component = codec_dai->component;
1859a91eb199SMark Brown int val;
1860a91eb199SMark Brown
1861a91eb199SMark Brown if (mute)
1862a91eb199SMark Brown val = WM8904_DAC_MUTE;
1863a91eb199SMark Brown else
1864a91eb199SMark Brown val = 0;
1865a91eb199SMark Brown
186646a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1867a91eb199SMark Brown
1868a91eb199SMark Brown return 0;
1869a91eb199SMark Brown }
1870a91eb199SMark Brown
wm8904_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)187146a9100cSKuninori Morimoto static int wm8904_set_bias_level(struct snd_soc_component *component,
1872a91eb199SMark Brown enum snd_soc_bias_level level)
1873a91eb199SMark Brown {
187446a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1875c1334218SMark Brown int ret;
1876a91eb199SMark Brown
1877a91eb199SMark Brown switch (level) {
1878a91eb199SMark Brown case SND_SOC_BIAS_ON:
1879a91eb199SMark Brown break;
1880a91eb199SMark Brown
1881a91eb199SMark Brown case SND_SOC_BIAS_PREPARE:
1882a91eb199SMark Brown /* VMID resistance 2*50k */
188346a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1884a91eb199SMark Brown WM8904_VMID_RES_MASK,
1885a91eb199SMark Brown 0x1 << WM8904_VMID_RES_SHIFT);
1886a91eb199SMark Brown
1887a91eb199SMark Brown /* Normal bias current */
188846a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1889a91eb199SMark Brown WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1890a91eb199SMark Brown break;
1891a91eb199SMark Brown
1892a91eb199SMark Brown case SND_SOC_BIAS_STANDBY:
189346a9100cSKuninori Morimoto if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1894a91eb199SMark Brown ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1895a91eb199SMark Brown wm8904->supplies);
1896a91eb199SMark Brown if (ret != 0) {
189746a9100cSKuninori Morimoto dev_err(component->dev,
1898a91eb199SMark Brown "Failed to enable supplies: %d\n",
1899a91eb199SMark Brown ret);
1900a91eb199SMark Brown return ret;
1901a91eb199SMark Brown }
1902a91eb199SMark Brown
19035489e81fSMichał Mirosław ret = clk_prepare_enable(wm8904->mclk);
19045489e81fSMichał Mirosław if (ret) {
19055489e81fSMichał Mirosław dev_err(component->dev,
19065489e81fSMichał Mirosław "Failed to enable MCLK: %d\n", ret);
19075489e81fSMichał Mirosław regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
19085489e81fSMichał Mirosław wm8904->supplies);
19095489e81fSMichał Mirosław return ret;
19105489e81fSMichał Mirosław }
19115489e81fSMichał Mirosław
1912c1b88ee2SMark Brown regcache_cache_only(wm8904->regmap, false);
191384d0d831SMark Brown regcache_sync(wm8904->regmap);
1914a91eb199SMark Brown
1915a91eb199SMark Brown /* Enable bias */
191646a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1917a91eb199SMark Brown WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1918a91eb199SMark Brown
1919a91eb199SMark Brown /* Enable VMID, VMID buffering, 2*5k resistance */
192046a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1921a91eb199SMark Brown WM8904_VMID_ENA |
1922a91eb199SMark Brown WM8904_VMID_RES_MASK,
1923a91eb199SMark Brown WM8904_VMID_ENA |
1924a91eb199SMark Brown 0x3 << WM8904_VMID_RES_SHIFT);
1925a91eb199SMark Brown
1926a91eb199SMark Brown /* Let VMID ramp */
1927a91eb199SMark Brown msleep(1);
1928a91eb199SMark Brown }
1929a91eb199SMark Brown
1930a91eb199SMark Brown /* Maintain VMID with 2*250k */
193146a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1932a91eb199SMark Brown WM8904_VMID_RES_MASK,
1933a91eb199SMark Brown 0x2 << WM8904_VMID_RES_SHIFT);
1934a91eb199SMark Brown
1935a91eb199SMark Brown /* Bias current *0.5 */
193646a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1937a91eb199SMark Brown WM8904_ISEL_MASK, 0);
1938a91eb199SMark Brown break;
1939a91eb199SMark Brown
1940a91eb199SMark Brown case SND_SOC_BIAS_OFF:
1941a91eb199SMark Brown /* Turn off VMID */
194246a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1943a91eb199SMark Brown WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1944a91eb199SMark Brown
1945a91eb199SMark Brown /* Stop bias generation */
194646a9100cSKuninori Morimoto snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1947a91eb199SMark Brown WM8904_BIAS_ENA, 0);
1948a91eb199SMark Brown
1949e9149b8cSMichael Walle snd_soc_component_write(component, WM8904_SW_RESET_AND_ID, 0);
1950c1b88ee2SMark Brown regcache_cache_only(wm8904->regmap, true);
1951c1b88ee2SMark Brown regcache_mark_dirty(wm8904->regmap);
1952c1334218SMark Brown
1953a91eb199SMark Brown regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1954a91eb199SMark Brown wm8904->supplies);
19558b9920e3SBo Shen clk_disable_unprepare(wm8904->mclk);
1956a91eb199SMark Brown break;
1957a91eb199SMark Brown }
1958a91eb199SMark Brown return 0;
1959a91eb199SMark Brown }
1960a91eb199SMark Brown
1961a91eb199SMark Brown #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1962a91eb199SMark Brown
1963a91eb199SMark Brown #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1964a91eb199SMark Brown SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1965a91eb199SMark Brown
196685e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops wm8904_dai_ops = {
1967a91eb199SMark Brown .set_sysclk = wm8904_set_sysclk,
1968a91eb199SMark Brown .set_fmt = wm8904_set_fmt,
1969a91eb199SMark Brown .set_tdm_slot = wm8904_set_tdm_slot,
1970a91eb199SMark Brown .set_pll = wm8904_set_fll,
1971a91eb199SMark Brown .hw_params = wm8904_hw_params,
197226d3c16eSKuninori Morimoto .mute_stream = wm8904_mute,
197326d3c16eSKuninori Morimoto .no_capture_mute = 1,
1974a91eb199SMark Brown };
1975a91eb199SMark Brown
1976f0fba2adSLiam Girdwood static struct snd_soc_dai_driver wm8904_dai = {
1977f0fba2adSLiam Girdwood .name = "wm8904-hifi",
1978a91eb199SMark Brown .playback = {
1979a91eb199SMark Brown .stream_name = "Playback",
1980a91eb199SMark Brown .channels_min = 2,
1981a91eb199SMark Brown .channels_max = 2,
1982a91eb199SMark Brown .rates = WM8904_RATES,
1983a91eb199SMark Brown .formats = WM8904_FORMATS,
1984a91eb199SMark Brown },
1985a91eb199SMark Brown .capture = {
1986a91eb199SMark Brown .stream_name = "Capture",
1987a91eb199SMark Brown .channels_min = 2,
1988a91eb199SMark Brown .channels_max = 2,
1989a91eb199SMark Brown .rates = WM8904_RATES,
1990a91eb199SMark Brown .formats = WM8904_FORMATS,
1991a91eb199SMark Brown },
1992a91eb199SMark Brown .ops = &wm8904_dai_ops,
199307695752SKuninori Morimoto .symmetric_rate = 1,
1994a91eb199SMark Brown };
1995a91eb199SMark Brown
wm8904_handle_retune_mobile_pdata(struct snd_soc_component * component)199646a9100cSKuninori Morimoto static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component)
1997a91eb199SMark Brown {
199846a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1999a91eb199SMark Brown struct wm8904_pdata *pdata = wm8904->pdata;
2000a91eb199SMark Brown struct snd_kcontrol_new control =
2001a91eb199SMark Brown SOC_ENUM_EXT("EQ Mode",
2002a91eb199SMark Brown wm8904->retune_mobile_enum,
2003a91eb199SMark Brown wm8904_get_retune_mobile_enum,
2004a91eb199SMark Brown wm8904_put_retune_mobile_enum);
2005a91eb199SMark Brown int ret, i, j;
2006a91eb199SMark Brown const char **t;
2007a91eb199SMark Brown
2008a91eb199SMark Brown /* We need an array of texts for the enum API but the number
2009a91eb199SMark Brown * of texts is likely to be less than the number of
2010a91eb199SMark Brown * configurations due to the sample rate dependency of the
2011a91eb199SMark Brown * configurations. */
2012a91eb199SMark Brown wm8904->num_retune_mobile_texts = 0;
2013a91eb199SMark Brown wm8904->retune_mobile_texts = NULL;
2014a91eb199SMark Brown for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2015a91eb199SMark Brown for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
2016a91eb199SMark Brown if (strcmp(pdata->retune_mobile_cfgs[i].name,
2017a91eb199SMark Brown wm8904->retune_mobile_texts[j]) == 0)
2018a91eb199SMark Brown break;
2019a91eb199SMark Brown }
2020a91eb199SMark Brown
2021a91eb199SMark Brown if (j != wm8904->num_retune_mobile_texts)
2022a91eb199SMark Brown continue;
2023a91eb199SMark Brown
2024a91eb199SMark Brown /* Expand the array... */
2025a91eb199SMark Brown t = krealloc(wm8904->retune_mobile_texts,
2026a91eb199SMark Brown sizeof(char *) *
2027a91eb199SMark Brown (wm8904->num_retune_mobile_texts + 1),
2028a91eb199SMark Brown GFP_KERNEL);
2029a91eb199SMark Brown if (t == NULL)
2030a91eb199SMark Brown continue;
2031a91eb199SMark Brown
2032a91eb199SMark Brown /* ...store the new entry... */
2033a91eb199SMark Brown t[wm8904->num_retune_mobile_texts] =
2034a91eb199SMark Brown pdata->retune_mobile_cfgs[i].name;
2035a91eb199SMark Brown
2036a91eb199SMark Brown /* ...and remember the new version. */
2037a91eb199SMark Brown wm8904->num_retune_mobile_texts++;
2038a91eb199SMark Brown wm8904->retune_mobile_texts = t;
2039a91eb199SMark Brown }
2040a91eb199SMark Brown
204146a9100cSKuninori Morimoto dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
2042a91eb199SMark Brown wm8904->num_retune_mobile_texts);
2043a91eb199SMark Brown
20449a8d38dbSTakashi Iwai wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
2045a91eb199SMark Brown wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2046a91eb199SMark Brown
204746a9100cSKuninori Morimoto ret = snd_soc_add_component_controls(component, &control, 1);
2048a91eb199SMark Brown if (ret != 0)
204946a9100cSKuninori Morimoto dev_err(component->dev,
2050a91eb199SMark Brown "Failed to add ReTune Mobile control: %d\n", ret);
2051a91eb199SMark Brown }
2052a91eb199SMark Brown
wm8904_handle_pdata(struct snd_soc_component * component)205346a9100cSKuninori Morimoto static void wm8904_handle_pdata(struct snd_soc_component *component)
2054a91eb199SMark Brown {
205546a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2056a91eb199SMark Brown struct wm8904_pdata *pdata = wm8904->pdata;
2057a91eb199SMark Brown int ret, i;
2058a91eb199SMark Brown
2059a91eb199SMark Brown if (!pdata) {
206046a9100cSKuninori Morimoto snd_soc_add_component_controls(component, wm8904_eq_controls,
2061a91eb199SMark Brown ARRAY_SIZE(wm8904_eq_controls));
2062a91eb199SMark Brown return;
2063a91eb199SMark Brown }
2064a91eb199SMark Brown
206546a9100cSKuninori Morimoto dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2066a91eb199SMark Brown
2067a91eb199SMark Brown if (pdata->num_drc_cfgs) {
2068a91eb199SMark Brown struct snd_kcontrol_new control =
2069a91eb199SMark Brown SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2070a91eb199SMark Brown wm8904_get_drc_enum, wm8904_put_drc_enum);
2071a91eb199SMark Brown
2072a91eb199SMark Brown /* We need an array of texts for the enum API */
20736da2ec56SKees Cook wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs,
20746da2ec56SKees Cook sizeof(char *),
20756da2ec56SKees Cook GFP_KERNEL);
2076d931099bSSachin Kamat if (!wm8904->drc_texts)
2077a91eb199SMark Brown return;
2078a91eb199SMark Brown
2079a91eb199SMark Brown for (i = 0; i < pdata->num_drc_cfgs; i++)
2080a91eb199SMark Brown wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2081a91eb199SMark Brown
20829a8d38dbSTakashi Iwai wm8904->drc_enum.items = pdata->num_drc_cfgs;
2083a91eb199SMark Brown wm8904->drc_enum.texts = wm8904->drc_texts;
2084a91eb199SMark Brown
208546a9100cSKuninori Morimoto ret = snd_soc_add_component_controls(component, &control, 1);
2086a91eb199SMark Brown if (ret != 0)
208746a9100cSKuninori Morimoto dev_err(component->dev,
2088a91eb199SMark Brown "Failed to add DRC mode control: %d\n", ret);
2089a91eb199SMark Brown
209046a9100cSKuninori Morimoto wm8904_set_drc(component);
2091a91eb199SMark Brown }
2092a91eb199SMark Brown
209346a9100cSKuninori Morimoto dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
2094a91eb199SMark Brown pdata->num_retune_mobile_cfgs);
2095a91eb199SMark Brown
2096a91eb199SMark Brown if (pdata->num_retune_mobile_cfgs)
209746a9100cSKuninori Morimoto wm8904_handle_retune_mobile_pdata(component);
2098a91eb199SMark Brown else
209946a9100cSKuninori Morimoto snd_soc_add_component_controls(component, wm8904_eq_controls,
2100a91eb199SMark Brown ARRAY_SIZE(wm8904_eq_controls));
2101a91eb199SMark Brown }
2102a91eb199SMark Brown
2103f0fba2adSLiam Girdwood
wm8904_probe(struct snd_soc_component * component)210446a9100cSKuninori Morimoto static int wm8904_probe(struct snd_soc_component *component)
2105a91eb199SMark Brown {
210646a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2107a91eb199SMark Brown
21088c126474SMark Brown switch (wm8904->devtype) {
21098c126474SMark Brown case WM8904:
21108c126474SMark Brown break;
21118c126474SMark Brown case WM8912:
21128c126474SMark Brown memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
21138c126474SMark Brown break;
21148c126474SMark Brown default:
211546a9100cSKuninori Morimoto dev_err(component->dev, "Unknown device type %d\n",
21168c126474SMark Brown wm8904->devtype);
2117f0fba2adSLiam Girdwood return -EINVAL;
21188c126474SMark Brown }
21198c126474SMark Brown
212046a9100cSKuninori Morimoto wm8904_handle_pdata(component);
2121a91eb199SMark Brown
212246a9100cSKuninori Morimoto wm8904_add_widgets(component);
2123a91eb199SMark Brown
2124a91eb199SMark Brown return 0;
2125a91eb199SMark Brown }
2126a91eb199SMark Brown
wm8904_remove(struct snd_soc_component * component)212746a9100cSKuninori Morimoto static void wm8904_remove(struct snd_soc_component *component)
2128a91eb199SMark Brown {
212946a9100cSKuninori Morimoto struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2130f0fba2adSLiam Girdwood
2131cd70978cSAxel Lin kfree(wm8904->retune_mobile_texts);
2132cd70978cSAxel Lin kfree(wm8904->drc_texts);
2133a91eb199SMark Brown }
2134a91eb199SMark Brown
213546a9100cSKuninori Morimoto static const struct snd_soc_component_driver soc_component_dev_wm8904 = {
2136f0fba2adSLiam Girdwood .probe = wm8904_probe,
2137f0fba2adSLiam Girdwood .remove = wm8904_remove,
2138f0fba2adSLiam Girdwood .set_bias_level = wm8904_set_bias_level,
213946a9100cSKuninori Morimoto .use_pmdown_time = 1,
214046a9100cSKuninori Morimoto .endianness = 1,
214184d0d831SMark Brown };
214284d0d831SMark Brown
214384d0d831SMark Brown static const struct regmap_config wm8904_regmap = {
214484d0d831SMark Brown .reg_bits = 8,
214584d0d831SMark Brown .val_bits = 16,
214684d0d831SMark Brown
214784d0d831SMark Brown .max_register = WM8904_MAX_REGISTER,
214884d0d831SMark Brown .volatile_reg = wm8904_volatile_register,
214984d0d831SMark Brown .readable_reg = wm8904_readable_register,
215084d0d831SMark Brown
21519bd4bc4cSMark Brown .cache_type = REGCACHE_MAPLE,
215284d0d831SMark Brown .reg_defaults = wm8904_reg_defaults,
215384d0d831SMark Brown .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
2154f0fba2adSLiam Girdwood };
2155f0fba2adSLiam Girdwood
2156b1a5fad5SAlexander Morozov #ifdef CONFIG_OF
2157b1a5fad5SAlexander Morozov static const struct of_device_id wm8904_of_match[] = {
2158b1a5fad5SAlexander Morozov {
2159b1a5fad5SAlexander Morozov .compatible = "wlf,wm8904",
2160fb82c6edSMichał Mirosław .data = (void *)WM8904,
2161b1a5fad5SAlexander Morozov }, {
2162b1a5fad5SAlexander Morozov .compatible = "wlf,wm8912",
2163fb82c6edSMichał Mirosław .data = (void *)WM8912,
2164b1a5fad5SAlexander Morozov }, {
2165b1a5fad5SAlexander Morozov /* sentinel */
2166b1a5fad5SAlexander Morozov }
2167b1a5fad5SAlexander Morozov };
2168b1a5fad5SAlexander Morozov MODULE_DEVICE_TABLE(of, wm8904_of_match);
2169b1a5fad5SAlexander Morozov #endif
2170b1a5fad5SAlexander Morozov
21716d8f318bSStephen Kitt static const struct i2c_device_id wm8904_i2c_id[];
21726d8f318bSStephen Kitt
wm8904_i2c_probe(struct i2c_client * i2c)21736d8f318bSStephen Kitt static int wm8904_i2c_probe(struct i2c_client *i2c)
2174a91eb199SMark Brown {
2175a91eb199SMark Brown struct wm8904_priv *wm8904;
217603862cf6SMark Brown unsigned int val;
217703862cf6SMark Brown int ret, i;
2178a91eb199SMark Brown
217993e26d4eSMark Brown wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
218093e26d4eSMark Brown GFP_KERNEL);
2181a91eb199SMark Brown if (wm8904 == NULL)
2182a91eb199SMark Brown return -ENOMEM;
2183a91eb199SMark Brown
21848b9920e3SBo Shen wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
21858b9920e3SBo Shen if (IS_ERR(wm8904->mclk)) {
21868b9920e3SBo Shen ret = PTR_ERR(wm8904->mclk);
21878b9920e3SBo Shen dev_err(&i2c->dev, "Failed to get MCLK\n");
21888b9920e3SBo Shen return ret;
21898b9920e3SBo Shen }
21908b9920e3SBo Shen
2191d633edd9SMark Brown wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
219284d0d831SMark Brown if (IS_ERR(wm8904->regmap)) {
219384d0d831SMark Brown ret = PTR_ERR(wm8904->regmap);
219484d0d831SMark Brown dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
219584d0d831SMark Brown ret);
219684d0d831SMark Brown return ret;
219784d0d831SMark Brown }
219884d0d831SMark Brown
2199b1a5fad5SAlexander Morozov if (i2c->dev.of_node) {
2200b1a5fad5SAlexander Morozov const struct of_device_id *match;
2201b1a5fad5SAlexander Morozov
2202b1a5fad5SAlexander Morozov match = of_match_node(wm8904_of_match, i2c->dev.of_node);
2203b1a5fad5SAlexander Morozov if (match == NULL)
2204b1a5fad5SAlexander Morozov return -EINVAL;
2205*5a180332SKrzysztof Kozlowski wm8904->devtype = (uintptr_t)match->data;
2206b1a5fad5SAlexander Morozov } else {
22076d8f318bSStephen Kitt const struct i2c_device_id *id =
22086d8f318bSStephen Kitt i2c_match_id(wm8904_i2c_id, i2c);
22098c126474SMark Brown wm8904->devtype = id->driver_data;
2210b1a5fad5SAlexander Morozov }
2211b1a5fad5SAlexander Morozov
2212a91eb199SMark Brown i2c_set_clientdata(i2c, wm8904);
2213a91eb199SMark Brown wm8904->pdata = i2c->dev.platform_data;
2214a91eb199SMark Brown
221503862cf6SMark Brown for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
221603862cf6SMark Brown wm8904->supplies[i].supply = wm8904_supply_names[i];
221703862cf6SMark Brown
221803862cf6SMark Brown ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
221903862cf6SMark Brown wm8904->supplies);
222003862cf6SMark Brown if (ret != 0) {
222103862cf6SMark Brown dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
222203862cf6SMark Brown return ret;
222303862cf6SMark Brown }
222403862cf6SMark Brown
222503862cf6SMark Brown ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
222603862cf6SMark Brown wm8904->supplies);
222703862cf6SMark Brown if (ret != 0) {
222803862cf6SMark Brown dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
222903862cf6SMark Brown return ret;
223003862cf6SMark Brown }
223103862cf6SMark Brown
223203862cf6SMark Brown ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
223303862cf6SMark Brown if (ret < 0) {
223403862cf6SMark Brown dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
223503862cf6SMark Brown goto err_enable;
223603862cf6SMark Brown }
223703862cf6SMark Brown if (val != 0x8904) {
223803862cf6SMark Brown dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
223903862cf6SMark Brown ret = -EINVAL;
224003862cf6SMark Brown goto err_enable;
224103862cf6SMark Brown }
224203862cf6SMark Brown
224303862cf6SMark Brown ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
224403862cf6SMark Brown if (ret < 0) {
224503862cf6SMark Brown dev_err(&i2c->dev, "Failed to read device revision: %d\n",
224603862cf6SMark Brown ret);
224703862cf6SMark Brown goto err_enable;
224803862cf6SMark Brown }
224903862cf6SMark Brown dev_info(&i2c->dev, "revision %c\n", val + 'A');
225003862cf6SMark Brown
225103862cf6SMark Brown ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
225203862cf6SMark Brown if (ret < 0) {
225303862cf6SMark Brown dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
225403862cf6SMark Brown goto err_enable;
225503862cf6SMark Brown }
225603862cf6SMark Brown
2257725e7a7bSMark Brown /* Change some default settings - latch VU and enable ZC */
2258725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2259725e7a7bSMark Brown WM8904_ADC_VU, WM8904_ADC_VU);
2260725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2261725e7a7bSMark Brown WM8904_ADC_VU, WM8904_ADC_VU);
2262725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2263725e7a7bSMark Brown WM8904_DAC_VU, WM8904_DAC_VU);
2264725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2265725e7a7bSMark Brown WM8904_DAC_VU, WM8904_DAC_VU);
2266725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2267725e7a7bSMark Brown WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2268725e7a7bSMark Brown WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2269725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2270725e7a7bSMark Brown WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2271725e7a7bSMark Brown WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2272725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2273725e7a7bSMark Brown WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2274725e7a7bSMark Brown WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2275725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2276725e7a7bSMark Brown WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2277725e7a7bSMark Brown WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2278725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2279725e7a7bSMark Brown WM8904_SR_MODE, 0);
2280725e7a7bSMark Brown
2281725e7a7bSMark Brown /* Apply configuration from the platform data. */
2282725e7a7bSMark Brown if (wm8904->pdata) {
2283725e7a7bSMark Brown for (i = 0; i < WM8904_GPIO_REGS; i++) {
2284725e7a7bSMark Brown if (!wm8904->pdata->gpio_cfg[i])
2285725e7a7bSMark Brown continue;
2286725e7a7bSMark Brown
2287725e7a7bSMark Brown regmap_update_bits(wm8904->regmap,
2288725e7a7bSMark Brown WM8904_GPIO_CONTROL_1 + i,
2289725e7a7bSMark Brown 0xffff,
2290725e7a7bSMark Brown wm8904->pdata->gpio_cfg[i]);
2291725e7a7bSMark Brown }
2292725e7a7bSMark Brown
2293725e7a7bSMark Brown /* Zero is the default value for these anyway */
2294725e7a7bSMark Brown for (i = 0; i < WM8904_MIC_REGS; i++)
2295725e7a7bSMark Brown regmap_update_bits(wm8904->regmap,
2296725e7a7bSMark Brown WM8904_MIC_BIAS_CONTROL_0 + i,
2297725e7a7bSMark Brown 0xffff,
2298725e7a7bSMark Brown wm8904->pdata->mic_cfg[i]);
2299725e7a7bSMark Brown }
2300725e7a7bSMark Brown
2301725e7a7bSMark Brown /* Set Class W by default - this will be managed by the Class
2302725e7a7bSMark Brown * G widget at runtime where bypass paths are available.
2303725e7a7bSMark Brown */
2304725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2305725e7a7bSMark Brown WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2306725e7a7bSMark Brown
2307725e7a7bSMark Brown /* Use normal bias source */
2308725e7a7bSMark Brown regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2309725e7a7bSMark Brown WM8904_POBCTRL, 0);
2310725e7a7bSMark Brown
2311f061e2beSMark Brown /* Fill the cache for the ADC test register */
2312f061e2beSMark Brown regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val);
2313f061e2beSMark Brown
231403862cf6SMark Brown /* Can leave the device powered off until we need it */
231503862cf6SMark Brown regcache_cache_only(wm8904->regmap, true);
231603862cf6SMark Brown regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
231703862cf6SMark Brown
231846a9100cSKuninori Morimoto ret = devm_snd_soc_register_component(&i2c->dev,
231946a9100cSKuninori Morimoto &soc_component_dev_wm8904, &wm8904_dai, 1);
232084d0d831SMark Brown if (ret != 0)
232103862cf6SMark Brown return ret;
232293e26d4eSMark Brown
232384d0d831SMark Brown return 0;
232484d0d831SMark Brown
232503862cf6SMark Brown err_enable:
232603862cf6SMark Brown regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2327f0fba2adSLiam Girdwood return ret;
2328a91eb199SMark Brown }
2329a91eb199SMark Brown
2330a91eb199SMark Brown static const struct i2c_device_id wm8904_i2c_id[] = {
23318c126474SMark Brown { "wm8904", WM8904 },
23328c126474SMark Brown { "wm8912", WM8912 },
2333df1553c8SMark Brown { "wm8918", WM8904 }, /* Actually a subset, updates to follow */
2334a91eb199SMark Brown { }
2335a91eb199SMark Brown };
2336a91eb199SMark Brown MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2337a91eb199SMark Brown
2338a91eb199SMark Brown static struct i2c_driver wm8904_i2c_driver = {
2339a91eb199SMark Brown .driver = {
2340091edccfSMark Brown .name = "wm8904",
2341b1a5fad5SAlexander Morozov .of_match_table = of_match_ptr(wm8904_of_match),
2342a91eb199SMark Brown },
23439abcd240SUwe Kleine-König .probe = wm8904_i2c_probe,
2344a91eb199SMark Brown .id_table = wm8904_i2c_id,
2345a91eb199SMark Brown };
2346a91eb199SMark Brown
23478cb28fd6SMark Brown module_i2c_driver(wm8904_i2c_driver);
2348a91eb199SMark Brown
2349a91eb199SMark Brown MODULE_DESCRIPTION("ASoC WM8904 driver");
2350a91eb199SMark Brown MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2351a91eb199SMark Brown MODULE_LICENSE("GPL");
2352