1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2018 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan
24e098bc96SEvan Quan #include <linux/delay.h>
25e098bc96SEvan Quan #include <linux/module.h>
26e098bc96SEvan Quan #include <linux/slab.h>
27e098bc96SEvan Quan
28e098bc96SEvan Quan #include "hwmgr.h"
29e098bc96SEvan Quan #include "amd_powerplay.h"
30e098bc96SEvan Quan #include "vega20_smumgr.h"
31e098bc96SEvan Quan #include "hardwaremanager.h"
32e098bc96SEvan Quan #include "ppatomfwctrl.h"
33e098bc96SEvan Quan #include "atomfirmware.h"
34e098bc96SEvan Quan #include "cgs_common.h"
35e098bc96SEvan Quan #include "vega20_powertune.h"
36e098bc96SEvan Quan #include "vega20_inc.h"
37e098bc96SEvan Quan #include "pppcielanes.h"
38e098bc96SEvan Quan #include "vega20_hwmgr.h"
39e098bc96SEvan Quan #include "vega20_processpptables.h"
40e098bc96SEvan Quan #include "vega20_pptable.h"
41e098bc96SEvan Quan #include "vega20_thermal.h"
42e098bc96SEvan Quan #include "vega20_ppsmc.h"
43e098bc96SEvan Quan #include "pp_debug.h"
44e098bc96SEvan Quan #include "amd_pcie_helpers.h"
45e098bc96SEvan Quan #include "ppinterrupt.h"
46e098bc96SEvan Quan #include "pp_overdriver.h"
47e098bc96SEvan Quan #include "pp_thermal.h"
48e098bc96SEvan Quan #include "soc15_common.h"
49e098bc96SEvan Quan #include "vega20_baco.h"
50e098bc96SEvan Quan #include "smuio/smuio_9_0_offset.h"
51e098bc96SEvan Quan #include "smuio/smuio_9_0_sh_mask.h"
52e098bc96SEvan Quan #include "nbio/nbio_7_4_sh_mask.h"
53e098bc96SEvan Quan
54e098bc96SEvan Quan #define smnPCIE_LC_SPEED_CNTL 0x11140290
55e098bc96SEvan Quan #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
56e098bc96SEvan Quan
57e098bc96SEvan Quan #define LINK_WIDTH_MAX 6
58e098bc96SEvan Quan #define LINK_SPEED_MAX 3
59dd67d7a6SAlex Deucher static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
60dd67d7a6SAlex Deucher static const int link_speed[] = {25, 50, 80, 160};
61e098bc96SEvan Quan
vega20_set_default_registry_data(struct pp_hwmgr * hwmgr)62e098bc96SEvan Quan static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
63e098bc96SEvan Quan {
64e098bc96SEvan Quan struct vega20_hwmgr *data =
65e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
66e098bc96SEvan Quan
67e098bc96SEvan Quan data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
68e098bc96SEvan Quan data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
69e098bc96SEvan Quan data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
70e098bc96SEvan Quan data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
71e098bc96SEvan Quan data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
72e098bc96SEvan Quan
73e098bc96SEvan Quan data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
74e098bc96SEvan Quan data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75e098bc96SEvan Quan data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76e098bc96SEvan Quan data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77e098bc96SEvan Quan data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
78e098bc96SEvan Quan data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79e098bc96SEvan Quan data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
80e098bc96SEvan Quan data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
81e098bc96SEvan Quan data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
82e098bc96SEvan Quan data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
83e098bc96SEvan Quan data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
84e098bc96SEvan Quan data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
85e098bc96SEvan Quan data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
86e098bc96SEvan Quan
87e098bc96SEvan Quan /*
88e098bc96SEvan Quan * Disable the following features for now:
89e098bc96SEvan Quan * GFXCLK DS
90e098bc96SEvan Quan * SOCLK DS
91e098bc96SEvan Quan * LCLK DS
92e098bc96SEvan Quan * DCEFCLK DS
93e098bc96SEvan Quan * FCLK DS
94e098bc96SEvan Quan * MP1CLK DS
95e098bc96SEvan Quan * MP0CLK DS
96e098bc96SEvan Quan */
97e098bc96SEvan Quan data->registry_data.disallowed_features = 0xE0041C00;
98e098bc96SEvan Quan /* ECC feature should be disabled on old SMUs */
99e098bc96SEvan Quan smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version);
100e098bc96SEvan Quan if (hwmgr->smu_version < 0x282100)
101e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
102e098bc96SEvan Quan
103e098bc96SEvan Quan if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
104e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK;
105e098bc96SEvan Quan
106e098bc96SEvan Quan if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
107e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK;
108e098bc96SEvan Quan
109e098bc96SEvan Quan if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
110e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK;
111e098bc96SEvan Quan
112e098bc96SEvan Quan if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
113e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK;
114e098bc96SEvan Quan
115e098bc96SEvan Quan if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
116e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK;
117e098bc96SEvan Quan
118e098bc96SEvan Quan if (!(hwmgr->feature_mask & PP_ULV_MASK))
119e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_ULV_MASK;
120e098bc96SEvan Quan
121e098bc96SEvan Quan if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
122e098bc96SEvan Quan data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK;
123e098bc96SEvan Quan
124e098bc96SEvan Quan data->registry_data.od_state_in_dc_support = 0;
125e098bc96SEvan Quan data->registry_data.thermal_support = 1;
126e098bc96SEvan Quan data->registry_data.skip_baco_hardware = 0;
127e098bc96SEvan Quan
128e098bc96SEvan Quan data->registry_data.log_avfs_param = 0;
129e098bc96SEvan Quan data->registry_data.sclk_throttle_low_notification = 1;
130e098bc96SEvan Quan data->registry_data.force_dpm_high = 0;
131e098bc96SEvan Quan data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
132e098bc96SEvan Quan
133e098bc96SEvan Quan data->registry_data.didt_support = 0;
134e098bc96SEvan Quan if (data->registry_data.didt_support) {
135e098bc96SEvan Quan data->registry_data.didt_mode = 6;
136e098bc96SEvan Quan data->registry_data.sq_ramping_support = 1;
137e098bc96SEvan Quan data->registry_data.db_ramping_support = 0;
138e098bc96SEvan Quan data->registry_data.td_ramping_support = 0;
139e098bc96SEvan Quan data->registry_data.tcp_ramping_support = 0;
140e098bc96SEvan Quan data->registry_data.dbr_ramping_support = 0;
141e098bc96SEvan Quan data->registry_data.edc_didt_support = 1;
142e098bc96SEvan Quan data->registry_data.gc_didt_support = 0;
143e098bc96SEvan Quan data->registry_data.psm_didt_support = 0;
144e098bc96SEvan Quan }
145e098bc96SEvan Quan
146e098bc96SEvan Quan data->registry_data.pcie_lane_override = 0xff;
147e098bc96SEvan Quan data->registry_data.pcie_speed_override = 0xff;
148e098bc96SEvan Quan data->registry_data.pcie_clock_override = 0xffffffff;
149e098bc96SEvan Quan data->registry_data.regulator_hot_gpio_support = 1;
150e098bc96SEvan Quan data->registry_data.ac_dc_switch_gpio_support = 0;
151e098bc96SEvan Quan data->registry_data.quick_transition_support = 0;
152e098bc96SEvan Quan data->registry_data.zrpm_start_temp = 0xffff;
153e098bc96SEvan Quan data->registry_data.zrpm_stop_temp = 0xffff;
154e098bc96SEvan Quan data->registry_data.od8_feature_enable = 1;
155e098bc96SEvan Quan data->registry_data.disable_water_mark = 0;
156e098bc96SEvan Quan data->registry_data.disable_pp_tuning = 0;
157e098bc96SEvan Quan data->registry_data.disable_xlpp_tuning = 0;
158e098bc96SEvan Quan data->registry_data.disable_workload_policy = 0;
159e098bc96SEvan Quan data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
160e098bc96SEvan Quan data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
161e098bc96SEvan Quan data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
162e098bc96SEvan Quan data->registry_data.force_workload_policy_mask = 0;
163e098bc96SEvan Quan data->registry_data.disable_3d_fs_detection = 0;
164e098bc96SEvan Quan data->registry_data.fps_support = 1;
165e098bc96SEvan Quan data->registry_data.disable_auto_wattman = 1;
166e098bc96SEvan Quan data->registry_data.auto_wattman_debug = 0;
167e098bc96SEvan Quan data->registry_data.auto_wattman_sample_period = 100;
168e098bc96SEvan Quan data->registry_data.fclk_gfxclk_ratio = 0;
169e098bc96SEvan Quan data->registry_data.auto_wattman_threshold = 50;
170e098bc96SEvan Quan data->registry_data.gfxoff_controlled_by_driver = 1;
171e098bc96SEvan Quan data->gfxoff_allowed = false;
172e098bc96SEvan Quan data->counter_gfxoff = 0;
1731a31474cSKenneth Feng data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
174e098bc96SEvan Quan }
175e098bc96SEvan Quan
vega20_set_features_platform_caps(struct pp_hwmgr * hwmgr)176e098bc96SEvan Quan static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
177e098bc96SEvan Quan {
178e098bc96SEvan Quan struct vega20_hwmgr *data =
179e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
180e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
181e098bc96SEvan Quan
182e098bc96SEvan Quan if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
183e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
184e098bc96SEvan Quan PHM_PlatformCaps_ControlVDDCI);
185e098bc96SEvan Quan
186e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
187e098bc96SEvan Quan PHM_PlatformCaps_TablelessHardwareInterface);
188e098bc96SEvan Quan
189e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
190e098bc96SEvan Quan PHM_PlatformCaps_BACO);
191e098bc96SEvan Quan
192e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193e098bc96SEvan Quan PHM_PlatformCaps_EnableSMU7ThermalManagement);
194e098bc96SEvan Quan
195e098bc96SEvan Quan if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
196e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
197e098bc96SEvan Quan PHM_PlatformCaps_UVDPowerGating);
198e098bc96SEvan Quan
199e098bc96SEvan Quan if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
200e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
201e098bc96SEvan Quan PHM_PlatformCaps_VCEPowerGating);
202e098bc96SEvan Quan
203e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204e098bc96SEvan Quan PHM_PlatformCaps_UnTabledHardwareInterface);
205e098bc96SEvan Quan
206e098bc96SEvan Quan if (data->registry_data.od8_feature_enable)
207e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
208e098bc96SEvan Quan PHM_PlatformCaps_OD8inACSupport);
209e098bc96SEvan Quan
210e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
211e098bc96SEvan Quan PHM_PlatformCaps_ActivityReporting);
212e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
213e098bc96SEvan Quan PHM_PlatformCaps_FanSpeedInTableIsRPM);
214e098bc96SEvan Quan
215e098bc96SEvan Quan if (data->registry_data.od_state_in_dc_support) {
216e098bc96SEvan Quan if (data->registry_data.od8_feature_enable)
217e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
218e098bc96SEvan Quan PHM_PlatformCaps_OD8inDCSupport);
219e098bc96SEvan Quan }
220e098bc96SEvan Quan
221e098bc96SEvan Quan if (data->registry_data.thermal_support &&
222e098bc96SEvan Quan data->registry_data.fuzzy_fan_control_support &&
223e098bc96SEvan Quan hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
224e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
225e098bc96SEvan Quan PHM_PlatformCaps_ODFuzzyFanControlSupport);
226e098bc96SEvan Quan
227e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
228e098bc96SEvan Quan PHM_PlatformCaps_DynamicPowerManagement);
229e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
230e098bc96SEvan Quan PHM_PlatformCaps_SMC);
231e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
232e098bc96SEvan Quan PHM_PlatformCaps_ThermalPolicyDelay);
233e098bc96SEvan Quan
234e098bc96SEvan Quan if (data->registry_data.force_dpm_high)
235e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
236e098bc96SEvan Quan PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
237e098bc96SEvan Quan
238e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
239e098bc96SEvan Quan PHM_PlatformCaps_DynamicUVDState);
240e098bc96SEvan Quan
241e098bc96SEvan Quan if (data->registry_data.sclk_throttle_low_notification)
242e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
243e098bc96SEvan Quan PHM_PlatformCaps_SclkThrottleLowNotification);
244e098bc96SEvan Quan
245e098bc96SEvan Quan /* power tune caps */
246e098bc96SEvan Quan /* assume disabled */
247e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
248e098bc96SEvan Quan PHM_PlatformCaps_PowerContainment);
249e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
250e098bc96SEvan Quan PHM_PlatformCaps_DiDtSupport);
251e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
252e098bc96SEvan Quan PHM_PlatformCaps_SQRamping);
253e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
254e098bc96SEvan Quan PHM_PlatformCaps_DBRamping);
255e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
256e098bc96SEvan Quan PHM_PlatformCaps_TDRamping);
257e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
258e098bc96SEvan Quan PHM_PlatformCaps_TCPRamping);
259e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
260e098bc96SEvan Quan PHM_PlatformCaps_DBRRamping);
261e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
262e098bc96SEvan Quan PHM_PlatformCaps_DiDtEDCEnable);
263e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
264e098bc96SEvan Quan PHM_PlatformCaps_GCEDC);
265e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
266e098bc96SEvan Quan PHM_PlatformCaps_PSM);
267e098bc96SEvan Quan
268e098bc96SEvan Quan if (data->registry_data.didt_support) {
269e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
270e098bc96SEvan Quan PHM_PlatformCaps_DiDtSupport);
271e098bc96SEvan Quan if (data->registry_data.sq_ramping_support)
272e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
273e098bc96SEvan Quan PHM_PlatformCaps_SQRamping);
274e098bc96SEvan Quan if (data->registry_data.db_ramping_support)
275e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
276e098bc96SEvan Quan PHM_PlatformCaps_DBRamping);
277e098bc96SEvan Quan if (data->registry_data.td_ramping_support)
278e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
279e098bc96SEvan Quan PHM_PlatformCaps_TDRamping);
280e098bc96SEvan Quan if (data->registry_data.tcp_ramping_support)
281e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
282e098bc96SEvan Quan PHM_PlatformCaps_TCPRamping);
283e098bc96SEvan Quan if (data->registry_data.dbr_ramping_support)
284e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
285e098bc96SEvan Quan PHM_PlatformCaps_DBRRamping);
286e098bc96SEvan Quan if (data->registry_data.edc_didt_support)
287e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
288e098bc96SEvan Quan PHM_PlatformCaps_DiDtEDCEnable);
289e098bc96SEvan Quan if (data->registry_data.gc_didt_support)
290e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291e098bc96SEvan Quan PHM_PlatformCaps_GCEDC);
292e098bc96SEvan Quan if (data->registry_data.psm_didt_support)
293e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
294e098bc96SEvan Quan PHM_PlatformCaps_PSM);
295e098bc96SEvan Quan }
296e098bc96SEvan Quan
297e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
298e098bc96SEvan Quan PHM_PlatformCaps_RegulatorHot);
299e098bc96SEvan Quan
300e098bc96SEvan Quan if (data->registry_data.ac_dc_switch_gpio_support) {
301e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
302e098bc96SEvan Quan PHM_PlatformCaps_AutomaticDCTransition);
303e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
304e098bc96SEvan Quan PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
305e098bc96SEvan Quan }
306e098bc96SEvan Quan
307e098bc96SEvan Quan if (data->registry_data.quick_transition_support) {
308e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
309e098bc96SEvan Quan PHM_PlatformCaps_AutomaticDCTransition);
310e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
311e098bc96SEvan Quan PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
312e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
313e098bc96SEvan Quan PHM_PlatformCaps_Falcon_QuickTransition);
314e098bc96SEvan Quan }
315e098bc96SEvan Quan
316e098bc96SEvan Quan if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
317e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
318e098bc96SEvan Quan PHM_PlatformCaps_LowestUclkReservedForUlv);
319e098bc96SEvan Quan if (data->lowest_uclk_reserved_for_ulv == 1)
320e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
321e098bc96SEvan Quan PHM_PlatformCaps_LowestUclkReservedForUlv);
322e098bc96SEvan Quan }
323e098bc96SEvan Quan
324e098bc96SEvan Quan if (data->registry_data.custom_fan_support)
325e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
326e098bc96SEvan Quan PHM_PlatformCaps_CustomFanControlSupport);
327e098bc96SEvan Quan
328e098bc96SEvan Quan return 0;
329e098bc96SEvan Quan }
330e098bc96SEvan Quan
vega20_init_dpm_defaults(struct pp_hwmgr * hwmgr)331336c8f55SMa Jun static int vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
332e098bc96SEvan Quan {
333e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
334e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
335e098bc96SEvan Quan uint32_t top32, bottom32;
336336c8f55SMa Jun int i, ret;
337e098bc96SEvan Quan
338e098bc96SEvan Quan data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
339e098bc96SEvan Quan FEATURE_DPM_PREFETCHER_BIT;
340e098bc96SEvan Quan data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
341e098bc96SEvan Quan FEATURE_DPM_GFXCLK_BIT;
342e098bc96SEvan Quan data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
343e098bc96SEvan Quan FEATURE_DPM_UCLK_BIT;
344e098bc96SEvan Quan data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
345e098bc96SEvan Quan FEATURE_DPM_SOCCLK_BIT;
346e098bc96SEvan Quan data->smu_features[GNLD_DPM_UVD].smu_feature_id =
347e098bc96SEvan Quan FEATURE_DPM_UVD_BIT;
348e098bc96SEvan Quan data->smu_features[GNLD_DPM_VCE].smu_feature_id =
349e098bc96SEvan Quan FEATURE_DPM_VCE_BIT;
350e098bc96SEvan Quan data->smu_features[GNLD_ULV].smu_feature_id =
351e098bc96SEvan Quan FEATURE_ULV_BIT;
352e098bc96SEvan Quan data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
353e098bc96SEvan Quan FEATURE_DPM_MP0CLK_BIT;
354e098bc96SEvan Quan data->smu_features[GNLD_DPM_LINK].smu_feature_id =
355e098bc96SEvan Quan FEATURE_DPM_LINK_BIT;
356e098bc96SEvan Quan data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
357e098bc96SEvan Quan FEATURE_DPM_DCEFCLK_BIT;
358e098bc96SEvan Quan data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
359e098bc96SEvan Quan FEATURE_DS_GFXCLK_BIT;
360e098bc96SEvan Quan data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
361e098bc96SEvan Quan FEATURE_DS_SOCCLK_BIT;
362e098bc96SEvan Quan data->smu_features[GNLD_DS_LCLK].smu_feature_id =
363e098bc96SEvan Quan FEATURE_DS_LCLK_BIT;
364e098bc96SEvan Quan data->smu_features[GNLD_PPT].smu_feature_id =
365e098bc96SEvan Quan FEATURE_PPT_BIT;
366e098bc96SEvan Quan data->smu_features[GNLD_TDC].smu_feature_id =
367e098bc96SEvan Quan FEATURE_TDC_BIT;
368e098bc96SEvan Quan data->smu_features[GNLD_THERMAL].smu_feature_id =
369e098bc96SEvan Quan FEATURE_THERMAL_BIT;
370e098bc96SEvan Quan data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
371e098bc96SEvan Quan FEATURE_GFX_PER_CU_CG_BIT;
372e098bc96SEvan Quan data->smu_features[GNLD_RM].smu_feature_id =
373e098bc96SEvan Quan FEATURE_RM_BIT;
374e098bc96SEvan Quan data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
375e098bc96SEvan Quan FEATURE_DS_DCEFCLK_BIT;
376e098bc96SEvan Quan data->smu_features[GNLD_ACDC].smu_feature_id =
377e098bc96SEvan Quan FEATURE_ACDC_BIT;
378e098bc96SEvan Quan data->smu_features[GNLD_VR0HOT].smu_feature_id =
379e098bc96SEvan Quan FEATURE_VR0HOT_BIT;
380e098bc96SEvan Quan data->smu_features[GNLD_VR1HOT].smu_feature_id =
381e098bc96SEvan Quan FEATURE_VR1HOT_BIT;
382e098bc96SEvan Quan data->smu_features[GNLD_FW_CTF].smu_feature_id =
383e098bc96SEvan Quan FEATURE_FW_CTF_BIT;
384e098bc96SEvan Quan data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
385e098bc96SEvan Quan FEATURE_LED_DISPLAY_BIT;
386e098bc96SEvan Quan data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
387e098bc96SEvan Quan FEATURE_FAN_CONTROL_BIT;
388e098bc96SEvan Quan data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
389e098bc96SEvan Quan data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
390e098bc96SEvan Quan data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
391e098bc96SEvan Quan data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
392e098bc96SEvan Quan data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
393e098bc96SEvan Quan data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
394e098bc96SEvan Quan data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
395e098bc96SEvan Quan data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
396e098bc96SEvan Quan data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
397e098bc96SEvan Quan
398e098bc96SEvan Quan for (i = 0; i < GNLD_FEATURES_MAX; i++) {
399e098bc96SEvan Quan data->smu_features[i].smu_feature_bitmap =
400e098bc96SEvan Quan (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
401e098bc96SEvan Quan data->smu_features[i].allowed =
402e098bc96SEvan Quan ((data->registry_data.disallowed_features >> i) & 1) ?
403e098bc96SEvan Quan false : true;
404e098bc96SEvan Quan }
405e098bc96SEvan Quan
406e098bc96SEvan Quan /* Get the SN to turn into a Unique ID */
407336c8f55SMa Jun ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
408336c8f55SMa Jun if (ret)
409336c8f55SMa Jun return ret;
410336c8f55SMa Jun
411336c8f55SMa Jun ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
412336c8f55SMa Jun if (ret)
413336c8f55SMa Jun return ret;
414e098bc96SEvan Quan
415e098bc96SEvan Quan adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
416336c8f55SMa Jun
417336c8f55SMa Jun return 0;
418e098bc96SEvan Quan }
419e098bc96SEvan Quan
vega20_set_private_data_based_on_pptable(struct pp_hwmgr * hwmgr)420e098bc96SEvan Quan static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
421e098bc96SEvan Quan {
422e098bc96SEvan Quan return 0;
423e098bc96SEvan Quan }
424e098bc96SEvan Quan
vega20_hwmgr_backend_fini(struct pp_hwmgr * hwmgr)425e098bc96SEvan Quan static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
426e098bc96SEvan Quan {
427e098bc96SEvan Quan kfree(hwmgr->backend);
428e098bc96SEvan Quan hwmgr->backend = NULL;
429e098bc96SEvan Quan
430e098bc96SEvan Quan return 0;
431e098bc96SEvan Quan }
432e098bc96SEvan Quan
vega20_hwmgr_backend_init(struct pp_hwmgr * hwmgr)433e098bc96SEvan Quan static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
434e098bc96SEvan Quan {
435e098bc96SEvan Quan struct vega20_hwmgr *data;
436e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
437336c8f55SMa Jun int result;
438e098bc96SEvan Quan
439e098bc96SEvan Quan data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
440e098bc96SEvan Quan if (data == NULL)
441e098bc96SEvan Quan return -ENOMEM;
442e098bc96SEvan Quan
443e098bc96SEvan Quan hwmgr->backend = data;
444e098bc96SEvan Quan
445e098bc96SEvan Quan hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
446e098bc96SEvan Quan hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
447e098bc96SEvan Quan hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
448e098bc96SEvan Quan
449e098bc96SEvan Quan vega20_set_default_registry_data(hwmgr);
450e098bc96SEvan Quan
451e098bc96SEvan Quan data->disable_dpm_mask = 0xff;
452e098bc96SEvan Quan
453e098bc96SEvan Quan /* need to set voltage control types before EVV patching */
454e098bc96SEvan Quan data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
455e098bc96SEvan Quan data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
456e098bc96SEvan Quan data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
457e098bc96SEvan Quan
458e098bc96SEvan Quan data->water_marks_bitmap = 0;
459e098bc96SEvan Quan data->avfs_exist = false;
460e098bc96SEvan Quan
461e098bc96SEvan Quan vega20_set_features_platform_caps(hwmgr);
462e098bc96SEvan Quan
463336c8f55SMa Jun result = vega20_init_dpm_defaults(hwmgr);
464336c8f55SMa Jun if (result) {
465336c8f55SMa Jun pr_err("%s failed\n", __func__);
466336c8f55SMa Jun return result;
467336c8f55SMa Jun }
468e098bc96SEvan Quan /* Parse pptable data read from VBIOS */
469e098bc96SEvan Quan vega20_set_private_data_based_on_pptable(hwmgr);
470e098bc96SEvan Quan
471e098bc96SEvan Quan data->is_tlu_enabled = false;
472e098bc96SEvan Quan
473e098bc96SEvan Quan hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
474e098bc96SEvan Quan VEGA20_MAX_HARDWARE_POWERLEVELS;
475e098bc96SEvan Quan hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
476e098bc96SEvan Quan hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
477e098bc96SEvan Quan
478e098bc96SEvan Quan hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
479e098bc96SEvan Quan /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
480e098bc96SEvan Quan hwmgr->platform_descriptor.clockStep.engineClock = 500;
481e098bc96SEvan Quan hwmgr->platform_descriptor.clockStep.memoryClock = 500;
482e098bc96SEvan Quan
483e098bc96SEvan Quan data->total_active_cus = adev->gfx.cu_info.number;
484e098bc96SEvan Quan data->is_custom_profile_set = false;
485e098bc96SEvan Quan
486e098bc96SEvan Quan return 0;
487e098bc96SEvan Quan }
488e098bc96SEvan Quan
vega20_init_sclk_threshold(struct pp_hwmgr * hwmgr)489e098bc96SEvan Quan static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
490e098bc96SEvan Quan {
491e098bc96SEvan Quan struct vega20_hwmgr *data =
492e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
493e098bc96SEvan Quan
494e098bc96SEvan Quan data->low_sclk_interrupt_threshold = 0;
495e098bc96SEvan Quan
496e098bc96SEvan Quan return 0;
497e098bc96SEvan Quan }
498e098bc96SEvan Quan
vega20_setup_asic_task(struct pp_hwmgr * hwmgr)499e098bc96SEvan Quan static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
500e098bc96SEvan Quan {
501e098bc96SEvan Quan struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
502e098bc96SEvan Quan int ret = 0;
50353b3f8f4SDennis Li bool use_baco = (amdgpu_in_reset(adev) &&
504e098bc96SEvan Quan (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
505e098bc96SEvan Quan (adev->in_runpm && amdgpu_asic_supports_baco(adev));
506e098bc96SEvan Quan
507e098bc96SEvan Quan ret = vega20_init_sclk_threshold(hwmgr);
508e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
509e098bc96SEvan Quan "Failed to init sclk threshold!",
510e098bc96SEvan Quan return ret);
511e098bc96SEvan Quan
512e098bc96SEvan Quan if (use_baco) {
513e098bc96SEvan Quan ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
514e098bc96SEvan Quan if (ret)
515e098bc96SEvan Quan pr_err("Failed to apply vega20 baco workaround!\n");
516e098bc96SEvan Quan }
517e098bc96SEvan Quan
518e098bc96SEvan Quan return ret;
519e098bc96SEvan Quan }
520e098bc96SEvan Quan
521e098bc96SEvan Quan /*
522e098bc96SEvan Quan * @fn vega20_init_dpm_state
523e098bc96SEvan Quan * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
524e098bc96SEvan Quan *
525e098bc96SEvan Quan * @param dpm_state - the address of the DPM Table to initiailize.
526e098bc96SEvan Quan * @return None.
527e098bc96SEvan Quan */
vega20_init_dpm_state(struct vega20_dpm_state * dpm_state)528e098bc96SEvan Quan static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
529e098bc96SEvan Quan {
530e098bc96SEvan Quan dpm_state->soft_min_level = 0x0;
531e098bc96SEvan Quan dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT;
532e098bc96SEvan Quan dpm_state->hard_min_level = 0x0;
533e098bc96SEvan Quan dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT;
534e098bc96SEvan Quan }
535e098bc96SEvan Quan
vega20_get_number_of_dpm_level(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t * num_of_levels)536e098bc96SEvan Quan static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
537e098bc96SEvan Quan PPCLK_e clk_id, uint32_t *num_of_levels)
538e098bc96SEvan Quan {
539e098bc96SEvan Quan int ret = 0;
540e098bc96SEvan Quan
541e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
542e098bc96SEvan Quan PPSMC_MSG_GetDpmFreqByIndex,
543e098bc96SEvan Quan (clk_id << 16 | 0xFF),
544e098bc96SEvan Quan num_of_levels);
545e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
546e098bc96SEvan Quan "[GetNumOfDpmLevel] failed to get dpm levels!",
547e098bc96SEvan Quan return ret);
548e098bc96SEvan Quan
549e098bc96SEvan Quan return ret;
550e098bc96SEvan Quan }
551e098bc96SEvan Quan
vega20_get_dpm_frequency_by_index(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t index,uint32_t * clk)552e098bc96SEvan Quan static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
553e098bc96SEvan Quan PPCLK_e clk_id, uint32_t index, uint32_t *clk)
554e098bc96SEvan Quan {
555e098bc96SEvan Quan int ret = 0;
556e098bc96SEvan Quan
557e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
558e098bc96SEvan Quan PPSMC_MSG_GetDpmFreqByIndex,
559e098bc96SEvan Quan (clk_id << 16 | index),
560e098bc96SEvan Quan clk);
561e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
562e098bc96SEvan Quan "[GetDpmFreqByIndex] failed to get dpm freq by index!",
563e098bc96SEvan Quan return ret);
564e098bc96SEvan Quan
565e098bc96SEvan Quan return ret;
566e098bc96SEvan Quan }
567e098bc96SEvan Quan
vega20_setup_single_dpm_table(struct pp_hwmgr * hwmgr,struct vega20_single_dpm_table * dpm_table,PPCLK_e clk_id)568e098bc96SEvan Quan static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
569e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
570e098bc96SEvan Quan {
571e098bc96SEvan Quan int ret = 0;
572e098bc96SEvan Quan uint32_t i, num_of_levels, clk;
573e098bc96SEvan Quan
574e098bc96SEvan Quan ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
575e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
576e098bc96SEvan Quan "[SetupSingleDpmTable] failed to get clk levels!",
577e098bc96SEvan Quan return ret);
578e098bc96SEvan Quan
579e098bc96SEvan Quan dpm_table->count = num_of_levels;
580e098bc96SEvan Quan
581e098bc96SEvan Quan for (i = 0; i < num_of_levels; i++) {
582e098bc96SEvan Quan ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
583e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
584e098bc96SEvan Quan "[SetupSingleDpmTable] failed to get clk of specific level!",
585e098bc96SEvan Quan return ret);
586e098bc96SEvan Quan dpm_table->dpm_levels[i].value = clk;
587e098bc96SEvan Quan dpm_table->dpm_levels[i].enabled = true;
588e098bc96SEvan Quan }
589e098bc96SEvan Quan
590e098bc96SEvan Quan return ret;
591e098bc96SEvan Quan }
592e098bc96SEvan Quan
vega20_setup_gfxclk_dpm_table(struct pp_hwmgr * hwmgr)593e098bc96SEvan Quan static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
594e098bc96SEvan Quan {
595e098bc96SEvan Quan struct vega20_hwmgr *data =
596e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
597e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table;
598e098bc96SEvan Quan int ret = 0;
599e098bc96SEvan Quan
600e098bc96SEvan Quan dpm_table = &(data->dpm_table.gfx_table);
601e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
602e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
603e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
604e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
605e098bc96SEvan Quan return ret);
606e098bc96SEvan Quan } else {
607e098bc96SEvan Quan dpm_table->count = 1;
608e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
609e098bc96SEvan Quan }
610e098bc96SEvan Quan
611e098bc96SEvan Quan return ret;
612e098bc96SEvan Quan }
613e098bc96SEvan Quan
vega20_setup_memclk_dpm_table(struct pp_hwmgr * hwmgr)614e098bc96SEvan Quan static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
615e098bc96SEvan Quan {
616e098bc96SEvan Quan struct vega20_hwmgr *data =
617e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
618e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table;
619e098bc96SEvan Quan int ret = 0;
620e098bc96SEvan Quan
621e098bc96SEvan Quan dpm_table = &(data->dpm_table.mem_table);
622e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled) {
623e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
624e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
625e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
626e098bc96SEvan Quan return ret);
627e098bc96SEvan Quan } else {
628e098bc96SEvan Quan dpm_table->count = 1;
629e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
630e098bc96SEvan Quan }
631e098bc96SEvan Quan
632e098bc96SEvan Quan return ret;
633e098bc96SEvan Quan }
634e098bc96SEvan Quan
635e098bc96SEvan Quan /*
636e098bc96SEvan Quan * This function is to initialize all DPM state tables
637e098bc96SEvan Quan * for SMU based on the dependency table.
638e098bc96SEvan Quan * Dynamic state patching function will then trim these
639e098bc96SEvan Quan * state tables to the allowed range based
640e098bc96SEvan Quan * on the power policy or external client requests,
641e098bc96SEvan Quan * such as UVD request, etc.
642e098bc96SEvan Quan */
vega20_setup_default_dpm_tables(struct pp_hwmgr * hwmgr)643e098bc96SEvan Quan static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
644e098bc96SEvan Quan {
645e098bc96SEvan Quan struct vega20_hwmgr *data =
646e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
647e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table;
648e098bc96SEvan Quan int ret = 0;
649e098bc96SEvan Quan
650e098bc96SEvan Quan memset(&data->dpm_table, 0, sizeof(data->dpm_table));
651e098bc96SEvan Quan
652e098bc96SEvan Quan /* socclk */
653e098bc96SEvan Quan dpm_table = &(data->dpm_table.soc_table);
654e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
655e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
656e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
657e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
658e098bc96SEvan Quan return ret);
659e098bc96SEvan Quan } else {
660e098bc96SEvan Quan dpm_table->count = 1;
661e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
662e098bc96SEvan Quan }
663e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
664e098bc96SEvan Quan
665e098bc96SEvan Quan /* gfxclk */
666e098bc96SEvan Quan dpm_table = &(data->dpm_table.gfx_table);
667e098bc96SEvan Quan ret = vega20_setup_gfxclk_dpm_table(hwmgr);
668e098bc96SEvan Quan if (ret)
669e098bc96SEvan Quan return ret;
670e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
671e098bc96SEvan Quan
672e098bc96SEvan Quan /* memclk */
673e098bc96SEvan Quan dpm_table = &(data->dpm_table.mem_table);
674e098bc96SEvan Quan ret = vega20_setup_memclk_dpm_table(hwmgr);
675e098bc96SEvan Quan if (ret)
676e098bc96SEvan Quan return ret;
677e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
678e098bc96SEvan Quan
679e098bc96SEvan Quan /* eclk */
680e098bc96SEvan Quan dpm_table = &(data->dpm_table.eclk_table);
681e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_VCE].enabled) {
682e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
683e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
684e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
685e098bc96SEvan Quan return ret);
686e098bc96SEvan Quan } else {
687e098bc96SEvan Quan dpm_table->count = 1;
688e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
689e098bc96SEvan Quan }
690e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
691e098bc96SEvan Quan
692e098bc96SEvan Quan /* vclk */
693e098bc96SEvan Quan dpm_table = &(data->dpm_table.vclk_table);
694e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UVD].enabled) {
695e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
696e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
697e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
698e098bc96SEvan Quan return ret);
699e098bc96SEvan Quan } else {
700e098bc96SEvan Quan dpm_table->count = 1;
701e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
702e098bc96SEvan Quan }
703e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
704e098bc96SEvan Quan
705e098bc96SEvan Quan /* dclk */
706e098bc96SEvan Quan dpm_table = &(data->dpm_table.dclk_table);
707e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UVD].enabled) {
708e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
709e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
710e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
711e098bc96SEvan Quan return ret);
712e098bc96SEvan Quan } else {
713e098bc96SEvan Quan dpm_table->count = 1;
714e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
715e098bc96SEvan Quan }
716e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
717e098bc96SEvan Quan
718e098bc96SEvan Quan /* dcefclk */
719e098bc96SEvan Quan dpm_table = &(data->dpm_table.dcef_table);
720e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
721e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
722e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
723e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
724e098bc96SEvan Quan return ret);
725e098bc96SEvan Quan } else {
726e098bc96SEvan Quan dpm_table->count = 1;
727e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
728e098bc96SEvan Quan }
729e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
730e098bc96SEvan Quan
731e098bc96SEvan Quan /* pixclk */
732e098bc96SEvan Quan dpm_table = &(data->dpm_table.pixel_table);
733e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
734e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
735e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
736e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
737e098bc96SEvan Quan return ret);
738e098bc96SEvan Quan } else
739e098bc96SEvan Quan dpm_table->count = 0;
740e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
741e098bc96SEvan Quan
742e098bc96SEvan Quan /* dispclk */
743e098bc96SEvan Quan dpm_table = &(data->dpm_table.display_table);
744e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
745e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
746e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
747e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
748e098bc96SEvan Quan return ret);
749e098bc96SEvan Quan } else
750e098bc96SEvan Quan dpm_table->count = 0;
751e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
752e098bc96SEvan Quan
753e098bc96SEvan Quan /* phyclk */
754e098bc96SEvan Quan dpm_table = &(data->dpm_table.phy_table);
755e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
756e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
757e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
758e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
759e098bc96SEvan Quan return ret);
760e098bc96SEvan Quan } else
761e098bc96SEvan Quan dpm_table->count = 0;
762e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
763e098bc96SEvan Quan
764e098bc96SEvan Quan /* fclk */
765e098bc96SEvan Quan dpm_table = &(data->dpm_table.fclk_table);
766e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_FCLK].enabled) {
767e098bc96SEvan Quan ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
768e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
769e098bc96SEvan Quan "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
770e098bc96SEvan Quan return ret);
771e098bc96SEvan Quan } else {
772e098bc96SEvan Quan dpm_table->count = 1;
773e098bc96SEvan Quan dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100;
774e098bc96SEvan Quan }
775e098bc96SEvan Quan vega20_init_dpm_state(&(dpm_table->dpm_state));
776e098bc96SEvan Quan
777e098bc96SEvan Quan /* save a copy of the default DPM table */
778e098bc96SEvan Quan memcpy(&(data->golden_dpm_table), &(data->dpm_table),
779e098bc96SEvan Quan sizeof(struct vega20_dpm_table));
780e098bc96SEvan Quan
781e098bc96SEvan Quan return 0;
782e098bc96SEvan Quan }
783e098bc96SEvan Quan
784e098bc96SEvan Quan /**
785c00e89efSLee Jones * vega20_init_smc_table - Initializes the SMC table and uploads it
786e098bc96SEvan Quan *
7879e0a4153SLee Jones * @hwmgr: the address of the powerplay hardware manager.
7889e0a4153SLee Jones * return: always 0
789e098bc96SEvan Quan */
vega20_init_smc_table(struct pp_hwmgr * hwmgr)790e098bc96SEvan Quan static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
791e098bc96SEvan Quan {
792e098bc96SEvan Quan int result;
793e098bc96SEvan Quan struct vega20_hwmgr *data =
794e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
795e098bc96SEvan Quan PPTable_t *pp_table = &(data->smc_state_table.pp_table);
796e098bc96SEvan Quan struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
797e098bc96SEvan Quan struct phm_ppt_v3_information *pptable_information =
798e098bc96SEvan Quan (struct phm_ppt_v3_information *)hwmgr->pptable;
799e098bc96SEvan Quan
800e098bc96SEvan Quan result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
801e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
802e098bc96SEvan Quan "[InitSMCTable] Failed to get vbios bootup values!",
803e098bc96SEvan Quan return result);
804e098bc96SEvan Quan
805e098bc96SEvan Quan data->vbios_boot_state.vddc = boot_up_values.usVddc;
806e098bc96SEvan Quan data->vbios_boot_state.vddci = boot_up_values.usVddci;
807e098bc96SEvan Quan data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
808e098bc96SEvan Quan data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
809e098bc96SEvan Quan data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
810e098bc96SEvan Quan data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
811e098bc96SEvan Quan data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
812e098bc96SEvan Quan data->vbios_boot_state.eclock = boot_up_values.ulEClk;
813e098bc96SEvan Quan data->vbios_boot_state.vclock = boot_up_values.ulVClk;
814e098bc96SEvan Quan data->vbios_boot_state.dclock = boot_up_values.ulDClk;
815e098bc96SEvan Quan data->vbios_boot_state.fclock = boot_up_values.ulFClk;
816e098bc96SEvan Quan data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
817e098bc96SEvan Quan
818e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
819e098bc96SEvan Quan PPSMC_MSG_SetMinDeepSleepDcefclk,
820e098bc96SEvan Quan (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
821e098bc96SEvan Quan NULL);
822e098bc96SEvan Quan
823e098bc96SEvan Quan memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
824e098bc96SEvan Quan
825e098bc96SEvan Quan result = smum_smc_table_manager(hwmgr,
826e098bc96SEvan Quan (uint8_t *)pp_table, TABLE_PPTABLE, false);
827e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
828e098bc96SEvan Quan "[InitSMCTable] Failed to upload PPtable!",
829e098bc96SEvan Quan return result);
830e098bc96SEvan Quan
831e098bc96SEvan Quan return 0;
832e098bc96SEvan Quan }
833e098bc96SEvan Quan
834e098bc96SEvan Quan /*
835e098bc96SEvan Quan * Override PCIe link speed and link width for DPM Level 1. PPTable entries
836e098bc96SEvan Quan * reflect the ASIC capabilities and not the system capabilities. For e.g.
837e098bc96SEvan Quan * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
838e098bc96SEvan Quan * to DPM1, it fails as system doesn't support Gen4.
839e098bc96SEvan Quan */
vega20_override_pcie_parameters(struct pp_hwmgr * hwmgr)840e098bc96SEvan Quan static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
841e098bc96SEvan Quan {
842e098bc96SEvan Quan struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
843e098bc96SEvan Quan struct vega20_hwmgr *data =
844e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
845be6523e3SKenneth Feng uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;
846be6523e3SKenneth Feng PPTable_t *pp_table = &(data->smc_state_table.pp_table);
847be6523e3SKenneth Feng int i;
848e098bc96SEvan Quan int ret;
849e098bc96SEvan Quan
850e098bc96SEvan Quan if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
851e098bc96SEvan Quan pcie_gen = 3;
852e098bc96SEvan Quan else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
853e098bc96SEvan Quan pcie_gen = 2;
854e098bc96SEvan Quan else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
855e098bc96SEvan Quan pcie_gen = 1;
856e098bc96SEvan Quan else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
857e098bc96SEvan Quan pcie_gen = 0;
858e098bc96SEvan Quan
859e098bc96SEvan Quan if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
860e098bc96SEvan Quan pcie_width = 6;
861e098bc96SEvan Quan else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
862e098bc96SEvan Quan pcie_width = 5;
863e098bc96SEvan Quan else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
864e098bc96SEvan Quan pcie_width = 4;
865e098bc96SEvan Quan else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
866e098bc96SEvan Quan pcie_width = 3;
867e098bc96SEvan Quan else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
868e098bc96SEvan Quan pcie_width = 2;
869e098bc96SEvan Quan else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
870e098bc96SEvan Quan pcie_width = 1;
871e098bc96SEvan Quan
872e098bc96SEvan Quan /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
873e098bc96SEvan Quan * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
874e098bc96SEvan Quan * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
875e098bc96SEvan Quan */
876be6523e3SKenneth Feng for (i = 0; i < NUM_LINK_LEVELS; i++) {
877be6523e3SKenneth Feng pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen :
878be6523e3SKenneth Feng pp_table->PcieGenSpeed[i];
879be6523e3SKenneth Feng pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width :
880be6523e3SKenneth Feng pp_table->PcieLaneCount[i];
881be6523e3SKenneth Feng
882be6523e3SKenneth Feng if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg !=
883be6523e3SKenneth Feng pp_table->PcieLaneCount[i]) {
884be6523e3SKenneth Feng smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg;
885e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
886e098bc96SEvan Quan PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
887e098bc96SEvan Quan NULL);
888e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
889e098bc96SEvan Quan "[OverridePcieParameters] Attempt to override pcie params failed!",
890e098bc96SEvan Quan return ret);
891be6523e3SKenneth Feng }
892e098bc96SEvan Quan
893be6523e3SKenneth Feng /* update the pptable */
894be6523e3SKenneth Feng pp_table->PcieGenSpeed[i] = pcie_gen_arg;
895be6523e3SKenneth Feng pp_table->PcieLaneCount[i] = pcie_width_arg;
896be6523e3SKenneth Feng }
897e098bc96SEvan Quan
8981a31474cSKenneth Feng /* override to the highest if it's disabled from ppfeaturmask */
8991a31474cSKenneth Feng if (data->registry_data.pcie_dpm_key_disabled) {
9001a31474cSKenneth Feng for (i = 0; i < NUM_LINK_LEVELS; i++) {
9011a31474cSKenneth Feng smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;
9021a31474cSKenneth Feng ret = smum_send_msg_to_smc_with_parameter(hwmgr,
9031a31474cSKenneth Feng PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
9041a31474cSKenneth Feng NULL);
9051a31474cSKenneth Feng PP_ASSERT_WITH_CODE(!ret,
9061a31474cSKenneth Feng "[OverridePcieParameters] Attempt to override pcie params failed!",
9071a31474cSKenneth Feng return ret);
9081a31474cSKenneth Feng
9091a31474cSKenneth Feng pp_table->PcieGenSpeed[i] = pcie_gen;
9101a31474cSKenneth Feng pp_table->PcieLaneCount[i] = pcie_width;
9111a31474cSKenneth Feng }
9121a31474cSKenneth Feng ret = vega20_enable_smc_features(hwmgr,
9131a31474cSKenneth Feng false,
9141a31474cSKenneth Feng data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);
9151a31474cSKenneth Feng PP_ASSERT_WITH_CODE(!ret,
9161a31474cSKenneth Feng "Attempt to Disable DPM LINK Failed!",
9171a31474cSKenneth Feng return ret);
9181a31474cSKenneth Feng data->smu_features[GNLD_DPM_LINK].enabled = false;
9191a31474cSKenneth Feng data->smu_features[GNLD_DPM_LINK].supported = false;
9201a31474cSKenneth Feng }
9211a31474cSKenneth Feng
922e098bc96SEvan Quan return 0;
923e098bc96SEvan Quan }
924e098bc96SEvan Quan
vega20_set_allowed_featuresmask(struct pp_hwmgr * hwmgr)925e098bc96SEvan Quan static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
926e098bc96SEvan Quan {
927e098bc96SEvan Quan struct vega20_hwmgr *data =
928e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
929e098bc96SEvan Quan uint32_t allowed_features_low = 0, allowed_features_high = 0;
930e098bc96SEvan Quan int i;
931e098bc96SEvan Quan int ret = 0;
932e098bc96SEvan Quan
933e098bc96SEvan Quan for (i = 0; i < GNLD_FEATURES_MAX; i++)
934e098bc96SEvan Quan if (data->smu_features[i].allowed)
935e098bc96SEvan Quan data->smu_features[i].smu_feature_id > 31 ?
936e098bc96SEvan Quan (allowed_features_high |=
937e098bc96SEvan Quan ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
938e098bc96SEvan Quan & 0xFFFFFFFF)) :
939e098bc96SEvan Quan (allowed_features_low |=
940e098bc96SEvan Quan ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
941e098bc96SEvan Quan & 0xFFFFFFFF));
942e098bc96SEvan Quan
943e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
944e098bc96SEvan Quan PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, NULL);
945e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
946e098bc96SEvan Quan "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
947e098bc96SEvan Quan return ret);
948e098bc96SEvan Quan
949e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
950e098bc96SEvan Quan PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, NULL);
951e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
952e098bc96SEvan Quan "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
953e098bc96SEvan Quan return ret);
954e098bc96SEvan Quan
955e098bc96SEvan Quan return 0;
956e098bc96SEvan Quan }
957e098bc96SEvan Quan
vega20_run_btc(struct pp_hwmgr * hwmgr)958e098bc96SEvan Quan static int vega20_run_btc(struct pp_hwmgr *hwmgr)
959e098bc96SEvan Quan {
960e098bc96SEvan Quan return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc, NULL);
961e098bc96SEvan Quan }
962e098bc96SEvan Quan
vega20_run_btc_afll(struct pp_hwmgr * hwmgr)963e098bc96SEvan Quan static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
964e098bc96SEvan Quan {
965e098bc96SEvan Quan return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc, NULL);
966e098bc96SEvan Quan }
967e098bc96SEvan Quan
vega20_enable_all_smu_features(struct pp_hwmgr * hwmgr)968e098bc96SEvan Quan static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
969e098bc96SEvan Quan {
970e098bc96SEvan Quan struct vega20_hwmgr *data =
971e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
972e098bc96SEvan Quan uint64_t features_enabled;
973e098bc96SEvan Quan int i;
974e098bc96SEvan Quan bool enabled;
975e098bc96SEvan Quan int ret = 0;
976e098bc96SEvan Quan
977e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
978e098bc96SEvan Quan PPSMC_MSG_EnableAllSmuFeatures,
979e098bc96SEvan Quan NULL)) == 0,
980e098bc96SEvan Quan "[EnableAllSMUFeatures] Failed to enable all smu features!",
981e098bc96SEvan Quan return ret);
982e098bc96SEvan Quan
983e098bc96SEvan Quan ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
984e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
985e098bc96SEvan Quan "[EnableAllSmuFeatures] Failed to get enabled smc features!",
986e098bc96SEvan Quan return ret);
987e098bc96SEvan Quan
988e098bc96SEvan Quan for (i = 0; i < GNLD_FEATURES_MAX; i++) {
989e098bc96SEvan Quan enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
990e098bc96SEvan Quan true : false;
991e098bc96SEvan Quan data->smu_features[i].enabled = enabled;
992e098bc96SEvan Quan data->smu_features[i].supported = enabled;
993e098bc96SEvan Quan
994e098bc96SEvan Quan #if 0
995e098bc96SEvan Quan if (data->smu_features[i].allowed && !enabled)
996e098bc96SEvan Quan pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
997e098bc96SEvan Quan else if (!data->smu_features[i].allowed && enabled)
998e098bc96SEvan Quan pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
999e098bc96SEvan Quan #endif
1000e098bc96SEvan Quan }
1001e098bc96SEvan Quan
1002e098bc96SEvan Quan return 0;
1003e098bc96SEvan Quan }
1004e098bc96SEvan Quan
vega20_notify_smc_display_change(struct pp_hwmgr * hwmgr)1005e098bc96SEvan Quan static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
1006e098bc96SEvan Quan {
1007e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1008e098bc96SEvan Quan
1009e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled)
1010e098bc96SEvan Quan return smum_send_msg_to_smc_with_parameter(hwmgr,
1011e098bc96SEvan Quan PPSMC_MSG_SetUclkFastSwitch,
1012e098bc96SEvan Quan 1,
1013e098bc96SEvan Quan NULL);
1014e098bc96SEvan Quan
1015e098bc96SEvan Quan return 0;
1016e098bc96SEvan Quan }
1017e098bc96SEvan Quan
vega20_send_clock_ratio(struct pp_hwmgr * hwmgr)1018e098bc96SEvan Quan static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
1019e098bc96SEvan Quan {
1020e098bc96SEvan Quan struct vega20_hwmgr *data =
1021e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
1022e098bc96SEvan Quan
1023e098bc96SEvan Quan return smum_send_msg_to_smc_with_parameter(hwmgr,
1024e098bc96SEvan Quan PPSMC_MSG_SetFclkGfxClkRatio,
1025e098bc96SEvan Quan data->registry_data.fclk_gfxclk_ratio,
1026e098bc96SEvan Quan NULL);
1027e098bc96SEvan Quan }
1028e098bc96SEvan Quan
vega20_disable_all_smu_features(struct pp_hwmgr * hwmgr)1029e098bc96SEvan Quan static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
1030e098bc96SEvan Quan {
1031e098bc96SEvan Quan struct vega20_hwmgr *data =
1032e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
1033e098bc96SEvan Quan int i, ret = 0;
1034e098bc96SEvan Quan
1035e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
1036e098bc96SEvan Quan PPSMC_MSG_DisableAllSmuFeatures,
1037e098bc96SEvan Quan NULL)) == 0,
1038e098bc96SEvan Quan "[DisableAllSMUFeatures] Failed to disable all smu features!",
1039e098bc96SEvan Quan return ret);
1040e098bc96SEvan Quan
1041e098bc96SEvan Quan for (i = 0; i < GNLD_FEATURES_MAX; i++)
1042e098bc96SEvan Quan data->smu_features[i].enabled = 0;
1043e098bc96SEvan Quan
1044e098bc96SEvan Quan return 0;
1045e098bc96SEvan Quan }
1046e098bc96SEvan Quan
vega20_od8_set_feature_capabilities(struct pp_hwmgr * hwmgr)1047e098bc96SEvan Quan static int vega20_od8_set_feature_capabilities(
1048e098bc96SEvan Quan struct pp_hwmgr *hwmgr)
1049e098bc96SEvan Quan {
1050e098bc96SEvan Quan struct phm_ppt_v3_information *pptable_information =
1051e098bc96SEvan Quan (struct phm_ppt_v3_information *)hwmgr->pptable;
1052e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1053e098bc96SEvan Quan PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1054e098bc96SEvan Quan struct vega20_od8_settings *od_settings = &(data->od8_settings);
1055e098bc96SEvan Quan
1056e098bc96SEvan Quan od_settings->overdrive8_capabilities = 0;
1057e098bc96SEvan Quan
1058e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1059e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1060e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1061e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1062e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1063e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
1064e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
1065e098bc96SEvan Quan
1066e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1067e098bc96SEvan Quan (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1068e098bc96SEvan Quan pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
1069e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1070e098bc96SEvan Quan pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
1071e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
1072e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
1073e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
1074e098bc96SEvan Quan }
1075e098bc96SEvan Quan
1076e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1077e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] =
1078e098bc96SEvan Quan data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value;
1079e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1080e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1081e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1082e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1083e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
1084e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
1085e098bc96SEvan Quan }
1086e098bc96SEvan Quan
1087e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1088e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1089e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1090e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1091e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
1092e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
1093e098bc96SEvan Quan
1094e098bc96SEvan Quan if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
1095e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1096e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1097e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1098e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1099e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
1100e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
1101e098bc96SEvan Quan
1102e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1103e098bc96SEvan Quan (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
1104e098bc96SEvan Quan (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
1105e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1106e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1107e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
1108e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
1109e098bc96SEvan Quan }
1110e098bc96SEvan Quan
1111e098bc96SEvan Quan if (data->smu_features[GNLD_THERMAL].enabled) {
1112e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1113e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1114e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1115e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1116e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
1117e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
1118e098bc96SEvan Quan
1119e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1120e098bc96SEvan Quan pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1121e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1122e098bc96SEvan Quan (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1123e098bc96SEvan Quan pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
1124e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
1125e098bc96SEvan Quan }
1126e098bc96SEvan Quan
1127e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
1128e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
1129e098bc96SEvan Quan
1130e098bc96SEvan Quan if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
1131e098bc96SEvan Quan pp_table->FanZeroRpmEnable)
1132e098bc96SEvan Quan od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
1133e098bc96SEvan Quan
1134e098bc96SEvan Quan if (!od_settings->overdrive8_capabilities)
1135e098bc96SEvan Quan hwmgr->od_enabled = false;
1136e098bc96SEvan Quan
1137e098bc96SEvan Quan return 0;
1138e098bc96SEvan Quan }
1139e098bc96SEvan Quan
vega20_od8_set_feature_id(struct pp_hwmgr * hwmgr)1140e098bc96SEvan Quan static int vega20_od8_set_feature_id(
1141e098bc96SEvan Quan struct pp_hwmgr *hwmgr)
1142e098bc96SEvan Quan {
1143e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1144e098bc96SEvan Quan struct vega20_od8_settings *od_settings = &(data->od8_settings);
1145e098bc96SEvan Quan
1146e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1147e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1148e098bc96SEvan Quan OD8_GFXCLK_LIMITS;
1149e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1150e098bc96SEvan Quan OD8_GFXCLK_LIMITS;
1151e098bc96SEvan Quan } else {
1152e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1153e098bc96SEvan Quan 0;
1154e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1155e098bc96SEvan Quan 0;
1156e098bc96SEvan Quan }
1157e098bc96SEvan Quan
1158e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1159e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1160e098bc96SEvan Quan OD8_GFXCLK_CURVE;
1161e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1162e098bc96SEvan Quan OD8_GFXCLK_CURVE;
1163e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1164e098bc96SEvan Quan OD8_GFXCLK_CURVE;
1165e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1166e098bc96SEvan Quan OD8_GFXCLK_CURVE;
1167e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1168e098bc96SEvan Quan OD8_GFXCLK_CURVE;
1169e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1170e098bc96SEvan Quan OD8_GFXCLK_CURVE;
1171e098bc96SEvan Quan } else {
1172e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1173e098bc96SEvan Quan 0;
1174e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1175e098bc96SEvan Quan 0;
1176e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1177e098bc96SEvan Quan 0;
1178e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1179e098bc96SEvan Quan 0;
1180e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1181e098bc96SEvan Quan 0;
1182e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1183e098bc96SEvan Quan 0;
1184e098bc96SEvan Quan }
1185e098bc96SEvan Quan
1186e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1187e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1188e098bc96SEvan Quan else
1189e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1190e098bc96SEvan Quan
1191e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1192e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1193e098bc96SEvan Quan else
1194e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1195e098bc96SEvan Quan
1196e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1197e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1198e098bc96SEvan Quan OD8_ACOUSTIC_LIMIT_SCLK;
1199e098bc96SEvan Quan else
1200e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1201e098bc96SEvan Quan 0;
1202e098bc96SEvan Quan
1203e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1204e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1205e098bc96SEvan Quan OD8_FAN_SPEED_MIN;
1206e098bc96SEvan Quan else
1207e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1208e098bc96SEvan Quan 0;
1209e098bc96SEvan Quan
1210e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1211e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1212e098bc96SEvan Quan OD8_TEMPERATURE_FAN;
1213e098bc96SEvan Quan else
1214e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1215e098bc96SEvan Quan 0;
1216e098bc96SEvan Quan
1217e098bc96SEvan Quan if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1218e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1219e098bc96SEvan Quan OD8_TEMPERATURE_SYSTEM;
1220e098bc96SEvan Quan else
1221e098bc96SEvan Quan od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1222e098bc96SEvan Quan 0;
1223e098bc96SEvan Quan
1224e098bc96SEvan Quan return 0;
1225e098bc96SEvan Quan }
1226e098bc96SEvan Quan
vega20_od8_get_gfx_clock_base_voltage(struct pp_hwmgr * hwmgr,uint32_t * voltage,uint32_t freq)1227e098bc96SEvan Quan static int vega20_od8_get_gfx_clock_base_voltage(
1228e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
1229e098bc96SEvan Quan uint32_t *voltage,
1230e098bc96SEvan Quan uint32_t freq)
1231e098bc96SEvan Quan {
1232e098bc96SEvan Quan int ret = 0;
1233e098bc96SEvan Quan
1234e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1235e098bc96SEvan Quan PPSMC_MSG_GetAVFSVoltageByDpm,
1236e098bc96SEvan Quan ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq),
1237e098bc96SEvan Quan voltage);
1238e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1239e098bc96SEvan Quan "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1240e098bc96SEvan Quan return ret);
1241e098bc96SEvan Quan
1242e098bc96SEvan Quan *voltage = *voltage / VOLTAGE_SCALE;
1243e098bc96SEvan Quan
1244e098bc96SEvan Quan return 0;
1245e098bc96SEvan Quan }
1246e098bc96SEvan Quan
vega20_od8_initialize_default_settings(struct pp_hwmgr * hwmgr)1247e098bc96SEvan Quan static int vega20_od8_initialize_default_settings(
1248e098bc96SEvan Quan struct pp_hwmgr *hwmgr)
1249e098bc96SEvan Quan {
1250e098bc96SEvan Quan struct phm_ppt_v3_information *pptable_information =
1251e098bc96SEvan Quan (struct phm_ppt_v3_information *)hwmgr->pptable;
1252e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1253e098bc96SEvan Quan struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1254e098bc96SEvan Quan OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1255e098bc96SEvan Quan int i, ret = 0;
1256e098bc96SEvan Quan
1257e098bc96SEvan Quan /* Set Feature Capabilities */
1258e098bc96SEvan Quan vega20_od8_set_feature_capabilities(hwmgr);
1259e098bc96SEvan Quan
1260e098bc96SEvan Quan /* Map FeatureID to individual settings */
1261e098bc96SEvan Quan vega20_od8_set_feature_id(hwmgr);
1262e098bc96SEvan Quan
1263e098bc96SEvan Quan /* Set default values */
1264e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1265e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1266e098bc96SEvan Quan "Failed to export over drive table!",
1267e098bc96SEvan Quan return ret);
1268e098bc96SEvan Quan
1269e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1270e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1271e098bc96SEvan Quan od_table->GfxclkFmin;
1272e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1273e098bc96SEvan Quan od_table->GfxclkFmax;
1274e098bc96SEvan Quan } else {
1275e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1276e098bc96SEvan Quan 0;
1277e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1278e098bc96SEvan Quan 0;
1279e098bc96SEvan Quan }
1280e098bc96SEvan Quan
1281e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1282e098bc96SEvan Quan od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1283e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1284e098bc96SEvan Quan od_table->GfxclkFreq1;
1285e098bc96SEvan Quan
1286e098bc96SEvan Quan od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1287e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1288e098bc96SEvan Quan od_table->GfxclkFreq3;
1289e098bc96SEvan Quan
1290e098bc96SEvan Quan od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1291e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1292e098bc96SEvan Quan od_table->GfxclkFreq2;
1293e098bc96SEvan Quan
1294e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1295e098bc96SEvan Quan &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1296e098bc96SEvan Quan od_table->GfxclkFreq1),
1297e098bc96SEvan Quan "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1298e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1299e098bc96SEvan Quan od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1300e098bc96SEvan Quan * VOLTAGE_SCALE;
1301e098bc96SEvan Quan
1302e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1303e098bc96SEvan Quan &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1304e098bc96SEvan Quan od_table->GfxclkFreq2),
1305e098bc96SEvan Quan "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1306e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1307e098bc96SEvan Quan od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1308e098bc96SEvan Quan * VOLTAGE_SCALE;
1309e098bc96SEvan Quan
1310e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1311e098bc96SEvan Quan &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1312e098bc96SEvan Quan od_table->GfxclkFreq3),
1313e098bc96SEvan Quan "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1314e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1315e098bc96SEvan Quan od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1316e098bc96SEvan Quan * VOLTAGE_SCALE;
1317e098bc96SEvan Quan } else {
1318e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1319e098bc96SEvan Quan 0;
1320e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1321e098bc96SEvan Quan 0;
1322e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1323e098bc96SEvan Quan 0;
1324e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1325e098bc96SEvan Quan 0;
1326e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1327e098bc96SEvan Quan 0;
1328e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1329e098bc96SEvan Quan 0;
1330e098bc96SEvan Quan }
1331e098bc96SEvan Quan
1332e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1333e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1334e098bc96SEvan Quan od_table->UclkFmax;
1335e098bc96SEvan Quan else
1336e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1337e098bc96SEvan Quan 0;
1338e098bc96SEvan Quan
1339e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1340e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1341e098bc96SEvan Quan od_table->OverDrivePct;
1342e098bc96SEvan Quan else
1343e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1344e098bc96SEvan Quan 0;
1345e098bc96SEvan Quan
1346e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1347e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1348e098bc96SEvan Quan od_table->FanMaximumRpm;
1349e098bc96SEvan Quan else
1350e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1351e098bc96SEvan Quan 0;
1352e098bc96SEvan Quan
1353e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1354e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1355e098bc96SEvan Quan od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1356e098bc96SEvan Quan else
1357e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1358e098bc96SEvan Quan 0;
1359e098bc96SEvan Quan
1360e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1361e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1362e098bc96SEvan Quan od_table->FanTargetTemperature;
1363e098bc96SEvan Quan else
1364e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1365e098bc96SEvan Quan 0;
1366e098bc96SEvan Quan
1367e098bc96SEvan Quan if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1368e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1369e098bc96SEvan Quan od_table->MaxOpTemp;
1370e098bc96SEvan Quan else
1371e098bc96SEvan Quan od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1372e098bc96SEvan Quan 0;
1373e098bc96SEvan Quan
1374e098bc96SEvan Quan for (i = 0; i < OD8_SETTING_COUNT; i++) {
1375e098bc96SEvan Quan if (od8_settings->od8_settings_array[i].feature_id) {
1376e098bc96SEvan Quan od8_settings->od8_settings_array[i].min_value =
1377e098bc96SEvan Quan pptable_information->od_settings_min[i];
1378e098bc96SEvan Quan od8_settings->od8_settings_array[i].max_value =
1379e098bc96SEvan Quan pptable_information->od_settings_max[i];
1380e098bc96SEvan Quan od8_settings->od8_settings_array[i].current_value =
1381e098bc96SEvan Quan od8_settings->od8_settings_array[i].default_value;
1382e098bc96SEvan Quan } else {
1383e098bc96SEvan Quan od8_settings->od8_settings_array[i].min_value =
1384e098bc96SEvan Quan 0;
1385e098bc96SEvan Quan od8_settings->od8_settings_array[i].max_value =
1386e098bc96SEvan Quan 0;
1387e098bc96SEvan Quan od8_settings->od8_settings_array[i].current_value =
1388e098bc96SEvan Quan 0;
1389e098bc96SEvan Quan }
1390e098bc96SEvan Quan }
1391e098bc96SEvan Quan
1392e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1393e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1394e098bc96SEvan Quan "Failed to import over drive table!",
1395e098bc96SEvan Quan return ret);
1396e098bc96SEvan Quan
1397e098bc96SEvan Quan return 0;
1398e098bc96SEvan Quan }
1399e098bc96SEvan Quan
vega20_od8_set_settings(struct pp_hwmgr * hwmgr,uint32_t index,uint32_t value)1400e098bc96SEvan Quan static int vega20_od8_set_settings(
1401e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
1402e098bc96SEvan Quan uint32_t index,
1403e098bc96SEvan Quan uint32_t value)
1404e098bc96SEvan Quan {
1405e098bc96SEvan Quan OverDriveTable_t od_table;
1406e098bc96SEvan Quan int ret = 0;
1407e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1408e098bc96SEvan Quan struct vega20_od8_single_setting *od8_settings =
1409e098bc96SEvan Quan data->od8_settings.od8_settings_array;
1410e098bc96SEvan Quan
1411e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1412e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1413e098bc96SEvan Quan "Failed to export over drive table!",
1414e098bc96SEvan Quan return ret);
1415e098bc96SEvan Quan
1416e098bc96SEvan Quan switch (index) {
1417e098bc96SEvan Quan case OD8_SETTING_GFXCLK_FMIN:
1418e098bc96SEvan Quan od_table.GfxclkFmin = (uint16_t)value;
1419e098bc96SEvan Quan break;
1420e098bc96SEvan Quan case OD8_SETTING_GFXCLK_FMAX:
1421e098bc96SEvan Quan if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1422e098bc96SEvan Quan value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1423e098bc96SEvan Quan return -EINVAL;
1424e098bc96SEvan Quan
1425e098bc96SEvan Quan od_table.GfxclkFmax = (uint16_t)value;
1426e098bc96SEvan Quan break;
1427e098bc96SEvan Quan case OD8_SETTING_GFXCLK_FREQ1:
1428e098bc96SEvan Quan od_table.GfxclkFreq1 = (uint16_t)value;
1429e098bc96SEvan Quan break;
1430e098bc96SEvan Quan case OD8_SETTING_GFXCLK_VOLTAGE1:
1431e098bc96SEvan Quan od_table.GfxclkVolt1 = (uint16_t)value;
1432e098bc96SEvan Quan break;
1433e098bc96SEvan Quan case OD8_SETTING_GFXCLK_FREQ2:
1434e098bc96SEvan Quan od_table.GfxclkFreq2 = (uint16_t)value;
1435e098bc96SEvan Quan break;
1436e098bc96SEvan Quan case OD8_SETTING_GFXCLK_VOLTAGE2:
1437e098bc96SEvan Quan od_table.GfxclkVolt2 = (uint16_t)value;
1438e098bc96SEvan Quan break;
1439e098bc96SEvan Quan case OD8_SETTING_GFXCLK_FREQ3:
1440e098bc96SEvan Quan od_table.GfxclkFreq3 = (uint16_t)value;
1441e098bc96SEvan Quan break;
1442e098bc96SEvan Quan case OD8_SETTING_GFXCLK_VOLTAGE3:
1443e098bc96SEvan Quan od_table.GfxclkVolt3 = (uint16_t)value;
1444e098bc96SEvan Quan break;
1445e098bc96SEvan Quan case OD8_SETTING_UCLK_FMAX:
1446e098bc96SEvan Quan if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1447e098bc96SEvan Quan value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1448e098bc96SEvan Quan return -EINVAL;
1449e098bc96SEvan Quan od_table.UclkFmax = (uint16_t)value;
1450e098bc96SEvan Quan break;
1451e098bc96SEvan Quan case OD8_SETTING_POWER_PERCENTAGE:
1452e098bc96SEvan Quan od_table.OverDrivePct = (int16_t)value;
1453e098bc96SEvan Quan break;
1454e098bc96SEvan Quan case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1455e098bc96SEvan Quan od_table.FanMaximumRpm = (uint16_t)value;
1456e098bc96SEvan Quan break;
1457e098bc96SEvan Quan case OD8_SETTING_FAN_MIN_SPEED:
1458e098bc96SEvan Quan od_table.FanMinimumPwm = (uint16_t)value;
1459e098bc96SEvan Quan break;
1460e098bc96SEvan Quan case OD8_SETTING_FAN_TARGET_TEMP:
1461e098bc96SEvan Quan od_table.FanTargetTemperature = (uint16_t)value;
1462e098bc96SEvan Quan break;
1463e098bc96SEvan Quan case OD8_SETTING_OPERATING_TEMP_MAX:
1464e098bc96SEvan Quan od_table.MaxOpTemp = (uint16_t)value;
1465e098bc96SEvan Quan break;
1466e098bc96SEvan Quan }
1467e098bc96SEvan Quan
1468e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1469e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1470e098bc96SEvan Quan "Failed to import over drive table!",
1471e098bc96SEvan Quan return ret);
1472e098bc96SEvan Quan
1473e098bc96SEvan Quan return 0;
1474e098bc96SEvan Quan }
1475e098bc96SEvan Quan
vega20_get_sclk_od(struct pp_hwmgr * hwmgr)1476e098bc96SEvan Quan static int vega20_get_sclk_od(
1477e098bc96SEvan Quan struct pp_hwmgr *hwmgr)
1478e098bc96SEvan Quan {
1479e098bc96SEvan Quan struct vega20_hwmgr *data = hwmgr->backend;
1480e098bc96SEvan Quan struct vega20_single_dpm_table *sclk_table =
1481e098bc96SEvan Quan &(data->dpm_table.gfx_table);
1482e098bc96SEvan Quan struct vega20_single_dpm_table *golden_sclk_table =
1483e098bc96SEvan Quan &(data->golden_dpm_table.gfx_table);
1484e098bc96SEvan Quan int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1485e098bc96SEvan Quan int golden_value = golden_sclk_table->dpm_levels
1486e098bc96SEvan Quan [golden_sclk_table->count - 1].value;
1487e098bc96SEvan Quan
1488e098bc96SEvan Quan /* od percentage */
1489e098bc96SEvan Quan value -= golden_value;
1490e098bc96SEvan Quan value = DIV_ROUND_UP(value * 100, golden_value);
1491e098bc96SEvan Quan
1492e098bc96SEvan Quan return value;
1493e098bc96SEvan Quan }
1494e098bc96SEvan Quan
vega20_set_sclk_od(struct pp_hwmgr * hwmgr,uint32_t value)1495e098bc96SEvan Quan static int vega20_set_sclk_od(
1496e098bc96SEvan Quan struct pp_hwmgr *hwmgr, uint32_t value)
1497e098bc96SEvan Quan {
1498e098bc96SEvan Quan struct vega20_hwmgr *data = hwmgr->backend;
1499e098bc96SEvan Quan struct vega20_single_dpm_table *golden_sclk_table =
1500e098bc96SEvan Quan &(data->golden_dpm_table.gfx_table);
1501e098bc96SEvan Quan uint32_t od_sclk;
1502e098bc96SEvan Quan int ret = 0;
1503e098bc96SEvan Quan
1504e098bc96SEvan Quan od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1505e098bc96SEvan Quan od_sclk /= 100;
1506e098bc96SEvan Quan od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1507e098bc96SEvan Quan
1508e098bc96SEvan Quan ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1509e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1510e098bc96SEvan Quan "[SetSclkOD] failed to set od gfxclk!",
1511e098bc96SEvan Quan return ret);
1512e098bc96SEvan Quan
1513e098bc96SEvan Quan /* retrieve updated gfxclk table */
1514e098bc96SEvan Quan ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1515e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1516e098bc96SEvan Quan "[SetSclkOD] failed to refresh gfxclk table!",
1517e098bc96SEvan Quan return ret);
1518e098bc96SEvan Quan
1519e098bc96SEvan Quan return 0;
1520e098bc96SEvan Quan }
1521e098bc96SEvan Quan
vega20_get_mclk_od(struct pp_hwmgr * hwmgr)1522e098bc96SEvan Quan static int vega20_get_mclk_od(
1523e098bc96SEvan Quan struct pp_hwmgr *hwmgr)
1524e098bc96SEvan Quan {
1525e098bc96SEvan Quan struct vega20_hwmgr *data = hwmgr->backend;
1526e098bc96SEvan Quan struct vega20_single_dpm_table *mclk_table =
1527e098bc96SEvan Quan &(data->dpm_table.mem_table);
1528e098bc96SEvan Quan struct vega20_single_dpm_table *golden_mclk_table =
1529e098bc96SEvan Quan &(data->golden_dpm_table.mem_table);
1530e098bc96SEvan Quan int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1531e098bc96SEvan Quan int golden_value = golden_mclk_table->dpm_levels
1532e098bc96SEvan Quan [golden_mclk_table->count - 1].value;
1533e098bc96SEvan Quan
1534e098bc96SEvan Quan /* od percentage */
1535e098bc96SEvan Quan value -= golden_value;
1536e098bc96SEvan Quan value = DIV_ROUND_UP(value * 100, golden_value);
1537e098bc96SEvan Quan
1538e098bc96SEvan Quan return value;
1539e098bc96SEvan Quan }
1540e098bc96SEvan Quan
vega20_set_mclk_od(struct pp_hwmgr * hwmgr,uint32_t value)1541e098bc96SEvan Quan static int vega20_set_mclk_od(
1542e098bc96SEvan Quan struct pp_hwmgr *hwmgr, uint32_t value)
1543e098bc96SEvan Quan {
1544e098bc96SEvan Quan struct vega20_hwmgr *data = hwmgr->backend;
1545e098bc96SEvan Quan struct vega20_single_dpm_table *golden_mclk_table =
1546e098bc96SEvan Quan &(data->golden_dpm_table.mem_table);
1547e098bc96SEvan Quan uint32_t od_mclk;
1548e098bc96SEvan Quan int ret = 0;
1549e098bc96SEvan Quan
1550e098bc96SEvan Quan od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1551e098bc96SEvan Quan od_mclk /= 100;
1552e098bc96SEvan Quan od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1553e098bc96SEvan Quan
1554e098bc96SEvan Quan ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1555e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1556e098bc96SEvan Quan "[SetMclkOD] failed to set od memclk!",
1557e098bc96SEvan Quan return ret);
1558e098bc96SEvan Quan
1559e098bc96SEvan Quan /* retrieve updated memclk table */
1560e098bc96SEvan Quan ret = vega20_setup_memclk_dpm_table(hwmgr);
1561e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
1562e098bc96SEvan Quan "[SetMclkOD] failed to refresh memclk table!",
1563e098bc96SEvan Quan return ret);
1564e098bc96SEvan Quan
1565e098bc96SEvan Quan return 0;
1566e098bc96SEvan Quan }
1567e098bc96SEvan Quan
vega20_populate_umdpstate_clocks(struct pp_hwmgr * hwmgr)1568b1a9557aSEvan Quan static void vega20_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
1569e098bc96SEvan Quan {
1570e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1571e098bc96SEvan Quan struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1572e098bc96SEvan Quan struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1573e098bc96SEvan Quan
1574e098bc96SEvan Quan if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1575e098bc96SEvan Quan mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1576e098bc96SEvan Quan hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1577e098bc96SEvan Quan hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1578b1a9557aSEvan Quan } else {
1579b1a9557aSEvan Quan hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1580b1a9557aSEvan Quan hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1581e098bc96SEvan Quan }
1582e098bc96SEvan Quan
1583b1a9557aSEvan Quan hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value;
1584b1a9557aSEvan Quan hwmgr->pstate_mclk_peak = mem_table->dpm_levels[mem_table->count - 1].value;
1585e098bc96SEvan Quan }
1586e098bc96SEvan Quan
vega20_get_max_sustainable_clock(struct pp_hwmgr * hwmgr,PP_Clock * clock,PPCLK_e clock_select)1587e098bc96SEvan Quan static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1588e098bc96SEvan Quan PP_Clock *clock, PPCLK_e clock_select)
1589e098bc96SEvan Quan {
1590e098bc96SEvan Quan int ret = 0;
1591e098bc96SEvan Quan
1592e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1593e098bc96SEvan Quan PPSMC_MSG_GetDcModeMaxDpmFreq,
1594e098bc96SEvan Quan (clock_select << 16),
1595e098bc96SEvan Quan clock)) == 0,
1596e098bc96SEvan Quan "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1597e098bc96SEvan Quan return ret);
1598e098bc96SEvan Quan
1599e098bc96SEvan Quan /* if DC limit is zero, return AC limit */
1600e098bc96SEvan Quan if (*clock == 0) {
1601e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1602e098bc96SEvan Quan PPSMC_MSG_GetMaxDpmFreq,
1603e098bc96SEvan Quan (clock_select << 16),
1604e098bc96SEvan Quan clock)) == 0,
1605e098bc96SEvan Quan "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1606e098bc96SEvan Quan return ret);
1607e098bc96SEvan Quan }
1608e098bc96SEvan Quan
1609e098bc96SEvan Quan return 0;
1610e098bc96SEvan Quan }
1611e098bc96SEvan Quan
vega20_init_max_sustainable_clocks(struct pp_hwmgr * hwmgr)1612e098bc96SEvan Quan static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1613e098bc96SEvan Quan {
1614e098bc96SEvan Quan struct vega20_hwmgr *data =
1615e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
1616e098bc96SEvan Quan struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1617e098bc96SEvan Quan &(data->max_sustainable_clocks);
1618e098bc96SEvan Quan int ret = 0;
1619e098bc96SEvan Quan
1620e098bc96SEvan Quan max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1621e098bc96SEvan Quan max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1622e098bc96SEvan Quan max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1623e098bc96SEvan Quan max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1624e098bc96SEvan Quan max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1625e098bc96SEvan Quan max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1626e098bc96SEvan Quan
1627e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled)
1628e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1629e098bc96SEvan Quan &(max_sustainable_clocks->uclock),
1630e098bc96SEvan Quan PPCLK_UCLK)) == 0,
1631e098bc96SEvan Quan "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1632e098bc96SEvan Quan return ret);
1633e098bc96SEvan Quan
1634e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1635e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1636e098bc96SEvan Quan &(max_sustainable_clocks->soc_clock),
1637e098bc96SEvan Quan PPCLK_SOCCLK)) == 0,
1638e098bc96SEvan Quan "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1639e098bc96SEvan Quan return ret);
1640e098bc96SEvan Quan
1641e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1642e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1643e098bc96SEvan Quan &(max_sustainable_clocks->dcef_clock),
1644e098bc96SEvan Quan PPCLK_DCEFCLK)) == 0,
1645e098bc96SEvan Quan "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1646e098bc96SEvan Quan return ret);
1647e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1648e098bc96SEvan Quan &(max_sustainable_clocks->display_clock),
1649e098bc96SEvan Quan PPCLK_DISPCLK)) == 0,
1650e098bc96SEvan Quan "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1651e098bc96SEvan Quan return ret);
1652e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1653e098bc96SEvan Quan &(max_sustainable_clocks->phy_clock),
1654e098bc96SEvan Quan PPCLK_PHYCLK)) == 0,
1655e098bc96SEvan Quan "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1656e098bc96SEvan Quan return ret);
1657e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1658e098bc96SEvan Quan &(max_sustainable_clocks->pixel_clock),
1659e098bc96SEvan Quan PPCLK_PIXCLK)) == 0,
1660e098bc96SEvan Quan "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1661e098bc96SEvan Quan return ret);
1662e098bc96SEvan Quan }
1663e098bc96SEvan Quan
1664e098bc96SEvan Quan if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1665e098bc96SEvan Quan max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1666e098bc96SEvan Quan
1667e098bc96SEvan Quan return 0;
1668e098bc96SEvan Quan }
1669e098bc96SEvan Quan
vega20_enable_mgpu_fan_boost(struct pp_hwmgr * hwmgr)1670e098bc96SEvan Quan static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1671e098bc96SEvan Quan {
1672e098bc96SEvan Quan int result;
1673e098bc96SEvan Quan
1674e098bc96SEvan Quan result = smum_send_msg_to_smc(hwmgr,
1675e098bc96SEvan Quan PPSMC_MSG_SetMGpuFanBoostLimitRpm,
1676e098bc96SEvan Quan NULL);
1677e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1678e098bc96SEvan Quan "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1679e098bc96SEvan Quan return result);
1680e098bc96SEvan Quan
1681e098bc96SEvan Quan return 0;
1682e098bc96SEvan Quan }
1683e098bc96SEvan Quan
vega20_init_powergate_state(struct pp_hwmgr * hwmgr)1684e098bc96SEvan Quan static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1685e098bc96SEvan Quan {
1686e098bc96SEvan Quan struct vega20_hwmgr *data =
1687e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
1688e098bc96SEvan Quan
1689e098bc96SEvan Quan data->uvd_power_gated = true;
1690e098bc96SEvan Quan data->vce_power_gated = true;
1691e098bc96SEvan Quan }
1692e098bc96SEvan Quan
vega20_enable_dpm_tasks(struct pp_hwmgr * hwmgr)1693e098bc96SEvan Quan static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1694e098bc96SEvan Quan {
1695e098bc96SEvan Quan int result = 0;
1696e098bc96SEvan Quan
1697e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
1698e098bc96SEvan Quan PPSMC_MSG_NumOfDisplays, 0, NULL);
1699e098bc96SEvan Quan
1700e098bc96SEvan Quan result = vega20_set_allowed_featuresmask(hwmgr);
1701e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1702e098bc96SEvan Quan "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1703e098bc96SEvan Quan return result);
1704e098bc96SEvan Quan
1705e098bc96SEvan Quan result = vega20_init_smc_table(hwmgr);
1706e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1707e098bc96SEvan Quan "[EnableDPMTasks] Failed to initialize SMC table!",
1708e098bc96SEvan Quan return result);
1709e098bc96SEvan Quan
1710e098bc96SEvan Quan result = vega20_run_btc(hwmgr);
1711e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1712e098bc96SEvan Quan "[EnableDPMTasks] Failed to run btc!",
1713e098bc96SEvan Quan return result);
1714e098bc96SEvan Quan
1715e098bc96SEvan Quan result = vega20_run_btc_afll(hwmgr);
1716e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1717e098bc96SEvan Quan "[EnableDPMTasks] Failed to run btc afll!",
1718e098bc96SEvan Quan return result);
1719e098bc96SEvan Quan
1720e098bc96SEvan Quan result = vega20_enable_all_smu_features(hwmgr);
1721e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1722e098bc96SEvan Quan "[EnableDPMTasks] Failed to enable all smu features!",
1723e098bc96SEvan Quan return result);
1724e098bc96SEvan Quan
1725e098bc96SEvan Quan result = vega20_override_pcie_parameters(hwmgr);
1726e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1727e098bc96SEvan Quan "[EnableDPMTasks] Failed to override pcie parameters!",
1728e098bc96SEvan Quan return result);
1729e098bc96SEvan Quan
1730e098bc96SEvan Quan result = vega20_notify_smc_display_change(hwmgr);
1731e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1732e098bc96SEvan Quan "[EnableDPMTasks] Failed to notify smc display change!",
1733e098bc96SEvan Quan return result);
1734e098bc96SEvan Quan
1735e098bc96SEvan Quan result = vega20_send_clock_ratio(hwmgr);
1736e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1737e098bc96SEvan Quan "[EnableDPMTasks] Failed to send clock ratio!",
1738e098bc96SEvan Quan return result);
1739e098bc96SEvan Quan
1740e098bc96SEvan Quan /* Initialize UVD/VCE powergating state */
1741e098bc96SEvan Quan vega20_init_powergate_state(hwmgr);
1742e098bc96SEvan Quan
1743e098bc96SEvan Quan result = vega20_setup_default_dpm_tables(hwmgr);
1744e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1745e098bc96SEvan Quan "[EnableDPMTasks] Failed to setup default DPM tables!",
1746e098bc96SEvan Quan return result);
1747e098bc96SEvan Quan
1748e098bc96SEvan Quan result = vega20_init_max_sustainable_clocks(hwmgr);
1749e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1750e098bc96SEvan Quan "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1751e098bc96SEvan Quan return result);
1752e098bc96SEvan Quan
1753e098bc96SEvan Quan result = vega20_power_control_set_level(hwmgr);
1754e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1755e098bc96SEvan Quan "[EnableDPMTasks] Failed to power control set level!",
1756e098bc96SEvan Quan return result);
1757e098bc96SEvan Quan
1758e098bc96SEvan Quan result = vega20_od8_initialize_default_settings(hwmgr);
1759e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1760e098bc96SEvan Quan "[EnableDPMTasks] Failed to initialize odn settings!",
1761e098bc96SEvan Quan return result);
1762e098bc96SEvan Quan
1763b1a9557aSEvan Quan vega20_populate_umdpstate_clocks(hwmgr);
1764e098bc96SEvan Quan
1765e098bc96SEvan Quan result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1766e098bc96SEvan Quan POWER_SOURCE_AC << 16, &hwmgr->default_power_limit);
1767e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
1768e098bc96SEvan Quan "[GetPptLimit] get default PPT limit failed!",
1769e098bc96SEvan Quan return result);
1770e098bc96SEvan Quan hwmgr->power_limit =
1771e098bc96SEvan Quan hwmgr->default_power_limit;
1772e098bc96SEvan Quan
1773e098bc96SEvan Quan return 0;
1774e098bc96SEvan Quan }
1775e098bc96SEvan Quan
vega20_find_lowest_dpm_level(struct vega20_single_dpm_table * table)1776e098bc96SEvan Quan static uint32_t vega20_find_lowest_dpm_level(
1777e098bc96SEvan Quan struct vega20_single_dpm_table *table)
1778e098bc96SEvan Quan {
1779e098bc96SEvan Quan uint32_t i;
1780e098bc96SEvan Quan
1781e098bc96SEvan Quan for (i = 0; i < table->count; i++) {
1782e098bc96SEvan Quan if (table->dpm_levels[i].enabled)
1783e098bc96SEvan Quan break;
1784e098bc96SEvan Quan }
1785e098bc96SEvan Quan if (i >= table->count) {
1786e098bc96SEvan Quan i = 0;
1787e098bc96SEvan Quan table->dpm_levels[i].enabled = true;
1788e098bc96SEvan Quan }
1789e098bc96SEvan Quan
1790e098bc96SEvan Quan return i;
1791e098bc96SEvan Quan }
1792e098bc96SEvan Quan
vega20_find_highest_dpm_level(struct vega20_single_dpm_table * table)1793e098bc96SEvan Quan static uint32_t vega20_find_highest_dpm_level(
1794e098bc96SEvan Quan struct vega20_single_dpm_table *table)
1795e098bc96SEvan Quan {
1796e098bc96SEvan Quan int i = 0;
1797e098bc96SEvan Quan
1798e098bc96SEvan Quan PP_ASSERT_WITH_CODE(table != NULL,
1799e098bc96SEvan Quan "[FindHighestDPMLevel] DPM Table does not exist!",
1800e098bc96SEvan Quan return 0);
1801e098bc96SEvan Quan PP_ASSERT_WITH_CODE(table->count > 0,
1802e098bc96SEvan Quan "[FindHighestDPMLevel] DPM Table has no entry!",
1803e098bc96SEvan Quan return 0);
1804e098bc96SEvan Quan PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1805e098bc96SEvan Quan "[FindHighestDPMLevel] DPM Table has too many entries!",
1806e098bc96SEvan Quan return MAX_REGULAR_DPM_NUMBER - 1);
1807e098bc96SEvan Quan
1808e098bc96SEvan Quan for (i = table->count - 1; i >= 0; i--) {
1809e098bc96SEvan Quan if (table->dpm_levels[i].enabled)
1810e098bc96SEvan Quan break;
1811e098bc96SEvan Quan }
1812e098bc96SEvan Quan if (i < 0) {
1813e098bc96SEvan Quan i = 0;
1814e098bc96SEvan Quan table->dpm_levels[i].enabled = true;
1815e098bc96SEvan Quan }
1816e098bc96SEvan Quan
1817e098bc96SEvan Quan return i;
1818e098bc96SEvan Quan }
1819e098bc96SEvan Quan
vega20_upload_dpm_min_level(struct pp_hwmgr * hwmgr,uint32_t feature_mask)1820e098bc96SEvan Quan static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1821e098bc96SEvan Quan {
1822e098bc96SEvan Quan struct vega20_hwmgr *data =
1823e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
1824e098bc96SEvan Quan uint32_t min_freq;
1825e098bc96SEvan Quan int ret = 0;
1826e098bc96SEvan Quan
1827e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1828e098bc96SEvan Quan (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1829e098bc96SEvan Quan min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1830e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1831e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1832e098bc96SEvan Quan (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1833e098bc96SEvan Quan NULL)),
1834e098bc96SEvan Quan "Failed to set soft min gfxclk !",
1835e098bc96SEvan Quan return ret);
1836e098bc96SEvan Quan }
1837e098bc96SEvan Quan
1838e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1839e098bc96SEvan Quan (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1840e098bc96SEvan Quan min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1841e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1842e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1843e098bc96SEvan Quan (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1844e098bc96SEvan Quan NULL)),
1845e098bc96SEvan Quan "Failed to set soft min memclk !",
1846e098bc96SEvan Quan return ret);
1847e098bc96SEvan Quan }
1848e098bc96SEvan Quan
1849e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UVD].enabled &&
1850e098bc96SEvan Quan (feature_mask & FEATURE_DPM_UVD_MASK)) {
1851e098bc96SEvan Quan min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1852e098bc96SEvan Quan
1853e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1854e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1855e098bc96SEvan Quan (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1856e098bc96SEvan Quan NULL)),
1857e098bc96SEvan Quan "Failed to set soft min vclk!",
1858e098bc96SEvan Quan return ret);
1859e098bc96SEvan Quan
1860e098bc96SEvan Quan min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1861e098bc96SEvan Quan
1862e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1863e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1864e098bc96SEvan Quan (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1865e098bc96SEvan Quan NULL)),
1866e098bc96SEvan Quan "Failed to set soft min dclk!",
1867e098bc96SEvan Quan return ret);
1868e098bc96SEvan Quan }
1869e098bc96SEvan Quan
1870e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_VCE].enabled &&
1871e098bc96SEvan Quan (feature_mask & FEATURE_DPM_VCE_MASK)) {
1872e098bc96SEvan Quan min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1873e098bc96SEvan Quan
1874e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1875e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1876e098bc96SEvan Quan (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1877e098bc96SEvan Quan NULL)),
1878e098bc96SEvan Quan "Failed to set soft min eclk!",
1879e098bc96SEvan Quan return ret);
1880e098bc96SEvan Quan }
1881e098bc96SEvan Quan
1882e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1883e098bc96SEvan Quan (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1884e098bc96SEvan Quan min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1885e098bc96SEvan Quan
1886e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1887e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1888e098bc96SEvan Quan (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1889e098bc96SEvan Quan NULL)),
1890e098bc96SEvan Quan "Failed to set soft min socclk!",
1891e098bc96SEvan Quan return ret);
1892e098bc96SEvan Quan }
1893e098bc96SEvan Quan
1894e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1895e098bc96SEvan Quan (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1896e098bc96SEvan Quan min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
1897e098bc96SEvan Quan
1898e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1899e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1900e098bc96SEvan Quan (PPCLK_FCLK << 16) | (min_freq & 0xffff),
1901e098bc96SEvan Quan NULL)),
1902e098bc96SEvan Quan "Failed to set soft min fclk!",
1903e098bc96SEvan Quan return ret);
1904e098bc96SEvan Quan }
1905e098bc96SEvan Quan
1906e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
1907e098bc96SEvan Quan (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1908e098bc96SEvan Quan min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1909e098bc96SEvan Quan
1910e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1911e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetHardMinByFreq,
1912e098bc96SEvan Quan (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1913e098bc96SEvan Quan NULL)),
1914e098bc96SEvan Quan "Failed to set hard min dcefclk!",
1915e098bc96SEvan Quan return ret);
1916e098bc96SEvan Quan }
1917e098bc96SEvan Quan
1918e098bc96SEvan Quan return ret;
1919e098bc96SEvan Quan }
1920e098bc96SEvan Quan
vega20_upload_dpm_max_level(struct pp_hwmgr * hwmgr,uint32_t feature_mask)1921e098bc96SEvan Quan static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1922e098bc96SEvan Quan {
1923e098bc96SEvan Quan struct vega20_hwmgr *data =
1924e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
1925e098bc96SEvan Quan uint32_t max_freq;
1926e098bc96SEvan Quan int ret = 0;
1927e098bc96SEvan Quan
1928e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1929e098bc96SEvan Quan (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1930e098bc96SEvan Quan max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1931e098bc96SEvan Quan
1932e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1933e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1934e098bc96SEvan Quan (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1935e098bc96SEvan Quan NULL)),
1936e098bc96SEvan Quan "Failed to set soft max gfxclk!",
1937e098bc96SEvan Quan return ret);
1938e098bc96SEvan Quan }
1939e098bc96SEvan Quan
1940e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1941e098bc96SEvan Quan (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1942e098bc96SEvan Quan max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1943e098bc96SEvan Quan
1944e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1945e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1946e098bc96SEvan Quan (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1947e098bc96SEvan Quan NULL)),
1948e098bc96SEvan Quan "Failed to set soft max memclk!",
1949e098bc96SEvan Quan return ret);
1950e098bc96SEvan Quan }
1951e098bc96SEvan Quan
1952e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UVD].enabled &&
1953e098bc96SEvan Quan (feature_mask & FEATURE_DPM_UVD_MASK)) {
1954e098bc96SEvan Quan max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1955e098bc96SEvan Quan
1956e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1957e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1958e098bc96SEvan Quan (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1959e098bc96SEvan Quan NULL)),
1960e098bc96SEvan Quan "Failed to set soft max vclk!",
1961e098bc96SEvan Quan return ret);
1962e098bc96SEvan Quan
1963e098bc96SEvan Quan max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1964e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1965e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1966e098bc96SEvan Quan (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1967e098bc96SEvan Quan NULL)),
1968e098bc96SEvan Quan "Failed to set soft max dclk!",
1969e098bc96SEvan Quan return ret);
1970e098bc96SEvan Quan }
1971e098bc96SEvan Quan
1972e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_VCE].enabled &&
1973e098bc96SEvan Quan (feature_mask & FEATURE_DPM_VCE_MASK)) {
1974e098bc96SEvan Quan max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1975e098bc96SEvan Quan
1976e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1977e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1978e098bc96SEvan Quan (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1979e098bc96SEvan Quan NULL)),
1980e098bc96SEvan Quan "Failed to set soft max eclk!",
1981e098bc96SEvan Quan return ret);
1982e098bc96SEvan Quan }
1983e098bc96SEvan Quan
1984e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1985e098bc96SEvan Quan (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1986e098bc96SEvan Quan max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1987e098bc96SEvan Quan
1988e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1989e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1990e098bc96SEvan Quan (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1991e098bc96SEvan Quan NULL)),
1992e098bc96SEvan Quan "Failed to set soft max socclk!",
1993e098bc96SEvan Quan return ret);
1994e098bc96SEvan Quan }
1995e098bc96SEvan Quan
1996e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1997e098bc96SEvan Quan (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1998e098bc96SEvan Quan max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
1999e098bc96SEvan Quan
2000e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
2001e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
2002e098bc96SEvan Quan (PPCLK_FCLK << 16) | (max_freq & 0xffff),
2003e098bc96SEvan Quan NULL)),
2004e098bc96SEvan Quan "Failed to set soft max fclk!",
2005e098bc96SEvan Quan return ret);
2006e098bc96SEvan Quan }
2007e098bc96SEvan Quan
2008e098bc96SEvan Quan return ret;
2009e098bc96SEvan Quan }
2010e098bc96SEvan Quan
vega20_enable_disable_vce_dpm(struct pp_hwmgr * hwmgr,bool enable)2011e098bc96SEvan Quan static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
2012e098bc96SEvan Quan {
2013e098bc96SEvan Quan struct vega20_hwmgr *data =
2014e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2015e098bc96SEvan Quan int ret = 0;
2016e098bc96SEvan Quan
2017e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_VCE].supported) {
2018e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
2019e098bc96SEvan Quan if (enable)
2020e098bc96SEvan Quan PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
2021e098bc96SEvan Quan else
2022e098bc96SEvan Quan PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
2023e098bc96SEvan Quan }
2024e098bc96SEvan Quan
2025e098bc96SEvan Quan ret = vega20_enable_smc_features(hwmgr,
2026e098bc96SEvan Quan enable,
2027e098bc96SEvan Quan data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
2028e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2029e098bc96SEvan Quan "Attempt to Enable/Disable DPM VCE Failed!",
2030e098bc96SEvan Quan return ret);
2031e098bc96SEvan Quan data->smu_features[GNLD_DPM_VCE].enabled = enable;
2032e098bc96SEvan Quan }
2033e098bc96SEvan Quan
2034e098bc96SEvan Quan return 0;
2035e098bc96SEvan Quan }
2036e098bc96SEvan Quan
vega20_get_clock_ranges(struct pp_hwmgr * hwmgr,uint32_t * clock,PPCLK_e clock_select,bool max)2037e098bc96SEvan Quan static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
2038e098bc96SEvan Quan uint32_t *clock,
2039e098bc96SEvan Quan PPCLK_e clock_select,
2040e098bc96SEvan Quan bool max)
2041e098bc96SEvan Quan {
2042e098bc96SEvan Quan int ret;
2043e098bc96SEvan Quan *clock = 0;
2044e098bc96SEvan Quan
2045e098bc96SEvan Quan if (max) {
2046e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2047e098bc96SEvan Quan PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16),
2048e098bc96SEvan Quan clock)) == 0,
2049e098bc96SEvan Quan "[GetClockRanges] Failed to get max clock from SMC!",
2050e098bc96SEvan Quan return ret);
2051e098bc96SEvan Quan } else {
2052e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2053e098bc96SEvan Quan PPSMC_MSG_GetMinDpmFreq,
2054e098bc96SEvan Quan (clock_select << 16),
2055e098bc96SEvan Quan clock)) == 0,
2056e098bc96SEvan Quan "[GetClockRanges] Failed to get min clock from SMC!",
2057e098bc96SEvan Quan return ret);
2058e098bc96SEvan Quan }
2059e098bc96SEvan Quan
2060e098bc96SEvan Quan return 0;
2061e098bc96SEvan Quan }
2062e098bc96SEvan Quan
vega20_dpm_get_sclk(struct pp_hwmgr * hwmgr,bool low)2063e098bc96SEvan Quan static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
2064e098bc96SEvan Quan {
2065e098bc96SEvan Quan struct vega20_hwmgr *data =
2066e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2067e098bc96SEvan Quan uint32_t gfx_clk;
2068e098bc96SEvan Quan int ret = 0;
2069e098bc96SEvan Quan
2070e098bc96SEvan Quan PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2071e098bc96SEvan Quan "[GetSclks]: gfxclk dpm not enabled!\n",
2072e098bc96SEvan Quan return -EPERM);
2073e098bc96SEvan Quan
2074e098bc96SEvan Quan if (low) {
2075e098bc96SEvan Quan ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
2076e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2077e098bc96SEvan Quan "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
2078e098bc96SEvan Quan return ret);
2079e098bc96SEvan Quan } else {
2080e098bc96SEvan Quan ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
2081e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2082e098bc96SEvan Quan "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
2083e098bc96SEvan Quan return ret);
2084e098bc96SEvan Quan }
2085e098bc96SEvan Quan
2086e098bc96SEvan Quan return (gfx_clk * 100);
2087e098bc96SEvan Quan }
2088e098bc96SEvan Quan
vega20_dpm_get_mclk(struct pp_hwmgr * hwmgr,bool low)2089e098bc96SEvan Quan static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2090e098bc96SEvan Quan {
2091e098bc96SEvan Quan struct vega20_hwmgr *data =
2092e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2093e098bc96SEvan Quan uint32_t mem_clk;
2094e098bc96SEvan Quan int ret = 0;
2095e098bc96SEvan Quan
2096e098bc96SEvan Quan PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2097e098bc96SEvan Quan "[MemMclks]: memclk dpm not enabled!\n",
2098e098bc96SEvan Quan return -EPERM);
2099e098bc96SEvan Quan
2100e098bc96SEvan Quan if (low) {
2101e098bc96SEvan Quan ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
2102e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2103e098bc96SEvan Quan "[GetMclks]: fail to get min PPCLK_UCLK\n",
2104e098bc96SEvan Quan return ret);
2105e098bc96SEvan Quan } else {
2106e098bc96SEvan Quan ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
2107e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2108e098bc96SEvan Quan "[GetMclks]: fail to get max PPCLK_UCLK\n",
2109e098bc96SEvan Quan return ret);
2110e098bc96SEvan Quan }
2111e098bc96SEvan Quan
2112e098bc96SEvan Quan return (mem_clk * 100);
2113e098bc96SEvan Quan }
2114e098bc96SEvan Quan
vega20_get_metrics_table(struct pp_hwmgr * hwmgr,SmuMetrics_t * metrics_table,bool bypass_cache)2115e098bc96SEvan Quan static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr,
2116e098bc96SEvan Quan SmuMetrics_t *metrics_table,
2117e098bc96SEvan Quan bool bypass_cache)
2118e098bc96SEvan Quan {
2119e098bc96SEvan Quan struct vega20_hwmgr *data =
2120e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2121e098bc96SEvan Quan int ret = 0;
2122e098bc96SEvan Quan
2123e098bc96SEvan Quan if (bypass_cache ||
2124e098bc96SEvan Quan !data->metrics_time ||
2125e098bc96SEvan Quan time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) {
2126e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr,
2127e098bc96SEvan Quan (uint8_t *)(&data->metrics_table),
2128e098bc96SEvan Quan TABLE_SMU_METRICS,
2129e098bc96SEvan Quan true);
2130e098bc96SEvan Quan if (ret) {
2131e098bc96SEvan Quan pr_info("Failed to export SMU metrics table!\n");
2132e098bc96SEvan Quan return ret;
2133e098bc96SEvan Quan }
2134e098bc96SEvan Quan data->metrics_time = jiffies;
2135e098bc96SEvan Quan }
2136e098bc96SEvan Quan
2137e098bc96SEvan Quan if (metrics_table)
2138e098bc96SEvan Quan memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
2139e098bc96SEvan Quan
2140e098bc96SEvan Quan return ret;
2141e098bc96SEvan Quan }
2142e098bc96SEvan Quan
vega20_get_gpu_power(struct pp_hwmgr * hwmgr,int idx,uint32_t * query)2143765bbbecSMario Limonciello static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr, int idx,
2144e098bc96SEvan Quan uint32_t *query)
2145e098bc96SEvan Quan {
2146e098bc96SEvan Quan int ret = 0;
2147e098bc96SEvan Quan SmuMetrics_t metrics_table;
2148e098bc96SEvan Quan
2149e098bc96SEvan Quan ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2150e098bc96SEvan Quan if (ret)
2151e098bc96SEvan Quan return ret;
2152e098bc96SEvan Quan
2153e098bc96SEvan Quan /* For the 40.46 release, they changed the value name */
2154765bbbecSMario Limonciello switch (idx) {
21559366c2e8SMario Limonciello case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
2156e098bc96SEvan Quan if (hwmgr->smu_version == 0x282e00)
2157e098bc96SEvan Quan *query = metrics_table.AverageSocketPower << 8;
2158e098bc96SEvan Quan else
2159765bbbecSMario Limonciello ret = -EOPNOTSUPP;
2160765bbbecSMario Limonciello break;
2161765bbbecSMario Limonciello case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2162e098bc96SEvan Quan *query = metrics_table.CurrSocketPower << 8;
2163765bbbecSMario Limonciello break;
2164765bbbecSMario Limonciello }
2165e098bc96SEvan Quan
2166e098bc96SEvan Quan return ret;
2167e098bc96SEvan Quan }
2168e098bc96SEvan Quan
vega20_get_current_clk_freq(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t * clk_freq)2169e098bc96SEvan Quan static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
2170e098bc96SEvan Quan PPCLK_e clk_id, uint32_t *clk_freq)
2171e098bc96SEvan Quan {
2172e098bc96SEvan Quan int ret = 0;
2173e098bc96SEvan Quan
2174e098bc96SEvan Quan *clk_freq = 0;
2175e098bc96SEvan Quan
2176e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2177e098bc96SEvan Quan PPSMC_MSG_GetDpmClockFreq, (clk_id << 16),
2178e098bc96SEvan Quan clk_freq)) == 0,
2179e098bc96SEvan Quan "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
2180e098bc96SEvan Quan return ret);
2181e098bc96SEvan Quan
2182e098bc96SEvan Quan *clk_freq = *clk_freq * 100;
2183e098bc96SEvan Quan
2184e098bc96SEvan Quan return 0;
2185e098bc96SEvan Quan }
2186e098bc96SEvan Quan
vega20_get_current_activity_percent(struct pp_hwmgr * hwmgr,int idx,uint32_t * activity_percent)2187e098bc96SEvan Quan static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
2188e098bc96SEvan Quan int idx,
2189e098bc96SEvan Quan uint32_t *activity_percent)
2190e098bc96SEvan Quan {
2191e098bc96SEvan Quan int ret = 0;
2192e098bc96SEvan Quan SmuMetrics_t metrics_table;
2193e098bc96SEvan Quan
2194e098bc96SEvan Quan ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2195e098bc96SEvan Quan if (ret)
2196e098bc96SEvan Quan return ret;
2197e098bc96SEvan Quan
2198e098bc96SEvan Quan switch (idx) {
2199e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GPU_LOAD:
2200e098bc96SEvan Quan *activity_percent = metrics_table.AverageGfxActivity;
2201e098bc96SEvan Quan break;
2202e098bc96SEvan Quan case AMDGPU_PP_SENSOR_MEM_LOAD:
2203e098bc96SEvan Quan *activity_percent = metrics_table.AverageUclkActivity;
2204e098bc96SEvan Quan break;
2205e098bc96SEvan Quan default:
2206e098bc96SEvan Quan pr_err("Invalid index for retrieving clock activity\n");
2207e098bc96SEvan Quan return -EINVAL;
2208e098bc96SEvan Quan }
2209e098bc96SEvan Quan
2210e098bc96SEvan Quan return ret;
2211e098bc96SEvan Quan }
2212e098bc96SEvan Quan
vega20_read_sensor(struct pp_hwmgr * hwmgr,int idx,void * value,int * size)2213e098bc96SEvan Quan static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
2214e098bc96SEvan Quan void *value, int *size)
2215e098bc96SEvan Quan {
2216e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2217e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
2218e098bc96SEvan Quan SmuMetrics_t metrics_table;
2219e098bc96SEvan Quan uint32_t val_vid;
2220e098bc96SEvan Quan int ret = 0;
2221e098bc96SEvan Quan
2222e098bc96SEvan Quan switch (idx) {
2223e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_SCLK:
2224e098bc96SEvan Quan ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2225e098bc96SEvan Quan if (ret)
2226e098bc96SEvan Quan return ret;
2227e098bc96SEvan Quan
2228e098bc96SEvan Quan *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
2229e098bc96SEvan Quan *size = 4;
2230e098bc96SEvan Quan break;
2231e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_MCLK:
2232e098bc96SEvan Quan ret = vega20_get_current_clk_freq(hwmgr,
2233e098bc96SEvan Quan PPCLK_UCLK,
2234e098bc96SEvan Quan (uint32_t *)value);
2235e098bc96SEvan Quan if (!ret)
2236e098bc96SEvan Quan *size = 4;
2237e098bc96SEvan Quan break;
2238e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GPU_LOAD:
2239e098bc96SEvan Quan case AMDGPU_PP_SENSOR_MEM_LOAD:
2240e098bc96SEvan Quan ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
2241e098bc96SEvan Quan if (!ret)
2242e098bc96SEvan Quan *size = 4;
2243e098bc96SEvan Quan break;
2244e098bc96SEvan Quan case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2245e098bc96SEvan Quan *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2246e098bc96SEvan Quan *size = 4;
2247e098bc96SEvan Quan break;
2248e098bc96SEvan Quan case AMDGPU_PP_SENSOR_EDGE_TEMP:
2249e098bc96SEvan Quan ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2250e098bc96SEvan Quan if (ret)
2251e098bc96SEvan Quan return ret;
2252e098bc96SEvan Quan
2253e098bc96SEvan Quan *((uint32_t *)value) = metrics_table.TemperatureEdge *
2254e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2255e098bc96SEvan Quan *size = 4;
2256e098bc96SEvan Quan break;
2257e098bc96SEvan Quan case AMDGPU_PP_SENSOR_MEM_TEMP:
2258e098bc96SEvan Quan ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2259e098bc96SEvan Quan if (ret)
2260e098bc96SEvan Quan return ret;
2261e098bc96SEvan Quan
2262e098bc96SEvan Quan *((uint32_t *)value) = metrics_table.TemperatureHBM *
2263e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2264e098bc96SEvan Quan *size = 4;
2265e098bc96SEvan Quan break;
2266e098bc96SEvan Quan case AMDGPU_PP_SENSOR_UVD_POWER:
2267e098bc96SEvan Quan *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2268e098bc96SEvan Quan *size = 4;
2269e098bc96SEvan Quan break;
2270e098bc96SEvan Quan case AMDGPU_PP_SENSOR_VCE_POWER:
2271e098bc96SEvan Quan *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2272e098bc96SEvan Quan *size = 4;
2273e098bc96SEvan Quan break;
22749366c2e8SMario Limonciello case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
227547f1724dSMario Limonciello case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2276e098bc96SEvan Quan *size = 16;
2277765bbbecSMario Limonciello ret = vega20_get_gpu_power(hwmgr, idx, (uint32_t *)value);
2278e098bc96SEvan Quan break;
2279e098bc96SEvan Quan case AMDGPU_PP_SENSOR_VDDGFX:
2280e098bc96SEvan Quan val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2281e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2282e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2283e098bc96SEvan Quan *((uint32_t *)value) =
2284e098bc96SEvan Quan (uint32_t)convert_to_vddc((uint8_t)val_vid);
2285e098bc96SEvan Quan break;
2286e098bc96SEvan Quan case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2287e098bc96SEvan Quan ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2288e098bc96SEvan Quan if (!ret)
2289e098bc96SEvan Quan *size = 8;
2290e098bc96SEvan Quan break;
2291e098bc96SEvan Quan default:
2292e0cd93b7SShirish S ret = -EOPNOTSUPP;
2293e098bc96SEvan Quan break;
2294e098bc96SEvan Quan }
2295e098bc96SEvan Quan return ret;
2296e098bc96SEvan Quan }
2297e098bc96SEvan Quan
vega20_display_clock_voltage_request(struct pp_hwmgr * hwmgr,struct pp_display_clock_request * clock_req)2298e098bc96SEvan Quan static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2299e098bc96SEvan Quan struct pp_display_clock_request *clock_req)
2300e098bc96SEvan Quan {
2301e098bc96SEvan Quan int result = 0;
2302e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2303e098bc96SEvan Quan enum amd_pp_clock_type clk_type = clock_req->clock_type;
2304e098bc96SEvan Quan uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2305e098bc96SEvan Quan PPCLK_e clk_select = 0;
2306e098bc96SEvan Quan uint32_t clk_request = 0;
2307e098bc96SEvan Quan
2308e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2309e098bc96SEvan Quan switch (clk_type) {
2310e098bc96SEvan Quan case amd_pp_dcef_clock:
2311e098bc96SEvan Quan clk_select = PPCLK_DCEFCLK;
2312e098bc96SEvan Quan break;
2313e098bc96SEvan Quan case amd_pp_disp_clock:
2314e098bc96SEvan Quan clk_select = PPCLK_DISPCLK;
2315e098bc96SEvan Quan break;
2316e098bc96SEvan Quan case amd_pp_pixel_clock:
2317e098bc96SEvan Quan clk_select = PPCLK_PIXCLK;
2318e098bc96SEvan Quan break;
2319e098bc96SEvan Quan case amd_pp_phy_clock:
2320e098bc96SEvan Quan clk_select = PPCLK_PHYCLK;
2321e098bc96SEvan Quan break;
2322e098bc96SEvan Quan default:
2323e098bc96SEvan Quan pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2324e098bc96SEvan Quan result = -EINVAL;
2325e098bc96SEvan Quan break;
2326e098bc96SEvan Quan }
2327e098bc96SEvan Quan
2328e098bc96SEvan Quan if (!result) {
2329e098bc96SEvan Quan clk_request = (clk_select << 16) | clk_freq;
2330e098bc96SEvan Quan result = smum_send_msg_to_smc_with_parameter(hwmgr,
2331e098bc96SEvan Quan PPSMC_MSG_SetHardMinByFreq,
2332e098bc96SEvan Quan clk_request,
2333e098bc96SEvan Quan NULL);
2334e098bc96SEvan Quan }
2335e098bc96SEvan Quan }
2336e098bc96SEvan Quan
2337e098bc96SEvan Quan return result;
2338e098bc96SEvan Quan }
2339e098bc96SEvan Quan
vega20_get_performance_level(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,PHM_PerformanceLevelDesignation designation,uint32_t index,PHM_PerformanceLevel * level)2340e098bc96SEvan Quan static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2341e098bc96SEvan Quan PHM_PerformanceLevelDesignation designation, uint32_t index,
2342e098bc96SEvan Quan PHM_PerformanceLevel *level)
2343e098bc96SEvan Quan {
2344e098bc96SEvan Quan return 0;
2345e098bc96SEvan Quan }
2346e098bc96SEvan Quan
vega20_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr * hwmgr)2347e098bc96SEvan Quan static int vega20_notify_smc_display_config_after_ps_adjustment(
2348e098bc96SEvan Quan struct pp_hwmgr *hwmgr)
2349e098bc96SEvan Quan {
2350e098bc96SEvan Quan struct vega20_hwmgr *data =
2351e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2352e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table =
2353e098bc96SEvan Quan &data->dpm_table.mem_table;
2354e098bc96SEvan Quan struct PP_Clocks min_clocks = {0};
2355e098bc96SEvan Quan struct pp_display_clock_request clock_req;
2356e098bc96SEvan Quan int ret = 0;
2357e098bc96SEvan Quan
2358e098bc96SEvan Quan min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2359e098bc96SEvan Quan min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2360e098bc96SEvan Quan min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2361e098bc96SEvan Quan
2362e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2363e098bc96SEvan Quan clock_req.clock_type = amd_pp_dcef_clock;
2364e098bc96SEvan Quan clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2365e098bc96SEvan Quan if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2366e098bc96SEvan Quan if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2367e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2368e098bc96SEvan Quan hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2369e098bc96SEvan Quan min_clocks.dcefClockInSR / 100,
2370e098bc96SEvan Quan NULL)) == 0,
2371e098bc96SEvan Quan "Attempt to set divider for DCEFCLK Failed!",
2372e098bc96SEvan Quan return ret);
2373e098bc96SEvan Quan } else {
2374e098bc96SEvan Quan pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2375e098bc96SEvan Quan }
2376e098bc96SEvan Quan }
2377e098bc96SEvan Quan
2378e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2379e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2380e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2381e098bc96SEvan Quan PPSMC_MSG_SetHardMinByFreq,
2382e098bc96SEvan Quan (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
2383e098bc96SEvan Quan NULL)),
2384e098bc96SEvan Quan "[SetHardMinFreq] Set hard min uclk failed!",
2385e098bc96SEvan Quan return ret);
2386e098bc96SEvan Quan }
2387e098bc96SEvan Quan
2388e098bc96SEvan Quan return 0;
2389e098bc96SEvan Quan }
2390e098bc96SEvan Quan
vega20_force_dpm_highest(struct pp_hwmgr * hwmgr)2391e098bc96SEvan Quan static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2392e098bc96SEvan Quan {
2393e098bc96SEvan Quan struct vega20_hwmgr *data =
2394e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2395e098bc96SEvan Quan uint32_t soft_level;
2396e098bc96SEvan Quan int ret = 0;
2397e098bc96SEvan Quan
2398e098bc96SEvan Quan soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2399e098bc96SEvan Quan
2400e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_min_level =
2401e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_max_level =
2402e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2403e098bc96SEvan Quan
2404e098bc96SEvan Quan soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2405e098bc96SEvan Quan
2406e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_min_level =
2407e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_max_level =
2408e098bc96SEvan Quan data->dpm_table.mem_table.dpm_levels[soft_level].value;
2409e098bc96SEvan Quan
2410e098bc96SEvan Quan soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2411e098bc96SEvan Quan
2412e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_min_level =
2413e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_max_level =
2414e098bc96SEvan Quan data->dpm_table.soc_table.dpm_levels[soft_level].value;
2415e098bc96SEvan Quan
2416e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2417e098bc96SEvan Quan FEATURE_DPM_UCLK_MASK |
2418e098bc96SEvan Quan FEATURE_DPM_SOCCLK_MASK);
2419e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2420e098bc96SEvan Quan "Failed to upload boot level to highest!",
2421e098bc96SEvan Quan return ret);
2422e098bc96SEvan Quan
2423e098bc96SEvan Quan ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2424e098bc96SEvan Quan FEATURE_DPM_UCLK_MASK |
2425e098bc96SEvan Quan FEATURE_DPM_SOCCLK_MASK);
2426e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2427e098bc96SEvan Quan "Failed to upload dpm max level to highest!",
2428e098bc96SEvan Quan return ret);
2429e098bc96SEvan Quan
2430e098bc96SEvan Quan return 0;
2431e098bc96SEvan Quan }
2432e098bc96SEvan Quan
vega20_force_dpm_lowest(struct pp_hwmgr * hwmgr)2433e098bc96SEvan Quan static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2434e098bc96SEvan Quan {
2435e098bc96SEvan Quan struct vega20_hwmgr *data =
2436e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2437e098bc96SEvan Quan uint32_t soft_level;
2438e098bc96SEvan Quan int ret = 0;
2439e098bc96SEvan Quan
2440e098bc96SEvan Quan soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2441e098bc96SEvan Quan
2442e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_min_level =
2443e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_max_level =
2444e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2445e098bc96SEvan Quan
2446e098bc96SEvan Quan soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2447e098bc96SEvan Quan
2448e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_min_level =
2449e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_max_level =
2450e098bc96SEvan Quan data->dpm_table.mem_table.dpm_levels[soft_level].value;
2451e098bc96SEvan Quan
2452e098bc96SEvan Quan soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2453e098bc96SEvan Quan
2454e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_min_level =
2455e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_max_level =
2456e098bc96SEvan Quan data->dpm_table.soc_table.dpm_levels[soft_level].value;
2457e098bc96SEvan Quan
2458e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2459e098bc96SEvan Quan FEATURE_DPM_UCLK_MASK |
2460e098bc96SEvan Quan FEATURE_DPM_SOCCLK_MASK);
2461e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2462e098bc96SEvan Quan "Failed to upload boot level to highest!",
2463e098bc96SEvan Quan return ret);
2464e098bc96SEvan Quan
2465e098bc96SEvan Quan ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2466e098bc96SEvan Quan FEATURE_DPM_UCLK_MASK |
2467e098bc96SEvan Quan FEATURE_DPM_SOCCLK_MASK);
2468e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2469e098bc96SEvan Quan "Failed to upload dpm max level to highest!",
2470e098bc96SEvan Quan return ret);
2471e098bc96SEvan Quan
2472e098bc96SEvan Quan return 0;
2473e098bc96SEvan Quan
2474e098bc96SEvan Quan }
2475e098bc96SEvan Quan
vega20_unforce_dpm_levels(struct pp_hwmgr * hwmgr)2476e098bc96SEvan Quan static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2477e098bc96SEvan Quan {
2478e098bc96SEvan Quan struct vega20_hwmgr *data =
2479e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2480e098bc96SEvan Quan uint32_t soft_min_level, soft_max_level;
2481e098bc96SEvan Quan int ret = 0;
2482e098bc96SEvan Quan
2483e098bc96SEvan Quan /* gfxclk soft min/max settings */
2484e098bc96SEvan Quan soft_min_level =
2485e098bc96SEvan Quan vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2486e098bc96SEvan Quan soft_max_level =
2487e098bc96SEvan Quan vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2488e098bc96SEvan Quan
2489e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_min_level =
2490e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2491e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_max_level =
2492e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2493e098bc96SEvan Quan
2494e098bc96SEvan Quan /* uclk soft min/max settings */
2495e098bc96SEvan Quan soft_min_level =
2496e098bc96SEvan Quan vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2497e098bc96SEvan Quan soft_max_level =
2498e098bc96SEvan Quan vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2499e098bc96SEvan Quan
2500e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_min_level =
2501e098bc96SEvan Quan data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2502e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_max_level =
2503e098bc96SEvan Quan data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2504e098bc96SEvan Quan
2505e098bc96SEvan Quan /* socclk soft min/max settings */
2506e098bc96SEvan Quan soft_min_level =
2507e098bc96SEvan Quan vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2508e098bc96SEvan Quan soft_max_level =
2509e098bc96SEvan Quan vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2510e098bc96SEvan Quan
2511e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_min_level =
2512e098bc96SEvan Quan data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2513e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_max_level =
2514e098bc96SEvan Quan data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2515e098bc96SEvan Quan
2516e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2517e098bc96SEvan Quan FEATURE_DPM_UCLK_MASK |
2518e098bc96SEvan Quan FEATURE_DPM_SOCCLK_MASK);
2519e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2520e098bc96SEvan Quan "Failed to upload DPM Bootup Levels!",
2521e098bc96SEvan Quan return ret);
2522e098bc96SEvan Quan
2523e098bc96SEvan Quan ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2524e098bc96SEvan Quan FEATURE_DPM_UCLK_MASK |
2525e098bc96SEvan Quan FEATURE_DPM_SOCCLK_MASK);
2526e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2527e098bc96SEvan Quan "Failed to upload DPM Max Levels!",
2528e098bc96SEvan Quan return ret);
2529e098bc96SEvan Quan
2530e098bc96SEvan Quan return 0;
2531e098bc96SEvan Quan }
2532e098bc96SEvan Quan
vega20_get_profiling_clk_mask(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)2533e098bc96SEvan Quan static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2534e098bc96SEvan Quan uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2535e098bc96SEvan Quan {
2536e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2537e098bc96SEvan Quan struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2538e098bc96SEvan Quan struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2539e098bc96SEvan Quan struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2540e098bc96SEvan Quan
2541e098bc96SEvan Quan *sclk_mask = 0;
2542e098bc96SEvan Quan *mclk_mask = 0;
2543e098bc96SEvan Quan *soc_mask = 0;
2544e098bc96SEvan Quan
2545e098bc96SEvan Quan if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2546e098bc96SEvan Quan mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2547e098bc96SEvan Quan soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2548e098bc96SEvan Quan *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2549e098bc96SEvan Quan *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2550e098bc96SEvan Quan *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2551e098bc96SEvan Quan }
2552e098bc96SEvan Quan
2553e098bc96SEvan Quan if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2554e098bc96SEvan Quan *sclk_mask = 0;
2555e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2556e098bc96SEvan Quan *mclk_mask = 0;
2557e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2558e098bc96SEvan Quan *sclk_mask = gfx_dpm_table->count - 1;
2559e098bc96SEvan Quan *mclk_mask = mem_dpm_table->count - 1;
2560e098bc96SEvan Quan *soc_mask = soc_dpm_table->count - 1;
2561e098bc96SEvan Quan }
2562e098bc96SEvan Quan
2563e098bc96SEvan Quan return 0;
2564e098bc96SEvan Quan }
2565e098bc96SEvan Quan
vega20_force_clock_level(struct pp_hwmgr * hwmgr,enum pp_clock_type type,uint32_t mask)2566e098bc96SEvan Quan static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2567e098bc96SEvan Quan enum pp_clock_type type, uint32_t mask)
2568e098bc96SEvan Quan {
2569e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2570e098bc96SEvan Quan uint32_t soft_min_level, soft_max_level, hard_min_level;
2571e098bc96SEvan Quan int ret = 0;
2572e098bc96SEvan Quan
2573e098bc96SEvan Quan switch (type) {
2574e098bc96SEvan Quan case PP_SCLK:
2575e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0;
2576e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0;
2577e098bc96SEvan Quan
2578e098bc96SEvan Quan if (soft_max_level >= data->dpm_table.gfx_table.count) {
2579e098bc96SEvan Quan pr_err("Clock level specified %d is over max allowed %d\n",
2580e098bc96SEvan Quan soft_max_level,
2581e098bc96SEvan Quan data->dpm_table.gfx_table.count - 1);
2582e098bc96SEvan Quan return -EINVAL;
2583e098bc96SEvan Quan }
2584e098bc96SEvan Quan
2585e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_min_level =
2586e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2587e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_state.soft_max_level =
2588e098bc96SEvan Quan data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2589e098bc96SEvan Quan
2590e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2591e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2592e098bc96SEvan Quan "Failed to upload boot level to lowest!",
2593e098bc96SEvan Quan return ret);
2594e098bc96SEvan Quan
2595e098bc96SEvan Quan ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2596e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2597e098bc96SEvan Quan "Failed to upload dpm max level to highest!",
2598e098bc96SEvan Quan return ret);
2599e098bc96SEvan Quan break;
2600e098bc96SEvan Quan
2601e098bc96SEvan Quan case PP_MCLK:
2602e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0;
2603e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0;
2604e098bc96SEvan Quan
2605e098bc96SEvan Quan if (soft_max_level >= data->dpm_table.mem_table.count) {
2606e098bc96SEvan Quan pr_err("Clock level specified %d is over max allowed %d\n",
2607e098bc96SEvan Quan soft_max_level,
2608e098bc96SEvan Quan data->dpm_table.mem_table.count - 1);
2609e098bc96SEvan Quan return -EINVAL;
2610e098bc96SEvan Quan }
2611e098bc96SEvan Quan
2612e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_min_level =
2613e098bc96SEvan Quan data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2614e098bc96SEvan Quan data->dpm_table.mem_table.dpm_state.soft_max_level =
2615e098bc96SEvan Quan data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2616e098bc96SEvan Quan
2617e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2618e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2619e098bc96SEvan Quan "Failed to upload boot level to lowest!",
2620e098bc96SEvan Quan return ret);
2621e098bc96SEvan Quan
2622e098bc96SEvan Quan ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2623e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2624e098bc96SEvan Quan "Failed to upload dpm max level to highest!",
2625e098bc96SEvan Quan return ret);
2626e098bc96SEvan Quan
2627e098bc96SEvan Quan break;
2628e098bc96SEvan Quan
2629e098bc96SEvan Quan case PP_SOCCLK:
2630e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0;
2631e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0;
2632e098bc96SEvan Quan
2633e098bc96SEvan Quan if (soft_max_level >= data->dpm_table.soc_table.count) {
2634e098bc96SEvan Quan pr_err("Clock level specified %d is over max allowed %d\n",
2635e098bc96SEvan Quan soft_max_level,
2636e098bc96SEvan Quan data->dpm_table.soc_table.count - 1);
2637e098bc96SEvan Quan return -EINVAL;
2638e098bc96SEvan Quan }
2639e098bc96SEvan Quan
2640e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_min_level =
2641e098bc96SEvan Quan data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2642e098bc96SEvan Quan data->dpm_table.soc_table.dpm_state.soft_max_level =
2643e098bc96SEvan Quan data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2644e098bc96SEvan Quan
2645e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2646e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2647e098bc96SEvan Quan "Failed to upload boot level to lowest!",
2648e098bc96SEvan Quan return ret);
2649e098bc96SEvan Quan
2650e098bc96SEvan Quan ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2651e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2652e098bc96SEvan Quan "Failed to upload dpm max level to highest!",
2653e098bc96SEvan Quan return ret);
2654e098bc96SEvan Quan
2655e098bc96SEvan Quan break;
2656e098bc96SEvan Quan
2657e098bc96SEvan Quan case PP_FCLK:
2658e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0;
2659e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0;
2660e098bc96SEvan Quan
2661e098bc96SEvan Quan if (soft_max_level >= data->dpm_table.fclk_table.count) {
2662e098bc96SEvan Quan pr_err("Clock level specified %d is over max allowed %d\n",
2663e098bc96SEvan Quan soft_max_level,
2664e098bc96SEvan Quan data->dpm_table.fclk_table.count - 1);
2665e098bc96SEvan Quan return -EINVAL;
2666e098bc96SEvan Quan }
2667e098bc96SEvan Quan
2668e098bc96SEvan Quan data->dpm_table.fclk_table.dpm_state.soft_min_level =
2669e098bc96SEvan Quan data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
2670e098bc96SEvan Quan data->dpm_table.fclk_table.dpm_state.soft_max_level =
2671e098bc96SEvan Quan data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
2672e098bc96SEvan Quan
2673e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2674e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2675e098bc96SEvan Quan "Failed to upload boot level to lowest!",
2676e098bc96SEvan Quan return ret);
2677e098bc96SEvan Quan
2678e098bc96SEvan Quan ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2679e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2680e098bc96SEvan Quan "Failed to upload dpm max level to highest!",
2681e098bc96SEvan Quan return ret);
2682e098bc96SEvan Quan
2683e098bc96SEvan Quan break;
2684e098bc96SEvan Quan
2685e098bc96SEvan Quan case PP_DCEFCLK:
2686e098bc96SEvan Quan hard_min_level = mask ? (ffs(mask) - 1) : 0;
2687e098bc96SEvan Quan
2688e098bc96SEvan Quan if (hard_min_level >= data->dpm_table.dcef_table.count) {
2689e098bc96SEvan Quan pr_err("Clock level specified %d is over max allowed %d\n",
2690e098bc96SEvan Quan hard_min_level,
2691e098bc96SEvan Quan data->dpm_table.dcef_table.count - 1);
2692e098bc96SEvan Quan return -EINVAL;
2693e098bc96SEvan Quan }
2694e098bc96SEvan Quan
2695e098bc96SEvan Quan data->dpm_table.dcef_table.dpm_state.hard_min_level =
2696e098bc96SEvan Quan data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2697e098bc96SEvan Quan
2698e098bc96SEvan Quan ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
2699e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2700e098bc96SEvan Quan "Failed to upload boot level to lowest!",
2701e098bc96SEvan Quan return ret);
2702e098bc96SEvan Quan
2703e098bc96SEvan Quan //TODO: Setting DCEFCLK max dpm level is not supported
2704e098bc96SEvan Quan
2705e098bc96SEvan Quan break;
2706e098bc96SEvan Quan
2707e098bc96SEvan Quan case PP_PCIE:
2708e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0;
2709e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0;
2710e098bc96SEvan Quan if (soft_min_level >= NUM_LINK_LEVELS ||
2711e098bc96SEvan Quan soft_max_level >= NUM_LINK_LEVELS)
2712e098bc96SEvan Quan return -EINVAL;
2713e098bc96SEvan Quan
2714e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2715e098bc96SEvan Quan PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level,
2716e098bc96SEvan Quan NULL);
2717e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
2718e098bc96SEvan Quan "Failed to set min link dpm level!",
2719e098bc96SEvan Quan return ret);
2720e098bc96SEvan Quan
2721e098bc96SEvan Quan break;
2722e098bc96SEvan Quan
2723e098bc96SEvan Quan default:
2724e098bc96SEvan Quan break;
2725e098bc96SEvan Quan }
2726e098bc96SEvan Quan
2727e098bc96SEvan Quan return 0;
2728e098bc96SEvan Quan }
2729e098bc96SEvan Quan
vega20_dpm_force_dpm_level(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level)2730e098bc96SEvan Quan static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2731e098bc96SEvan Quan enum amd_dpm_forced_level level)
2732e098bc96SEvan Quan {
2733e098bc96SEvan Quan int ret = 0;
2734e098bc96SEvan Quan uint32_t sclk_mask, mclk_mask, soc_mask;
2735e098bc96SEvan Quan
2736e098bc96SEvan Quan switch (level) {
2737e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_HIGH:
2738e098bc96SEvan Quan ret = vega20_force_dpm_highest(hwmgr);
2739e098bc96SEvan Quan break;
2740e098bc96SEvan Quan
2741e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_LOW:
2742e098bc96SEvan Quan ret = vega20_force_dpm_lowest(hwmgr);
2743e098bc96SEvan Quan break;
2744e098bc96SEvan Quan
2745e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_AUTO:
2746e098bc96SEvan Quan ret = vega20_unforce_dpm_levels(hwmgr);
2747e098bc96SEvan Quan break;
2748e098bc96SEvan Quan
2749e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2750e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2751e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2752e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2753e098bc96SEvan Quan ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2754e098bc96SEvan Quan if (ret)
2755e098bc96SEvan Quan return ret;
2756e098bc96SEvan Quan vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2757e098bc96SEvan Quan vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2758e098bc96SEvan Quan vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2759e098bc96SEvan Quan break;
2760e098bc96SEvan Quan
2761e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_MANUAL:
2762e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2763e098bc96SEvan Quan default:
2764e098bc96SEvan Quan break;
2765e098bc96SEvan Quan }
2766e098bc96SEvan Quan
2767e098bc96SEvan Quan return ret;
2768e098bc96SEvan Quan }
2769e098bc96SEvan Quan
vega20_get_fan_control_mode(struct pp_hwmgr * hwmgr)2770e098bc96SEvan Quan static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2771e098bc96SEvan Quan {
2772e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2773e098bc96SEvan Quan
2774e098bc96SEvan Quan if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2775e098bc96SEvan Quan return AMD_FAN_CTRL_MANUAL;
2776e098bc96SEvan Quan else
2777e098bc96SEvan Quan return AMD_FAN_CTRL_AUTO;
2778e098bc96SEvan Quan }
2779e098bc96SEvan Quan
vega20_set_fan_control_mode(struct pp_hwmgr * hwmgr,uint32_t mode)2780e098bc96SEvan Quan static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2781e098bc96SEvan Quan {
2782e098bc96SEvan Quan switch (mode) {
2783e098bc96SEvan Quan case AMD_FAN_CTRL_NONE:
27840d8318e1SEvan Quan vega20_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
2785e098bc96SEvan Quan break;
2786e098bc96SEvan Quan case AMD_FAN_CTRL_MANUAL:
2787e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2788e098bc96SEvan Quan vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2789e098bc96SEvan Quan break;
2790e098bc96SEvan Quan case AMD_FAN_CTRL_AUTO:
2791e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2792e098bc96SEvan Quan vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2793e098bc96SEvan Quan break;
2794e098bc96SEvan Quan default:
2795e098bc96SEvan Quan break;
2796e098bc96SEvan Quan }
2797e098bc96SEvan Quan }
2798e098bc96SEvan Quan
vega20_get_dal_power_level(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * info)2799e098bc96SEvan Quan static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2800e098bc96SEvan Quan struct amd_pp_simple_clock_info *info)
2801e098bc96SEvan Quan {
2802e098bc96SEvan Quan #if 0
2803e098bc96SEvan Quan struct phm_ppt_v2_information *table_info =
2804e098bc96SEvan Quan (struct phm_ppt_v2_information *)hwmgr->pptable;
2805e098bc96SEvan Quan struct phm_clock_and_voltage_limits *max_limits =
2806e098bc96SEvan Quan &table_info->max_clock_voltage_on_ac;
2807e098bc96SEvan Quan
2808e098bc96SEvan Quan info->engine_max_clock = max_limits->sclk;
2809e098bc96SEvan Quan info->memory_max_clock = max_limits->mclk;
2810e098bc96SEvan Quan #endif
2811e098bc96SEvan Quan return 0;
2812e098bc96SEvan Quan }
2813e098bc96SEvan Quan
2814e098bc96SEvan Quan
vega20_get_sclks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2815e098bc96SEvan Quan static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2816e098bc96SEvan Quan struct pp_clock_levels_with_latency *clocks)
2817e098bc96SEvan Quan {
2818e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2819e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2820e098bc96SEvan Quan int i, count;
2821e098bc96SEvan Quan
2822e098bc96SEvan Quan if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
2823e098bc96SEvan Quan return -1;
2824e098bc96SEvan Quan
2825e098bc96SEvan Quan count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2826e098bc96SEvan Quan clocks->num_levels = count;
2827e098bc96SEvan Quan
2828e098bc96SEvan Quan for (i = 0; i < count; i++) {
2829e098bc96SEvan Quan clocks->data[i].clocks_in_khz =
2830e098bc96SEvan Quan dpm_table->dpm_levels[i].value * 1000;
2831e098bc96SEvan Quan clocks->data[i].latency_in_us = 0;
2832e098bc96SEvan Quan }
2833e098bc96SEvan Quan
2834e098bc96SEvan Quan return 0;
2835e098bc96SEvan Quan }
2836e098bc96SEvan Quan
vega20_get_mem_latency(struct pp_hwmgr * hwmgr,uint32_t clock)2837e098bc96SEvan Quan static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2838e098bc96SEvan Quan uint32_t clock)
2839e098bc96SEvan Quan {
2840e098bc96SEvan Quan return 25;
2841e098bc96SEvan Quan }
2842e098bc96SEvan Quan
vega20_get_memclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2843e098bc96SEvan Quan static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2844e098bc96SEvan Quan struct pp_clock_levels_with_latency *clocks)
2845e098bc96SEvan Quan {
2846e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2847e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2848e098bc96SEvan Quan int i, count;
2849e098bc96SEvan Quan
2850e098bc96SEvan Quan if (!data->smu_features[GNLD_DPM_UCLK].enabled)
2851e098bc96SEvan Quan return -1;
2852e098bc96SEvan Quan
2853e098bc96SEvan Quan count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2854e098bc96SEvan Quan clocks->num_levels = data->mclk_latency_table.count = count;
2855e098bc96SEvan Quan
2856e098bc96SEvan Quan for (i = 0; i < count; i++) {
2857e098bc96SEvan Quan clocks->data[i].clocks_in_khz =
2858e098bc96SEvan Quan data->mclk_latency_table.entries[i].frequency =
2859e098bc96SEvan Quan dpm_table->dpm_levels[i].value * 1000;
2860e098bc96SEvan Quan clocks->data[i].latency_in_us =
2861e098bc96SEvan Quan data->mclk_latency_table.entries[i].latency =
2862e098bc96SEvan Quan vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2863e098bc96SEvan Quan }
2864e098bc96SEvan Quan
2865e098bc96SEvan Quan return 0;
2866e098bc96SEvan Quan }
2867e098bc96SEvan Quan
vega20_get_dcefclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2868e098bc96SEvan Quan static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2869e098bc96SEvan Quan struct pp_clock_levels_with_latency *clocks)
2870e098bc96SEvan Quan {
2871e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2872e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2873e098bc96SEvan Quan int i, count;
2874e098bc96SEvan Quan
2875e098bc96SEvan Quan if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
2876e098bc96SEvan Quan return -1;
2877e098bc96SEvan Quan
2878e098bc96SEvan Quan count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2879e098bc96SEvan Quan clocks->num_levels = count;
2880e098bc96SEvan Quan
2881e098bc96SEvan Quan for (i = 0; i < count; i++) {
2882e098bc96SEvan Quan clocks->data[i].clocks_in_khz =
2883e098bc96SEvan Quan dpm_table->dpm_levels[i].value * 1000;
2884e098bc96SEvan Quan clocks->data[i].latency_in_us = 0;
2885e098bc96SEvan Quan }
2886e098bc96SEvan Quan
2887e098bc96SEvan Quan return 0;
2888e098bc96SEvan Quan }
2889e098bc96SEvan Quan
vega20_get_socclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2890e098bc96SEvan Quan static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2891e098bc96SEvan Quan struct pp_clock_levels_with_latency *clocks)
2892e098bc96SEvan Quan {
2893e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2894e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2895e098bc96SEvan Quan int i, count;
2896e098bc96SEvan Quan
2897e098bc96SEvan Quan if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
2898e098bc96SEvan Quan return -1;
2899e098bc96SEvan Quan
2900e098bc96SEvan Quan count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2901e098bc96SEvan Quan clocks->num_levels = count;
2902e098bc96SEvan Quan
2903e098bc96SEvan Quan for (i = 0; i < count; i++) {
2904e098bc96SEvan Quan clocks->data[i].clocks_in_khz =
2905e098bc96SEvan Quan dpm_table->dpm_levels[i].value * 1000;
2906e098bc96SEvan Quan clocks->data[i].latency_in_us = 0;
2907e098bc96SEvan Quan }
2908e098bc96SEvan Quan
2909e098bc96SEvan Quan return 0;
2910e098bc96SEvan Quan
2911e098bc96SEvan Quan }
2912e098bc96SEvan Quan
vega20_get_clock_by_type_with_latency(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)2913e098bc96SEvan Quan static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2914e098bc96SEvan Quan enum amd_pp_clock_type type,
2915e098bc96SEvan Quan struct pp_clock_levels_with_latency *clocks)
2916e098bc96SEvan Quan {
2917e098bc96SEvan Quan int ret;
2918e098bc96SEvan Quan
2919e098bc96SEvan Quan switch (type) {
2920e098bc96SEvan Quan case amd_pp_sys_clock:
2921e098bc96SEvan Quan ret = vega20_get_sclks(hwmgr, clocks);
2922e098bc96SEvan Quan break;
2923e098bc96SEvan Quan case amd_pp_mem_clock:
2924e098bc96SEvan Quan ret = vega20_get_memclocks(hwmgr, clocks);
2925e098bc96SEvan Quan break;
2926e098bc96SEvan Quan case amd_pp_dcef_clock:
2927e098bc96SEvan Quan ret = vega20_get_dcefclocks(hwmgr, clocks);
2928e098bc96SEvan Quan break;
2929e098bc96SEvan Quan case amd_pp_soc_clock:
2930e098bc96SEvan Quan ret = vega20_get_socclocks(hwmgr, clocks);
2931e098bc96SEvan Quan break;
2932e098bc96SEvan Quan default:
2933e098bc96SEvan Quan return -EINVAL;
2934e098bc96SEvan Quan }
2935e098bc96SEvan Quan
2936e098bc96SEvan Quan return ret;
2937e098bc96SEvan Quan }
2938e098bc96SEvan Quan
vega20_get_clock_by_type_with_voltage(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)2939e098bc96SEvan Quan static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2940e098bc96SEvan Quan enum amd_pp_clock_type type,
2941e098bc96SEvan Quan struct pp_clock_levels_with_voltage *clocks)
2942e098bc96SEvan Quan {
2943e098bc96SEvan Quan clocks->num_levels = 0;
2944e098bc96SEvan Quan
2945e098bc96SEvan Quan return 0;
2946e098bc96SEvan Quan }
2947e098bc96SEvan Quan
vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr * hwmgr,void * clock_ranges)2948e098bc96SEvan Quan static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2949e098bc96SEvan Quan void *clock_ranges)
2950e098bc96SEvan Quan {
2951e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2952e098bc96SEvan Quan Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2953e098bc96SEvan Quan struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2954e098bc96SEvan Quan
2955e098bc96SEvan Quan if (!data->registry_data.disable_water_mark &&
2956e098bc96SEvan Quan data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2957e098bc96SEvan Quan data->smu_features[GNLD_DPM_SOCCLK].supported) {
2958e098bc96SEvan Quan smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2959e098bc96SEvan Quan data->water_marks_bitmap |= WaterMarksExist;
2960e098bc96SEvan Quan data->water_marks_bitmap &= ~WaterMarksLoaded;
2961e098bc96SEvan Quan }
2962e098bc96SEvan Quan
2963e098bc96SEvan Quan return 0;
2964e098bc96SEvan Quan }
2965e098bc96SEvan Quan
vega20_odn_edit_dpm_table(struct pp_hwmgr * hwmgr,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)2966e098bc96SEvan Quan static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2967e098bc96SEvan Quan enum PP_OD_DPM_TABLE_COMMAND type,
2968e098bc96SEvan Quan long *input, uint32_t size)
2969e098bc96SEvan Quan {
2970e098bc96SEvan Quan struct vega20_hwmgr *data =
2971e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
2972e098bc96SEvan Quan struct vega20_od8_single_setting *od8_settings =
2973e098bc96SEvan Quan data->od8_settings.od8_settings_array;
2974e098bc96SEvan Quan OverDriveTable_t *od_table =
2975e098bc96SEvan Quan &(data->smc_state_table.overdrive_table);
2976d27252b5SDan Carpenter int32_t input_clk, input_vol, i;
2977d27252b5SDan Carpenter uint32_t input_index;
2978e098bc96SEvan Quan int od8_id;
2979e098bc96SEvan Quan int ret;
2980e098bc96SEvan Quan
2981e098bc96SEvan Quan PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2982e098bc96SEvan Quan return -EINVAL);
2983e098bc96SEvan Quan
2984e098bc96SEvan Quan switch (type) {
2985e098bc96SEvan Quan case PP_OD_EDIT_SCLK_VDDC_TABLE:
2986e098bc96SEvan Quan if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2987e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2988e098bc96SEvan Quan pr_info("Sclk min/max frequency overdrive not supported\n");
2989e098bc96SEvan Quan return -EOPNOTSUPP;
2990e098bc96SEvan Quan }
2991e098bc96SEvan Quan
2992e098bc96SEvan Quan for (i = 0; i < size; i += 2) {
2993e098bc96SEvan Quan if (i + 2 > size) {
2994e098bc96SEvan Quan pr_info("invalid number of input parameters %d\n",
2995e098bc96SEvan Quan size);
2996e098bc96SEvan Quan return -EINVAL;
2997e098bc96SEvan Quan }
2998e098bc96SEvan Quan
2999e098bc96SEvan Quan input_index = input[i];
3000e098bc96SEvan Quan input_clk = input[i + 1];
3001e098bc96SEvan Quan
3002e098bc96SEvan Quan if (input_index != 0 && input_index != 1) {
3003e098bc96SEvan Quan pr_info("Invalid index %d\n", input_index);
3004e098bc96SEvan Quan pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
3005e098bc96SEvan Quan return -EINVAL;
3006e098bc96SEvan Quan }
3007e098bc96SEvan Quan
3008e098bc96SEvan Quan if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
3009e098bc96SEvan Quan input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
3010e098bc96SEvan Quan pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3011e098bc96SEvan Quan input_clk,
3012e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3013e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3014e098bc96SEvan Quan return -EINVAL;
3015e098bc96SEvan Quan }
3016e098bc96SEvan Quan
3017e098bc96SEvan Quan if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
3018e098bc96SEvan Quan (input_index == 1 && od_table->GfxclkFmax != input_clk))
3019e098bc96SEvan Quan data->gfxclk_overdrive = true;
3020e098bc96SEvan Quan
3021e098bc96SEvan Quan if (input_index == 0)
3022e098bc96SEvan Quan od_table->GfxclkFmin = input_clk;
3023e098bc96SEvan Quan else
3024e098bc96SEvan Quan od_table->GfxclkFmax = input_clk;
3025e098bc96SEvan Quan }
3026e098bc96SEvan Quan
3027e098bc96SEvan Quan break;
3028e098bc96SEvan Quan
3029e098bc96SEvan Quan case PP_OD_EDIT_MCLK_VDDC_TABLE:
3030e098bc96SEvan Quan if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3031e098bc96SEvan Quan pr_info("Mclk max frequency overdrive not supported\n");
3032e098bc96SEvan Quan return -EOPNOTSUPP;
3033e098bc96SEvan Quan }
3034e098bc96SEvan Quan
3035e098bc96SEvan Quan for (i = 0; i < size; i += 2) {
3036e098bc96SEvan Quan if (i + 2 > size) {
3037e098bc96SEvan Quan pr_info("invalid number of input parameters %d\n",
3038e098bc96SEvan Quan size);
3039e098bc96SEvan Quan return -EINVAL;
3040e098bc96SEvan Quan }
3041e098bc96SEvan Quan
3042e098bc96SEvan Quan input_index = input[i];
3043e098bc96SEvan Quan input_clk = input[i + 1];
3044e098bc96SEvan Quan
3045e098bc96SEvan Quan if (input_index != 1) {
3046e098bc96SEvan Quan pr_info("Invalid index %d\n", input_index);
3047e098bc96SEvan Quan pr_info("Support max Mclk frequency setting only which index by 1\n");
3048e098bc96SEvan Quan return -EINVAL;
3049e098bc96SEvan Quan }
3050e098bc96SEvan Quan
3051e098bc96SEvan Quan if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
3052e098bc96SEvan Quan input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
3053e098bc96SEvan Quan pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3054e098bc96SEvan Quan input_clk,
3055e098bc96SEvan Quan od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3056e098bc96SEvan Quan od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3057e098bc96SEvan Quan return -EINVAL;
3058e098bc96SEvan Quan }
3059e098bc96SEvan Quan
3060e098bc96SEvan Quan if (input_index == 1 && od_table->UclkFmax != input_clk)
3061e098bc96SEvan Quan data->memclk_overdrive = true;
3062e098bc96SEvan Quan
3063e098bc96SEvan Quan od_table->UclkFmax = input_clk;
3064e098bc96SEvan Quan }
3065e098bc96SEvan Quan
3066e098bc96SEvan Quan break;
3067e098bc96SEvan Quan
3068e098bc96SEvan Quan case PP_OD_EDIT_VDDC_CURVE:
3069e098bc96SEvan Quan if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3070e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3071e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3072e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3073e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3074e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
3075e098bc96SEvan Quan pr_info("Voltage curve calibrate not supported\n");
3076e098bc96SEvan Quan return -EOPNOTSUPP;
3077e098bc96SEvan Quan }
3078e098bc96SEvan Quan
3079e098bc96SEvan Quan for (i = 0; i < size; i += 3) {
3080e098bc96SEvan Quan if (i + 3 > size) {
3081e098bc96SEvan Quan pr_info("invalid number of input parameters %d\n",
3082e098bc96SEvan Quan size);
3083e098bc96SEvan Quan return -EINVAL;
3084e098bc96SEvan Quan }
3085e098bc96SEvan Quan
3086e098bc96SEvan Quan input_index = input[i];
3087e098bc96SEvan Quan input_clk = input[i + 1];
3088e098bc96SEvan Quan input_vol = input[i + 2];
3089e098bc96SEvan Quan
3090e098bc96SEvan Quan if (input_index > 2) {
3091e098bc96SEvan Quan pr_info("Setting for point %d is not supported\n",
3092e098bc96SEvan Quan input_index + 1);
3093e098bc96SEvan Quan pr_info("Three supported points index by 0, 1, 2\n");
3094e098bc96SEvan Quan return -EINVAL;
3095e098bc96SEvan Quan }
3096e098bc96SEvan Quan
3097e098bc96SEvan Quan od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
3098e098bc96SEvan Quan if (input_clk < od8_settings[od8_id].min_value ||
3099e098bc96SEvan Quan input_clk > od8_settings[od8_id].max_value) {
3100e098bc96SEvan Quan pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3101e098bc96SEvan Quan input_clk,
3102e098bc96SEvan Quan od8_settings[od8_id].min_value,
3103e098bc96SEvan Quan od8_settings[od8_id].max_value);
3104e098bc96SEvan Quan return -EINVAL;
3105e098bc96SEvan Quan }
3106e098bc96SEvan Quan
3107e098bc96SEvan Quan od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
3108e098bc96SEvan Quan if (input_vol < od8_settings[od8_id].min_value ||
3109e098bc96SEvan Quan input_vol > od8_settings[od8_id].max_value) {
3110e098bc96SEvan Quan pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
3111e098bc96SEvan Quan input_vol,
3112e098bc96SEvan Quan od8_settings[od8_id].min_value,
3113e098bc96SEvan Quan od8_settings[od8_id].max_value);
3114e098bc96SEvan Quan return -EINVAL;
3115e098bc96SEvan Quan }
3116e098bc96SEvan Quan
3117e098bc96SEvan Quan switch (input_index) {
3118e098bc96SEvan Quan case 0:
3119e098bc96SEvan Quan od_table->GfxclkFreq1 = input_clk;
3120e098bc96SEvan Quan od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
3121e098bc96SEvan Quan break;
3122e098bc96SEvan Quan case 1:
3123e098bc96SEvan Quan od_table->GfxclkFreq2 = input_clk;
3124e098bc96SEvan Quan od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
3125e098bc96SEvan Quan break;
3126e098bc96SEvan Quan case 2:
3127e098bc96SEvan Quan od_table->GfxclkFreq3 = input_clk;
3128e098bc96SEvan Quan od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
3129e098bc96SEvan Quan break;
3130e098bc96SEvan Quan }
3131e098bc96SEvan Quan }
3132e098bc96SEvan Quan break;
3133e098bc96SEvan Quan
3134e098bc96SEvan Quan case PP_OD_RESTORE_DEFAULT_TABLE:
3135e098bc96SEvan Quan data->gfxclk_overdrive = false;
3136e098bc96SEvan Quan data->memclk_overdrive = false;
3137e098bc96SEvan Quan
3138e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr,
3139e098bc96SEvan Quan (uint8_t *)od_table,
3140e098bc96SEvan Quan TABLE_OVERDRIVE, true);
3141e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3142e098bc96SEvan Quan "Failed to export overdrive table!",
3143e098bc96SEvan Quan return ret);
3144e098bc96SEvan Quan break;
3145e098bc96SEvan Quan
3146e098bc96SEvan Quan case PP_OD_COMMIT_DPM_TABLE:
3147e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr,
3148e098bc96SEvan Quan (uint8_t *)od_table,
3149e098bc96SEvan Quan TABLE_OVERDRIVE, false);
3150e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3151e098bc96SEvan Quan "Failed to import overdrive table!",
3152e098bc96SEvan Quan return ret);
3153e098bc96SEvan Quan
3154e098bc96SEvan Quan /* retrieve updated gfxclk table */
3155e098bc96SEvan Quan if (data->gfxclk_overdrive) {
3156e098bc96SEvan Quan data->gfxclk_overdrive = false;
3157e098bc96SEvan Quan
3158e098bc96SEvan Quan ret = vega20_setup_gfxclk_dpm_table(hwmgr);
3159e098bc96SEvan Quan if (ret)
3160e098bc96SEvan Quan return ret;
3161e098bc96SEvan Quan }
3162e098bc96SEvan Quan
3163e098bc96SEvan Quan /* retrieve updated memclk table */
3164e098bc96SEvan Quan if (data->memclk_overdrive) {
3165e098bc96SEvan Quan data->memclk_overdrive = false;
3166e098bc96SEvan Quan
3167e098bc96SEvan Quan ret = vega20_setup_memclk_dpm_table(hwmgr);
3168e098bc96SEvan Quan if (ret)
3169e098bc96SEvan Quan return ret;
3170e098bc96SEvan Quan }
3171e098bc96SEvan Quan break;
3172e098bc96SEvan Quan
3173e098bc96SEvan Quan default:
3174e098bc96SEvan Quan return -EINVAL;
3175e098bc96SEvan Quan }
3176e098bc96SEvan Quan
3177e098bc96SEvan Quan return 0;
3178e098bc96SEvan Quan }
3179e098bc96SEvan Quan
vega20_set_mp1_state(struct pp_hwmgr * hwmgr,enum pp_mp1_state mp1_state)3180e098bc96SEvan Quan static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr,
3181e098bc96SEvan Quan enum pp_mp1_state mp1_state)
3182e098bc96SEvan Quan {
3183e098bc96SEvan Quan uint16_t msg;
3184e098bc96SEvan Quan int ret;
3185e098bc96SEvan Quan
3186e098bc96SEvan Quan switch (mp1_state) {
3187e098bc96SEvan Quan case PP_MP1_STATE_SHUTDOWN:
3188e098bc96SEvan Quan msg = PPSMC_MSG_PrepareMp1ForShutdown;
3189e098bc96SEvan Quan break;
3190e098bc96SEvan Quan case PP_MP1_STATE_UNLOAD:
3191e098bc96SEvan Quan msg = PPSMC_MSG_PrepareMp1ForUnload;
3192e098bc96SEvan Quan break;
3193e098bc96SEvan Quan case PP_MP1_STATE_RESET:
3194e098bc96SEvan Quan msg = PPSMC_MSG_PrepareMp1ForReset;
3195e098bc96SEvan Quan break;
3196e098bc96SEvan Quan case PP_MP1_STATE_NONE:
3197e098bc96SEvan Quan default:
3198e098bc96SEvan Quan return 0;
3199e098bc96SEvan Quan }
3200e098bc96SEvan Quan
3201e098bc96SEvan Quan PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
3202e098bc96SEvan Quan "[PrepareMp1] Failed!",
3203e098bc96SEvan Quan return ret);
3204e098bc96SEvan Quan
3205e098bc96SEvan Quan return 0;
3206e098bc96SEvan Quan }
3207e098bc96SEvan Quan
vega20_get_ppfeature_status(struct pp_hwmgr * hwmgr,char * buf)3208e098bc96SEvan Quan static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
3209e098bc96SEvan Quan {
3210e098bc96SEvan Quan static const char *ppfeature_name[] = {
3211e098bc96SEvan Quan "DPM_PREFETCHER",
3212e098bc96SEvan Quan "GFXCLK_DPM",
3213e098bc96SEvan Quan "UCLK_DPM",
3214e098bc96SEvan Quan "SOCCLK_DPM",
3215e098bc96SEvan Quan "UVD_DPM",
3216e098bc96SEvan Quan "VCE_DPM",
3217e098bc96SEvan Quan "ULV",
3218e098bc96SEvan Quan "MP0CLK_DPM",
3219e098bc96SEvan Quan "LINK_DPM",
3220e098bc96SEvan Quan "DCEFCLK_DPM",
3221e098bc96SEvan Quan "GFXCLK_DS",
3222e098bc96SEvan Quan "SOCCLK_DS",
3223e098bc96SEvan Quan "LCLK_DS",
3224e098bc96SEvan Quan "PPT",
3225e098bc96SEvan Quan "TDC",
3226e098bc96SEvan Quan "THERMAL",
3227e098bc96SEvan Quan "GFX_PER_CU_CG",
3228e098bc96SEvan Quan "RM",
3229e098bc96SEvan Quan "DCEFCLK_DS",
3230e098bc96SEvan Quan "ACDC",
3231e098bc96SEvan Quan "VR0HOT",
3232e098bc96SEvan Quan "VR1HOT",
3233e098bc96SEvan Quan "FW_CTF",
3234e098bc96SEvan Quan "LED_DISPLAY",
3235e098bc96SEvan Quan "FAN_CONTROL",
3236e098bc96SEvan Quan "GFX_EDC",
3237e098bc96SEvan Quan "GFXOFF",
3238e098bc96SEvan Quan "CG",
3239e098bc96SEvan Quan "FCLK_DPM",
3240e098bc96SEvan Quan "FCLK_DS",
3241e098bc96SEvan Quan "MP1CLK_DS",
3242e098bc96SEvan Quan "MP0CLK_DS",
3243e098bc96SEvan Quan "XGMI",
3244e098bc96SEvan Quan "ECC"};
3245e098bc96SEvan Quan static const char *output_title[] = {
3246e098bc96SEvan Quan "FEATURES",
3247e098bc96SEvan Quan "BITMASK",
3248e098bc96SEvan Quan "ENABLEMENT"};
3249e098bc96SEvan Quan uint64_t features_enabled;
3250e098bc96SEvan Quan int i;
3251e098bc96SEvan Quan int ret = 0;
3252e098bc96SEvan Quan int size = 0;
3253e098bc96SEvan Quan
3254e9c76719SAlex Deucher phm_get_sysfs_buf(&buf, &size);
3255e9c76719SAlex Deucher
3256e098bc96SEvan Quan ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3257e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3258e098bc96SEvan Quan "[EnableAllSmuFeatures] Failed to get enabled smc features!",
3259e098bc96SEvan Quan return ret);
3260e098bc96SEvan Quan
32610b023410SDarren Powell size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
32620b023410SDarren Powell size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
3263e098bc96SEvan Quan output_title[0],
3264e098bc96SEvan Quan output_title[1],
3265e098bc96SEvan Quan output_title[2]);
3266e098bc96SEvan Quan for (i = 0; i < GNLD_FEATURES_MAX; i++) {
32670b023410SDarren Powell size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
3268e098bc96SEvan Quan ppfeature_name[i],
3269e098bc96SEvan Quan 1ULL << i,
3270e098bc96SEvan Quan (features_enabled & (1ULL << i)) ? "Y" : "N");
3271e098bc96SEvan Quan }
3272e098bc96SEvan Quan
3273e098bc96SEvan Quan return size;
3274e098bc96SEvan Quan }
3275e098bc96SEvan Quan
vega20_set_ppfeature_status(struct pp_hwmgr * hwmgr,uint64_t new_ppfeature_masks)3276e098bc96SEvan Quan static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3277e098bc96SEvan Quan {
3278e098bc96SEvan Quan struct vega20_hwmgr *data =
3279e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
3280e098bc96SEvan Quan uint64_t features_enabled, features_to_enable, features_to_disable;
3281e098bc96SEvan Quan int i, ret = 0;
3282e098bc96SEvan Quan bool enabled;
3283e098bc96SEvan Quan
3284e098bc96SEvan Quan if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3285e098bc96SEvan Quan return -EINVAL;
3286e098bc96SEvan Quan
3287e098bc96SEvan Quan ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3288e098bc96SEvan Quan if (ret)
3289e098bc96SEvan Quan return ret;
3290e098bc96SEvan Quan
3291e098bc96SEvan Quan features_to_disable =
3292e098bc96SEvan Quan features_enabled & ~new_ppfeature_masks;
3293e098bc96SEvan Quan features_to_enable =
3294e098bc96SEvan Quan ~features_enabled & new_ppfeature_masks;
3295e098bc96SEvan Quan
3296e098bc96SEvan Quan pr_debug("features_to_disable 0x%llx\n", features_to_disable);
3297e098bc96SEvan Quan pr_debug("features_to_enable 0x%llx\n", features_to_enable);
3298e098bc96SEvan Quan
3299e098bc96SEvan Quan if (features_to_disable) {
3300e098bc96SEvan Quan ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
3301e098bc96SEvan Quan if (ret)
3302e098bc96SEvan Quan return ret;
3303e098bc96SEvan Quan }
3304e098bc96SEvan Quan
3305e098bc96SEvan Quan if (features_to_enable) {
3306e098bc96SEvan Quan ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
3307e098bc96SEvan Quan if (ret)
3308e098bc96SEvan Quan return ret;
3309e098bc96SEvan Quan }
3310e098bc96SEvan Quan
3311e098bc96SEvan Quan /* Update the cached feature enablement state */
3312e098bc96SEvan Quan ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3313e098bc96SEvan Quan if (ret)
3314e098bc96SEvan Quan return ret;
3315e098bc96SEvan Quan
3316e098bc96SEvan Quan for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3317e098bc96SEvan Quan enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
3318e098bc96SEvan Quan true : false;
3319e098bc96SEvan Quan data->smu_features[i].enabled = enabled;
3320e098bc96SEvan Quan }
3321e098bc96SEvan Quan
3322e098bc96SEvan Quan return 0;
3323e098bc96SEvan Quan }
3324e098bc96SEvan Quan
vega20_get_current_pcie_link_width_level(struct pp_hwmgr * hwmgr)3325e098bc96SEvan Quan static int vega20_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
3326e098bc96SEvan Quan {
3327e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
3328e098bc96SEvan Quan
3329e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
3330e098bc96SEvan Quan PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
3331e098bc96SEvan Quan >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
3332e098bc96SEvan Quan }
3333e098bc96SEvan Quan
vega20_get_current_pcie_link_width(struct pp_hwmgr * hwmgr)3334e098bc96SEvan Quan static int vega20_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
3335e098bc96SEvan Quan {
3336e098bc96SEvan Quan uint32_t width_level;
3337e098bc96SEvan Quan
3338e098bc96SEvan Quan width_level = vega20_get_current_pcie_link_width_level(hwmgr);
3339e098bc96SEvan Quan if (width_level > LINK_WIDTH_MAX)
3340e098bc96SEvan Quan width_level = 0;
3341e098bc96SEvan Quan
3342e098bc96SEvan Quan return link_width[width_level];
3343e098bc96SEvan Quan }
3344e098bc96SEvan Quan
vega20_get_current_pcie_link_speed_level(struct pp_hwmgr * hwmgr)3345e098bc96SEvan Quan static int vega20_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
3346e098bc96SEvan Quan {
3347e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
3348e098bc96SEvan Quan
3349e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3350e098bc96SEvan Quan PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
3351e098bc96SEvan Quan >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
3352e098bc96SEvan Quan }
3353e098bc96SEvan Quan
vega20_get_current_pcie_link_speed(struct pp_hwmgr * hwmgr)3354e098bc96SEvan Quan static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
3355e098bc96SEvan Quan {
3356e098bc96SEvan Quan uint32_t speed_level;
3357e098bc96SEvan Quan
3358e098bc96SEvan Quan speed_level = vega20_get_current_pcie_link_speed_level(hwmgr);
3359e098bc96SEvan Quan if (speed_level > LINK_SPEED_MAX)
3360e098bc96SEvan Quan speed_level = 0;
3361e098bc96SEvan Quan
3362e098bc96SEvan Quan return link_speed[speed_level];
3363e098bc96SEvan Quan }
3364e098bc96SEvan Quan
vega20_print_clock_levels(struct pp_hwmgr * hwmgr,enum pp_clock_type type,char * buf)3365e098bc96SEvan Quan static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
3366e098bc96SEvan Quan enum pp_clock_type type, char *buf)
3367e098bc96SEvan Quan {
3368e098bc96SEvan Quan struct vega20_hwmgr *data =
3369e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
3370e098bc96SEvan Quan struct vega20_od8_single_setting *od8_settings =
3371e098bc96SEvan Quan data->od8_settings.od8_settings_array;
3372e098bc96SEvan Quan OverDriveTable_t *od_table =
3373e098bc96SEvan Quan &(data->smc_state_table.overdrive_table);
3374be6523e3SKenneth Feng PPTable_t *pptable = &(data->smc_state_table.pp_table);
3375e098bc96SEvan Quan struct pp_clock_levels_with_latency clocks;
3376e098bc96SEvan Quan struct vega20_single_dpm_table *fclk_dpm_table =
3377e098bc96SEvan Quan &(data->dpm_table.fclk_table);
3378e098bc96SEvan Quan int i, now, size = 0;
3379e098bc96SEvan Quan int ret = 0;
3380e098bc96SEvan Quan uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
3381e098bc96SEvan Quan
3382e098bc96SEvan Quan switch (type) {
3383e098bc96SEvan Quan case PP_SCLK:
3384e098bc96SEvan Quan ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
3385e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3386e098bc96SEvan Quan "Attempt to get current gfx clk Failed!",
3387e098bc96SEvan Quan return ret);
3388e098bc96SEvan Quan
3389e098bc96SEvan Quan if (vega20_get_sclks(hwmgr, &clocks)) {
3390081664efSAlex Deucher size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3391e098bc96SEvan Quan now / 100);
3392e098bc96SEvan Quan break;
3393e098bc96SEvan Quan }
3394e098bc96SEvan Quan
3395e098bc96SEvan Quan for (i = 0; i < clocks.num_levels; i++)
3396081664efSAlex Deucher size += sprintf(buf + size, "%d: %uMhz %s\n",
3397e098bc96SEvan Quan i, clocks.data[i].clocks_in_khz / 1000,
3398e098bc96SEvan Quan (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3399e098bc96SEvan Quan break;
3400e098bc96SEvan Quan
3401e098bc96SEvan Quan case PP_MCLK:
3402e098bc96SEvan Quan ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
3403e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3404e098bc96SEvan Quan "Attempt to get current mclk freq Failed!",
3405e098bc96SEvan Quan return ret);
3406e098bc96SEvan Quan
3407e098bc96SEvan Quan if (vega20_get_memclocks(hwmgr, &clocks)) {
3408081664efSAlex Deucher size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3409e098bc96SEvan Quan now / 100);
3410e098bc96SEvan Quan break;
3411e098bc96SEvan Quan }
3412e098bc96SEvan Quan
3413e098bc96SEvan Quan for (i = 0; i < clocks.num_levels; i++)
3414081664efSAlex Deucher size += sprintf(buf + size, "%d: %uMhz %s\n",
3415e098bc96SEvan Quan i, clocks.data[i].clocks_in_khz / 1000,
3416e098bc96SEvan Quan (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3417e098bc96SEvan Quan break;
3418e098bc96SEvan Quan
3419e098bc96SEvan Quan case PP_SOCCLK:
3420e098bc96SEvan Quan ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
3421e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3422e098bc96SEvan Quan "Attempt to get current socclk freq Failed!",
3423e098bc96SEvan Quan return ret);
3424e098bc96SEvan Quan
3425e098bc96SEvan Quan if (vega20_get_socclocks(hwmgr, &clocks)) {
3426081664efSAlex Deucher size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3427e098bc96SEvan Quan now / 100);
3428e098bc96SEvan Quan break;
3429e098bc96SEvan Quan }
3430e098bc96SEvan Quan
3431e098bc96SEvan Quan for (i = 0; i < clocks.num_levels; i++)
3432081664efSAlex Deucher size += sprintf(buf + size, "%d: %uMhz %s\n",
3433e098bc96SEvan Quan i, clocks.data[i].clocks_in_khz / 1000,
3434e098bc96SEvan Quan (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3435e098bc96SEvan Quan break;
3436e098bc96SEvan Quan
3437e098bc96SEvan Quan case PP_FCLK:
3438e098bc96SEvan Quan ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
3439e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3440e098bc96SEvan Quan "Attempt to get current fclk freq Failed!",
3441e098bc96SEvan Quan return ret);
3442e098bc96SEvan Quan
3443e098bc96SEvan Quan for (i = 0; i < fclk_dpm_table->count; i++)
3444081664efSAlex Deucher size += sprintf(buf + size, "%d: %uMhz %s\n",
3445e098bc96SEvan Quan i, fclk_dpm_table->dpm_levels[i].value,
3446e098bc96SEvan Quan fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
3447e098bc96SEvan Quan break;
3448e098bc96SEvan Quan
3449e098bc96SEvan Quan case PP_DCEFCLK:
3450e098bc96SEvan Quan ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
3451e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3452e098bc96SEvan Quan "Attempt to get current dcefclk freq Failed!",
3453e098bc96SEvan Quan return ret);
3454e098bc96SEvan Quan
3455e098bc96SEvan Quan if (vega20_get_dcefclocks(hwmgr, &clocks)) {
3456081664efSAlex Deucher size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3457e098bc96SEvan Quan now / 100);
3458e098bc96SEvan Quan break;
3459e098bc96SEvan Quan }
3460e098bc96SEvan Quan
3461e098bc96SEvan Quan for (i = 0; i < clocks.num_levels; i++)
3462081664efSAlex Deucher size += sprintf(buf + size, "%d: %uMhz %s\n",
3463e098bc96SEvan Quan i, clocks.data[i].clocks_in_khz / 1000,
3464e098bc96SEvan Quan (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3465e098bc96SEvan Quan break;
3466e098bc96SEvan Quan
3467e098bc96SEvan Quan case PP_PCIE:
3468e098bc96SEvan Quan current_gen_speed =
3469e098bc96SEvan Quan vega20_get_current_pcie_link_speed_level(hwmgr);
3470e098bc96SEvan Quan current_lane_width =
3471e098bc96SEvan Quan vega20_get_current_pcie_link_width_level(hwmgr);
3472e098bc96SEvan Quan for (i = 0; i < NUM_LINK_LEVELS; i++) {
3473e098bc96SEvan Quan gen_speed = pptable->PcieGenSpeed[i];
3474e098bc96SEvan Quan lane_width = pptable->PcieLaneCount[i];
3475be6523e3SKenneth Feng
3476081664efSAlex Deucher size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
3477e098bc96SEvan Quan (gen_speed == 0) ? "2.5GT/s," :
3478e098bc96SEvan Quan (gen_speed == 1) ? "5.0GT/s," :
3479e098bc96SEvan Quan (gen_speed == 2) ? "8.0GT/s," :
3480e098bc96SEvan Quan (gen_speed == 3) ? "16.0GT/s," : "",
3481e098bc96SEvan Quan (lane_width == 1) ? "x1" :
3482e098bc96SEvan Quan (lane_width == 2) ? "x2" :
3483e098bc96SEvan Quan (lane_width == 3) ? "x4" :
3484e098bc96SEvan Quan (lane_width == 4) ? "x8" :
3485e098bc96SEvan Quan (lane_width == 5) ? "x12" :
3486e098bc96SEvan Quan (lane_width == 6) ? "x16" : "",
3487e098bc96SEvan Quan pptable->LclkFreq[i],
3488e098bc96SEvan Quan (current_gen_speed == gen_speed) &&
3489e098bc96SEvan Quan (current_lane_width == lane_width) ?
3490e098bc96SEvan Quan "*" : "");
3491e098bc96SEvan Quan }
3492e098bc96SEvan Quan break;
3493e098bc96SEvan Quan
3494e098bc96SEvan Quan case OD_SCLK:
3495e098bc96SEvan Quan if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3496e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3497081664efSAlex Deucher size += sprintf(buf + size, "%s:\n", "OD_SCLK");
3498081664efSAlex Deucher size += sprintf(buf + size, "0: %10uMhz\n",
3499e098bc96SEvan Quan od_table->GfxclkFmin);
3500081664efSAlex Deucher size += sprintf(buf + size, "1: %10uMhz\n",
3501e098bc96SEvan Quan od_table->GfxclkFmax);
3502e098bc96SEvan Quan }
3503e098bc96SEvan Quan break;
3504e098bc96SEvan Quan
3505e098bc96SEvan Quan case OD_MCLK:
3506e098bc96SEvan Quan if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3507081664efSAlex Deucher size += sprintf(buf + size, "%s:\n", "OD_MCLK");
3508081664efSAlex Deucher size += sprintf(buf + size, "1: %10uMhz\n",
3509e098bc96SEvan Quan od_table->UclkFmax);
3510e098bc96SEvan Quan }
3511e098bc96SEvan Quan
3512e098bc96SEvan Quan break;
3513e098bc96SEvan Quan
3514e098bc96SEvan Quan case OD_VDDC_CURVE:
3515e098bc96SEvan Quan if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3516e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3517e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3518e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3519e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3520e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3521081664efSAlex Deucher size += sprintf(buf + size, "%s:\n", "OD_VDDC_CURVE");
3522081664efSAlex Deucher size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
3523e098bc96SEvan Quan od_table->GfxclkFreq1,
3524e098bc96SEvan Quan od_table->GfxclkVolt1 / VOLTAGE_SCALE);
3525081664efSAlex Deucher size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
3526e098bc96SEvan Quan od_table->GfxclkFreq2,
3527e098bc96SEvan Quan od_table->GfxclkVolt2 / VOLTAGE_SCALE);
3528081664efSAlex Deucher size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
3529e098bc96SEvan Quan od_table->GfxclkFreq3,
3530e098bc96SEvan Quan od_table->GfxclkVolt3 / VOLTAGE_SCALE);
3531e098bc96SEvan Quan }
3532e098bc96SEvan Quan
3533e098bc96SEvan Quan break;
3534e098bc96SEvan Quan
3535e098bc96SEvan Quan case OD_RANGE:
3536081664efSAlex Deucher size += sprintf(buf + size, "%s:\n", "OD_RANGE");
3537e098bc96SEvan Quan
3538e098bc96SEvan Quan if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3539e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3540081664efSAlex Deucher size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
3541e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3542e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3543e098bc96SEvan Quan }
3544e098bc96SEvan Quan
3545e098bc96SEvan Quan if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3546081664efSAlex Deucher size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
3547e098bc96SEvan Quan od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3548e098bc96SEvan Quan od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3549e098bc96SEvan Quan }
3550e098bc96SEvan Quan
3551e098bc96SEvan Quan if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3552e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3553e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3554e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3555e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3556e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3557081664efSAlex Deucher size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
3558e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
3559e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
3560081664efSAlex Deucher size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
3561e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
3562e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
3563081664efSAlex Deucher size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
3564e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
3565e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
3566081664efSAlex Deucher size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
3567e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
3568e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
3569081664efSAlex Deucher size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
3570e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
3571e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
3572081664efSAlex Deucher size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
3573e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
3574e098bc96SEvan Quan od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
3575e098bc96SEvan Quan }
3576e098bc96SEvan Quan
3577e098bc96SEvan Quan break;
3578e098bc96SEvan Quan default:
3579e098bc96SEvan Quan break;
3580e098bc96SEvan Quan }
3581e098bc96SEvan Quan return size;
3582e098bc96SEvan Quan }
3583e098bc96SEvan Quan
vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr * hwmgr,struct vega20_single_dpm_table * dpm_table)3584e098bc96SEvan Quan static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
3585e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table)
3586e098bc96SEvan Quan {
3587e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3588e098bc96SEvan Quan int ret = 0;
3589e098bc96SEvan Quan
3590e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UCLK].enabled) {
3591e098bc96SEvan Quan PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3592e098bc96SEvan Quan "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
3593e098bc96SEvan Quan return -EINVAL);
3594e098bc96SEvan Quan PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
3595e098bc96SEvan Quan "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
3596e098bc96SEvan Quan return -EINVAL);
3597e098bc96SEvan Quan
3598e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3599e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3600e098bc96SEvan Quan PPSMC_MSG_SetHardMinByFreq,
3601e098bc96SEvan Quan (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
3602e098bc96SEvan Quan NULL)),
3603e098bc96SEvan Quan "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
3604e098bc96SEvan Quan return ret);
3605e098bc96SEvan Quan }
3606e098bc96SEvan Quan
3607e098bc96SEvan Quan return ret;
3608e098bc96SEvan Quan }
3609e098bc96SEvan Quan
vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr * hwmgr)3610e098bc96SEvan Quan static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
3611e098bc96SEvan Quan {
3612e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3613e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table);
3614e098bc96SEvan Quan int ret = 0;
3615e098bc96SEvan Quan
3616e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_FCLK].enabled) {
3617e098bc96SEvan Quan PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3618e098bc96SEvan Quan "[SetFclkToHightestDpmLevel] Dpm table has no entry!",
3619e098bc96SEvan Quan return -EINVAL);
3620e098bc96SEvan Quan PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,
3621e098bc96SEvan Quan "[SetFclkToHightestDpmLevel] Dpm table has too many entries!",
3622e098bc96SEvan Quan return -EINVAL);
3623e098bc96SEvan Quan
3624e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3625e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3626e098bc96SEvan Quan PPSMC_MSG_SetSoftMinByFreq,
3627e098bc96SEvan Quan (PPCLK_FCLK << 16) | dpm_table->dpm_state.soft_min_level,
3628e098bc96SEvan Quan NULL)),
3629e098bc96SEvan Quan "[SetFclkToHightestDpmLevel] Set soft min fclk failed!",
3630e098bc96SEvan Quan return ret);
3631e098bc96SEvan Quan }
3632e098bc96SEvan Quan
3633e098bc96SEvan Quan return ret;
3634e098bc96SEvan Quan }
3635e098bc96SEvan Quan
vega20_pre_display_configuration_changed_task(struct pp_hwmgr * hwmgr)3636e098bc96SEvan Quan static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3637e098bc96SEvan Quan {
3638e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3639e098bc96SEvan Quan int ret = 0;
3640e098bc96SEvan Quan
3641e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
3642e098bc96SEvan Quan PPSMC_MSG_NumOfDisplays, 0, NULL);
3643e098bc96SEvan Quan
3644e098bc96SEvan Quan ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
3645e098bc96SEvan Quan &data->dpm_table.mem_table);
3646e098bc96SEvan Quan if (ret)
3647e098bc96SEvan Quan return ret;
3648e098bc96SEvan Quan
3649e098bc96SEvan Quan return vega20_set_fclk_to_highest_dpm_level(hwmgr);
3650e098bc96SEvan Quan }
3651e098bc96SEvan Quan
vega20_display_configuration_changed_task(struct pp_hwmgr * hwmgr)3652e098bc96SEvan Quan static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3653e098bc96SEvan Quan {
3654e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3655e098bc96SEvan Quan int result = 0;
3656e098bc96SEvan Quan Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
3657e098bc96SEvan Quan
3658e098bc96SEvan Quan if ((data->water_marks_bitmap & WaterMarksExist) &&
3659e098bc96SEvan Quan !(data->water_marks_bitmap & WaterMarksLoaded)) {
3660e098bc96SEvan Quan result = smum_smc_table_manager(hwmgr,
3661e098bc96SEvan Quan (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3662e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
3663e098bc96SEvan Quan "Failed to update WMTABLE!",
3664e098bc96SEvan Quan return result);
3665e098bc96SEvan Quan data->water_marks_bitmap |= WaterMarksLoaded;
3666e098bc96SEvan Quan }
3667e098bc96SEvan Quan
3668e098bc96SEvan Quan if ((data->water_marks_bitmap & WaterMarksExist) &&
3669e098bc96SEvan Quan data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3670e098bc96SEvan Quan data->smu_features[GNLD_DPM_SOCCLK].supported) {
3671e098bc96SEvan Quan result = smum_send_msg_to_smc_with_parameter(hwmgr,
3672e098bc96SEvan Quan PPSMC_MSG_NumOfDisplays,
3673e098bc96SEvan Quan hwmgr->display_config->num_display,
3674e098bc96SEvan Quan NULL);
3675e098bc96SEvan Quan }
3676e098bc96SEvan Quan
3677e098bc96SEvan Quan return result;
3678e098bc96SEvan Quan }
3679e098bc96SEvan Quan
vega20_enable_disable_uvd_dpm(struct pp_hwmgr * hwmgr,bool enable)3680e098bc96SEvan Quan static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3681e098bc96SEvan Quan {
3682e098bc96SEvan Quan struct vega20_hwmgr *data =
3683e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
3684e098bc96SEvan Quan int ret = 0;
3685e098bc96SEvan Quan
3686e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UVD].supported) {
3687e098bc96SEvan Quan if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3688e098bc96SEvan Quan if (enable)
3689e098bc96SEvan Quan PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3690e098bc96SEvan Quan else
3691e098bc96SEvan Quan PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3692e098bc96SEvan Quan }
3693e098bc96SEvan Quan
3694e098bc96SEvan Quan ret = vega20_enable_smc_features(hwmgr,
3695e098bc96SEvan Quan enable,
3696e098bc96SEvan Quan data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3697e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3698e098bc96SEvan Quan "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3699e098bc96SEvan Quan return ret);
3700e098bc96SEvan Quan data->smu_features[GNLD_DPM_UVD].enabled = enable;
3701e098bc96SEvan Quan }
3702e098bc96SEvan Quan
3703e098bc96SEvan Quan return 0;
3704e098bc96SEvan Quan }
3705e098bc96SEvan Quan
vega20_power_gate_vce(struct pp_hwmgr * hwmgr,bool bgate)3706e098bc96SEvan Quan static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3707e098bc96SEvan Quan {
3708e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3709e098bc96SEvan Quan
3710e098bc96SEvan Quan if (data->vce_power_gated == bgate)
3711e098bc96SEvan Quan return ;
3712e098bc96SEvan Quan
3713e098bc96SEvan Quan data->vce_power_gated = bgate;
3714e098bc96SEvan Quan if (bgate) {
3715e098bc96SEvan Quan vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3716e098bc96SEvan Quan amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3717e098bc96SEvan Quan AMD_IP_BLOCK_TYPE_VCE,
3718e098bc96SEvan Quan AMD_PG_STATE_GATE);
3719e098bc96SEvan Quan } else {
3720e098bc96SEvan Quan amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3721e098bc96SEvan Quan AMD_IP_BLOCK_TYPE_VCE,
3722e098bc96SEvan Quan AMD_PG_STATE_UNGATE);
3723e098bc96SEvan Quan vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3724e098bc96SEvan Quan }
3725e098bc96SEvan Quan
3726e098bc96SEvan Quan }
3727e098bc96SEvan Quan
vega20_power_gate_uvd(struct pp_hwmgr * hwmgr,bool bgate)3728e098bc96SEvan Quan static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3729e098bc96SEvan Quan {
3730e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3731e098bc96SEvan Quan
3732e098bc96SEvan Quan if (data->uvd_power_gated == bgate)
3733e098bc96SEvan Quan return ;
3734e098bc96SEvan Quan
3735e098bc96SEvan Quan data->uvd_power_gated = bgate;
3736e098bc96SEvan Quan vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3737e098bc96SEvan Quan }
3738e098bc96SEvan Quan
vega20_apply_clocks_adjust_rules(struct pp_hwmgr * hwmgr)3739e098bc96SEvan Quan static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3740e098bc96SEvan Quan {
3741e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3742e098bc96SEvan Quan struct vega20_single_dpm_table *dpm_table;
3743e098bc96SEvan Quan bool vblank_too_short = false;
3744e098bc96SEvan Quan bool disable_mclk_switching;
3745e098bc96SEvan Quan bool disable_fclk_switching;
3746e098bc96SEvan Quan uint32_t i, latency;
3747e098bc96SEvan Quan
3748e098bc96SEvan Quan disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3749e098bc96SEvan Quan !hwmgr->display_config->multi_monitor_in_sync) ||
3750e098bc96SEvan Quan vblank_too_short;
3751e098bc96SEvan Quan latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3752e098bc96SEvan Quan
3753e098bc96SEvan Quan /* gfxclk */
3754e098bc96SEvan Quan dpm_table = &(data->dpm_table.gfx_table);
3755e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3756e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3757e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3758e098bc96SEvan Quan dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3759e098bc96SEvan Quan
3760e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3761e098bc96SEvan Quan if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3762e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3763e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3764e098bc96SEvan Quan }
3765e098bc96SEvan Quan
3766e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3767e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3768e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3769e098bc96SEvan Quan }
3770e098bc96SEvan Quan
3771e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3772e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3773e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3774e098bc96SEvan Quan }
3775e098bc96SEvan Quan }
3776e098bc96SEvan Quan
3777e098bc96SEvan Quan /* memclk */
3778e098bc96SEvan Quan dpm_table = &(data->dpm_table.mem_table);
3779e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3780e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3781e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3782e098bc96SEvan Quan dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3783e098bc96SEvan Quan
3784e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3785e098bc96SEvan Quan if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3786e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3787e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3788e098bc96SEvan Quan }
3789e098bc96SEvan Quan
3790e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3791e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3792e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3793e098bc96SEvan Quan }
3794e098bc96SEvan Quan
3795e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3796e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3797e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3798e098bc96SEvan Quan }
3799e098bc96SEvan Quan }
3800e098bc96SEvan Quan
3801e098bc96SEvan Quan /* honour DAL's UCLK Hardmin */
3802e098bc96SEvan Quan if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3803e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3804e098bc96SEvan Quan
3805e098bc96SEvan Quan /* Hardmin is dependent on displayconfig */
3806e098bc96SEvan Quan if (disable_mclk_switching) {
3807e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3808e098bc96SEvan Quan for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3809e098bc96SEvan Quan if (data->mclk_latency_table.entries[i].latency <= latency) {
3810e098bc96SEvan Quan if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3811e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3812e098bc96SEvan Quan break;
3813e098bc96SEvan Quan }
3814e098bc96SEvan Quan }
3815e098bc96SEvan Quan }
3816e098bc96SEvan Quan }
3817e098bc96SEvan Quan
3818e098bc96SEvan Quan if (hwmgr->display_config->nb_pstate_switch_disable)
3819e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3820e098bc96SEvan Quan
3821e098bc96SEvan Quan if ((disable_mclk_switching &&
3822e098bc96SEvan Quan (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
3823e098bc96SEvan Quan hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
3824e098bc96SEvan Quan disable_fclk_switching = true;
3825e098bc96SEvan Quan else
3826e098bc96SEvan Quan disable_fclk_switching = false;
3827e098bc96SEvan Quan
3828e098bc96SEvan Quan /* fclk */
3829e098bc96SEvan Quan dpm_table = &(data->dpm_table.fclk_table);
3830e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3831e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3832e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3833e098bc96SEvan Quan dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3834e098bc96SEvan Quan if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
3835e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3836e098bc96SEvan Quan
3837e098bc96SEvan Quan /* vclk */
3838e098bc96SEvan Quan dpm_table = &(data->dpm_table.vclk_table);
3839e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3840e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3841e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3842e098bc96SEvan Quan dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3843e098bc96SEvan Quan
3844e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3845e098bc96SEvan Quan if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3846e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3847e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3848e098bc96SEvan Quan }
3849e098bc96SEvan Quan
3850e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3851e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3852e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3853e098bc96SEvan Quan }
3854e098bc96SEvan Quan }
3855e098bc96SEvan Quan
3856e098bc96SEvan Quan /* dclk */
3857e098bc96SEvan Quan dpm_table = &(data->dpm_table.dclk_table);
3858e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3859e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3860e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3861e098bc96SEvan Quan dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3862e098bc96SEvan Quan
3863e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3864e098bc96SEvan Quan if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3865e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3866e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3867e098bc96SEvan Quan }
3868e098bc96SEvan Quan
3869e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3870e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3871e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3872e098bc96SEvan Quan }
3873e098bc96SEvan Quan }
3874e098bc96SEvan Quan
3875e098bc96SEvan Quan /* socclk */
3876e098bc96SEvan Quan dpm_table = &(data->dpm_table.soc_table);
3877e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3878e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3879e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3880e098bc96SEvan Quan dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3881e098bc96SEvan Quan
3882e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3883e098bc96SEvan Quan if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3884e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3885e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3886e098bc96SEvan Quan }
3887e098bc96SEvan Quan
3888e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3889e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3890e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3891e098bc96SEvan Quan }
3892e098bc96SEvan Quan }
3893e098bc96SEvan Quan
3894e098bc96SEvan Quan /* eclk */
3895e098bc96SEvan Quan dpm_table = &(data->dpm_table.eclk_table);
3896e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3897e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3898e098bc96SEvan Quan dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3899e098bc96SEvan Quan dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3900e098bc96SEvan Quan
3901e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3902e098bc96SEvan Quan if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3903e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3904e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3905e098bc96SEvan Quan }
3906e098bc96SEvan Quan
3907e098bc96SEvan Quan if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3908e098bc96SEvan Quan dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3909e098bc96SEvan Quan dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3910e098bc96SEvan Quan }
3911e098bc96SEvan Quan }
3912e098bc96SEvan Quan
3913e098bc96SEvan Quan return 0;
3914e098bc96SEvan Quan }
3915e098bc96SEvan Quan
3916e098bc96SEvan Quan static bool
vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr * hwmgr)3917e098bc96SEvan Quan vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3918e098bc96SEvan Quan {
3919e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3920e098bc96SEvan Quan bool is_update_required = false;
3921e098bc96SEvan Quan
3922e098bc96SEvan Quan if (data->display_timing.num_existing_displays !=
3923e098bc96SEvan Quan hwmgr->display_config->num_display)
3924e098bc96SEvan Quan is_update_required = true;
3925e098bc96SEvan Quan
3926e098bc96SEvan Quan if (data->registry_data.gfx_clk_deep_sleep_support &&
3927e098bc96SEvan Quan (data->display_timing.min_clock_in_sr !=
3928e098bc96SEvan Quan hwmgr->display_config->min_core_set_clock_in_sr))
3929e098bc96SEvan Quan is_update_required = true;
3930e098bc96SEvan Quan
3931e098bc96SEvan Quan return is_update_required;
3932e098bc96SEvan Quan }
3933e098bc96SEvan Quan
vega20_disable_dpm_tasks(struct pp_hwmgr * hwmgr)3934e098bc96SEvan Quan static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3935e098bc96SEvan Quan {
3936e098bc96SEvan Quan int ret = 0;
3937e098bc96SEvan Quan
3938e098bc96SEvan Quan ret = vega20_disable_all_smu_features(hwmgr);
3939e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!ret,
3940e098bc96SEvan Quan "[DisableDpmTasks] Failed to disable all smu features!",
3941e098bc96SEvan Quan return ret);
3942e098bc96SEvan Quan
3943e098bc96SEvan Quan return 0;
3944e098bc96SEvan Quan }
3945e098bc96SEvan Quan
vega20_power_off_asic(struct pp_hwmgr * hwmgr)3946e098bc96SEvan Quan static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3947e098bc96SEvan Quan {
3948e098bc96SEvan Quan struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3949e098bc96SEvan Quan int result;
3950e098bc96SEvan Quan
3951e098bc96SEvan Quan result = vega20_disable_dpm_tasks(hwmgr);
3952e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 == result),
3953e098bc96SEvan Quan "[PowerOffAsic] Failed to disable DPM!",
3954e098bc96SEvan Quan );
3955e098bc96SEvan Quan data->water_marks_bitmap &= ~(WaterMarksLoaded);
3956e098bc96SEvan Quan
3957e098bc96SEvan Quan return result;
3958e098bc96SEvan Quan }
3959e098bc96SEvan Quan
conv_power_profile_to_pplib_workload(int power_profile)3960e098bc96SEvan Quan static int conv_power_profile_to_pplib_workload(int power_profile)
3961e098bc96SEvan Quan {
3962e098bc96SEvan Quan int pplib_workload = 0;
3963e098bc96SEvan Quan
3964e098bc96SEvan Quan switch (power_profile) {
3965e098bc96SEvan Quan case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
3966e098bc96SEvan Quan pplib_workload = WORKLOAD_DEFAULT_BIT;
3967e098bc96SEvan Quan break;
3968e098bc96SEvan Quan case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3969e098bc96SEvan Quan pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3970e098bc96SEvan Quan break;
3971e098bc96SEvan Quan case PP_SMC_POWER_PROFILE_POWERSAVING:
3972e098bc96SEvan Quan pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3973e098bc96SEvan Quan break;
3974e098bc96SEvan Quan case PP_SMC_POWER_PROFILE_VIDEO:
3975e098bc96SEvan Quan pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3976e098bc96SEvan Quan break;
3977e098bc96SEvan Quan case PP_SMC_POWER_PROFILE_VR:
3978e098bc96SEvan Quan pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3979e098bc96SEvan Quan break;
3980e098bc96SEvan Quan case PP_SMC_POWER_PROFILE_COMPUTE:
3981e098bc96SEvan Quan pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3982e098bc96SEvan Quan break;
3983e098bc96SEvan Quan case PP_SMC_POWER_PROFILE_CUSTOM:
3984e098bc96SEvan Quan pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3985e098bc96SEvan Quan break;
3986e098bc96SEvan Quan }
3987e098bc96SEvan Quan
3988e098bc96SEvan Quan return pplib_workload;
3989e098bc96SEvan Quan }
3990e098bc96SEvan Quan
vega20_get_power_profile_mode(struct pp_hwmgr * hwmgr,char * buf)3991e098bc96SEvan Quan static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3992e098bc96SEvan Quan {
3993e098bc96SEvan Quan DpmActivityMonitorCoeffInt_t activity_monitor;
3994e098bc96SEvan Quan uint32_t i, size = 0;
3995e098bc96SEvan Quan uint16_t workload_type = 0;
3996e098bc96SEvan Quan static const char *title[] = {
3997e098bc96SEvan Quan "PROFILE_INDEX(NAME)",
3998e098bc96SEvan Quan "CLOCK_TYPE(NAME)",
3999e098bc96SEvan Quan "FPS",
4000e098bc96SEvan Quan "UseRlcBusy",
4001e098bc96SEvan Quan "MinActiveFreqType",
4002e098bc96SEvan Quan "MinActiveFreq",
4003e098bc96SEvan Quan "BoosterFreqType",
4004e098bc96SEvan Quan "BoosterFreq",
4005e098bc96SEvan Quan "PD_Data_limit_c",
4006e098bc96SEvan Quan "PD_Data_error_coeff",
4007e098bc96SEvan Quan "PD_Data_error_rate_coeff"};
4008e098bc96SEvan Quan int result = 0;
4009e098bc96SEvan Quan
4010e098bc96SEvan Quan if (!buf)
4011e098bc96SEvan Quan return -EINVAL;
4012e098bc96SEvan Quan
4013e9c76719SAlex Deucher phm_get_sysfs_buf(&buf, &size);
4014e9c76719SAlex Deucher
40150b023410SDarren Powell size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
4016e098bc96SEvan Quan title[0], title[1], title[2], title[3], title[4], title[5],
4017e098bc96SEvan Quan title[6], title[7], title[8], title[9], title[10]);
4018e098bc96SEvan Quan
4019e098bc96SEvan Quan for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
4020e098bc96SEvan Quan /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
4021e098bc96SEvan Quan workload_type = conv_power_profile_to_pplib_workload(i);
4022e098bc96SEvan Quan result = vega20_get_activity_monitor_coeff(hwmgr,
4023e098bc96SEvan Quan (uint8_t *)(&activity_monitor), workload_type);
4024e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
4025e098bc96SEvan Quan "[GetPowerProfile] Failed to get activity monitor!",
4026e098bc96SEvan Quan return result);
4027e098bc96SEvan Quan
40280b023410SDarren Powell size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
402994a80b5bSDarren Powell i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
4030e098bc96SEvan Quan
40310b023410SDarren Powell size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4032e098bc96SEvan Quan " ",
4033e098bc96SEvan Quan 0,
4034e098bc96SEvan Quan "GFXCLK",
4035e098bc96SEvan Quan activity_monitor.Gfx_FPS,
4036e098bc96SEvan Quan activity_monitor.Gfx_UseRlcBusy,
4037e098bc96SEvan Quan activity_monitor.Gfx_MinActiveFreqType,
4038e098bc96SEvan Quan activity_monitor.Gfx_MinActiveFreq,
4039e098bc96SEvan Quan activity_monitor.Gfx_BoosterFreqType,
4040e098bc96SEvan Quan activity_monitor.Gfx_BoosterFreq,
4041e098bc96SEvan Quan activity_monitor.Gfx_PD_Data_limit_c,
4042e098bc96SEvan Quan activity_monitor.Gfx_PD_Data_error_coeff,
4043e098bc96SEvan Quan activity_monitor.Gfx_PD_Data_error_rate_coeff);
4044e098bc96SEvan Quan
40450b023410SDarren Powell size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4046e098bc96SEvan Quan " ",
4047e098bc96SEvan Quan 1,
4048e098bc96SEvan Quan "SOCCLK",
4049e098bc96SEvan Quan activity_monitor.Soc_FPS,
4050e098bc96SEvan Quan activity_monitor.Soc_UseRlcBusy,
4051e098bc96SEvan Quan activity_monitor.Soc_MinActiveFreqType,
4052e098bc96SEvan Quan activity_monitor.Soc_MinActiveFreq,
4053e098bc96SEvan Quan activity_monitor.Soc_BoosterFreqType,
4054e098bc96SEvan Quan activity_monitor.Soc_BoosterFreq,
4055e098bc96SEvan Quan activity_monitor.Soc_PD_Data_limit_c,
4056e098bc96SEvan Quan activity_monitor.Soc_PD_Data_error_coeff,
4057e098bc96SEvan Quan activity_monitor.Soc_PD_Data_error_rate_coeff);
4058e098bc96SEvan Quan
40590b023410SDarren Powell size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4060e098bc96SEvan Quan " ",
4061e098bc96SEvan Quan 2,
4062e098bc96SEvan Quan "UCLK",
4063e098bc96SEvan Quan activity_monitor.Mem_FPS,
4064e098bc96SEvan Quan activity_monitor.Mem_UseRlcBusy,
4065e098bc96SEvan Quan activity_monitor.Mem_MinActiveFreqType,
4066e098bc96SEvan Quan activity_monitor.Mem_MinActiveFreq,
4067e098bc96SEvan Quan activity_monitor.Mem_BoosterFreqType,
4068e098bc96SEvan Quan activity_monitor.Mem_BoosterFreq,
4069e098bc96SEvan Quan activity_monitor.Mem_PD_Data_limit_c,
4070e098bc96SEvan Quan activity_monitor.Mem_PD_Data_error_coeff,
4071e098bc96SEvan Quan activity_monitor.Mem_PD_Data_error_rate_coeff);
4072e098bc96SEvan Quan
40730b023410SDarren Powell size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4074e098bc96SEvan Quan " ",
4075e098bc96SEvan Quan 3,
4076e098bc96SEvan Quan "FCLK",
4077e098bc96SEvan Quan activity_monitor.Fclk_FPS,
4078e098bc96SEvan Quan activity_monitor.Fclk_UseRlcBusy,
4079e098bc96SEvan Quan activity_monitor.Fclk_MinActiveFreqType,
4080e098bc96SEvan Quan activity_monitor.Fclk_MinActiveFreq,
4081e098bc96SEvan Quan activity_monitor.Fclk_BoosterFreqType,
4082e098bc96SEvan Quan activity_monitor.Fclk_BoosterFreq,
4083e098bc96SEvan Quan activity_monitor.Fclk_PD_Data_limit_c,
4084e098bc96SEvan Quan activity_monitor.Fclk_PD_Data_error_coeff,
4085e098bc96SEvan Quan activity_monitor.Fclk_PD_Data_error_rate_coeff);
4086e098bc96SEvan Quan }
4087e098bc96SEvan Quan
4088e098bc96SEvan Quan return size;
4089e098bc96SEvan Quan }
4090e098bc96SEvan Quan
vega20_set_power_profile_mode(struct pp_hwmgr * hwmgr,long * input,uint32_t size)4091e098bc96SEvan Quan static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4092e098bc96SEvan Quan {
4093e098bc96SEvan Quan DpmActivityMonitorCoeffInt_t activity_monitor;
4094e098bc96SEvan Quan int workload_type, result = 0;
4095e098bc96SEvan Quan uint32_t power_profile_mode = input[size];
4096e098bc96SEvan Quan
4097e098bc96SEvan Quan if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
4098e098bc96SEvan Quan pr_err("Invalid power profile mode %d\n", power_profile_mode);
4099e098bc96SEvan Quan return -EINVAL;
4100e098bc96SEvan Quan }
4101e098bc96SEvan Quan
4102e098bc96SEvan Quan if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4103e098bc96SEvan Quan struct vega20_hwmgr *data =
4104e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
4105*df0a9bd9SMa Jun
4106*df0a9bd9SMa Jun if (size != 10 && size != 0)
4107e098bc96SEvan Quan return -EINVAL;
4108*df0a9bd9SMa Jun
4109*df0a9bd9SMa Jun if (size == 0 && !data->is_custom_profile_set)
4110e098bc96SEvan Quan return -EINVAL;
4111e098bc96SEvan Quan
4112e098bc96SEvan Quan result = vega20_get_activity_monitor_coeff(hwmgr,
4113e098bc96SEvan Quan (uint8_t *)(&activity_monitor),
4114e098bc96SEvan Quan WORKLOAD_PPLIB_CUSTOM_BIT);
4115e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
4116e098bc96SEvan Quan "[SetPowerProfile] Failed to get activity monitor!",
4117e098bc96SEvan Quan return result);
4118e098bc96SEvan Quan
4119e098bc96SEvan Quan /* If size==0, then we want to apply the already-configured
4120e098bc96SEvan Quan * CUSTOM profile again. Just apply it, since we checked its
4121e098bc96SEvan Quan * validity above
4122e098bc96SEvan Quan */
4123e098bc96SEvan Quan if (size == 0)
4124e098bc96SEvan Quan goto out;
4125e098bc96SEvan Quan
4126e098bc96SEvan Quan switch (input[0]) {
4127e098bc96SEvan Quan case 0: /* Gfxclk */
4128e098bc96SEvan Quan activity_monitor.Gfx_FPS = input[1];
4129e098bc96SEvan Quan activity_monitor.Gfx_UseRlcBusy = input[2];
4130e098bc96SEvan Quan activity_monitor.Gfx_MinActiveFreqType = input[3];
4131e098bc96SEvan Quan activity_monitor.Gfx_MinActiveFreq = input[4];
4132e098bc96SEvan Quan activity_monitor.Gfx_BoosterFreqType = input[5];
4133e098bc96SEvan Quan activity_monitor.Gfx_BoosterFreq = input[6];
4134e098bc96SEvan Quan activity_monitor.Gfx_PD_Data_limit_c = input[7];
4135e098bc96SEvan Quan activity_monitor.Gfx_PD_Data_error_coeff = input[8];
4136e098bc96SEvan Quan activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
4137e098bc96SEvan Quan break;
4138e098bc96SEvan Quan case 1: /* Socclk */
4139e098bc96SEvan Quan activity_monitor.Soc_FPS = input[1];
4140e098bc96SEvan Quan activity_monitor.Soc_UseRlcBusy = input[2];
4141e098bc96SEvan Quan activity_monitor.Soc_MinActiveFreqType = input[3];
4142e098bc96SEvan Quan activity_monitor.Soc_MinActiveFreq = input[4];
4143e098bc96SEvan Quan activity_monitor.Soc_BoosterFreqType = input[5];
4144e098bc96SEvan Quan activity_monitor.Soc_BoosterFreq = input[6];
4145e098bc96SEvan Quan activity_monitor.Soc_PD_Data_limit_c = input[7];
4146e098bc96SEvan Quan activity_monitor.Soc_PD_Data_error_coeff = input[8];
4147e098bc96SEvan Quan activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
4148e098bc96SEvan Quan break;
4149e098bc96SEvan Quan case 2: /* Uclk */
4150e098bc96SEvan Quan activity_monitor.Mem_FPS = input[1];
4151e098bc96SEvan Quan activity_monitor.Mem_UseRlcBusy = input[2];
4152e098bc96SEvan Quan activity_monitor.Mem_MinActiveFreqType = input[3];
4153e098bc96SEvan Quan activity_monitor.Mem_MinActiveFreq = input[4];
4154e098bc96SEvan Quan activity_monitor.Mem_BoosterFreqType = input[5];
4155e098bc96SEvan Quan activity_monitor.Mem_BoosterFreq = input[6];
4156e098bc96SEvan Quan activity_monitor.Mem_PD_Data_limit_c = input[7];
4157e098bc96SEvan Quan activity_monitor.Mem_PD_Data_error_coeff = input[8];
4158e098bc96SEvan Quan activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
4159e098bc96SEvan Quan break;
4160e098bc96SEvan Quan case 3: /* Fclk */
4161e098bc96SEvan Quan activity_monitor.Fclk_FPS = input[1];
4162e098bc96SEvan Quan activity_monitor.Fclk_UseRlcBusy = input[2];
4163e098bc96SEvan Quan activity_monitor.Fclk_MinActiveFreqType = input[3];
4164e098bc96SEvan Quan activity_monitor.Fclk_MinActiveFreq = input[4];
4165e098bc96SEvan Quan activity_monitor.Fclk_BoosterFreqType = input[5];
4166e098bc96SEvan Quan activity_monitor.Fclk_BoosterFreq = input[6];
4167e098bc96SEvan Quan activity_monitor.Fclk_PD_Data_limit_c = input[7];
4168e098bc96SEvan Quan activity_monitor.Fclk_PD_Data_error_coeff = input[8];
4169e098bc96SEvan Quan activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
4170e098bc96SEvan Quan break;
4171*df0a9bd9SMa Jun default:
4172*df0a9bd9SMa Jun return -EINVAL;
4173e098bc96SEvan Quan }
4174e098bc96SEvan Quan
4175e098bc96SEvan Quan result = vega20_set_activity_monitor_coeff(hwmgr,
4176e098bc96SEvan Quan (uint8_t *)(&activity_monitor),
4177e098bc96SEvan Quan WORKLOAD_PPLIB_CUSTOM_BIT);
4178e098bc96SEvan Quan data->is_custom_profile_set = true;
4179e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
4180e098bc96SEvan Quan "[SetPowerProfile] Failed to set activity monitor!",
4181e098bc96SEvan Quan return result);
4182e098bc96SEvan Quan }
4183e098bc96SEvan Quan
4184e098bc96SEvan Quan out:
4185e098bc96SEvan Quan /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
4186e098bc96SEvan Quan workload_type =
4187e098bc96SEvan Quan conv_power_profile_to_pplib_workload(power_profile_mode);
4188e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4189e098bc96SEvan Quan 1 << workload_type,
4190e098bc96SEvan Quan NULL);
4191e098bc96SEvan Quan
4192e098bc96SEvan Quan hwmgr->power_profile_mode = power_profile_mode;
4193e098bc96SEvan Quan
4194e098bc96SEvan Quan return 0;
4195e098bc96SEvan Quan }
4196e098bc96SEvan Quan
vega20_notify_cac_buffer_info(struct pp_hwmgr * hwmgr,uint32_t virtual_addr_low,uint32_t virtual_addr_hi,uint32_t mc_addr_low,uint32_t mc_addr_hi,uint32_t size)4197e098bc96SEvan Quan static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4198e098bc96SEvan Quan uint32_t virtual_addr_low,
4199e098bc96SEvan Quan uint32_t virtual_addr_hi,
4200e098bc96SEvan Quan uint32_t mc_addr_low,
4201e098bc96SEvan Quan uint32_t mc_addr_hi,
4202e098bc96SEvan Quan uint32_t size)
4203e098bc96SEvan Quan {
4204e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
4205e098bc96SEvan Quan PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4206e098bc96SEvan Quan virtual_addr_hi,
4207e098bc96SEvan Quan NULL);
4208e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
4209e098bc96SEvan Quan PPSMC_MSG_SetSystemVirtualDramAddrLow,
4210e098bc96SEvan Quan virtual_addr_low,
4211e098bc96SEvan Quan NULL);
4212e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
4213e098bc96SEvan Quan PPSMC_MSG_DramLogSetDramAddrHigh,
4214e098bc96SEvan Quan mc_addr_hi,
4215e098bc96SEvan Quan NULL);
4216e098bc96SEvan Quan
4217e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
4218e098bc96SEvan Quan PPSMC_MSG_DramLogSetDramAddrLow,
4219e098bc96SEvan Quan mc_addr_low,
4220e098bc96SEvan Quan NULL);
4221e098bc96SEvan Quan
4222e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
4223e098bc96SEvan Quan PPSMC_MSG_DramLogSetDramSize,
4224e098bc96SEvan Quan size,
4225e098bc96SEvan Quan NULL);
4226e098bc96SEvan Quan return 0;
4227e098bc96SEvan Quan }
4228e098bc96SEvan Quan
vega20_get_thermal_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * thermal_data)4229e098bc96SEvan Quan static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4230e098bc96SEvan Quan struct PP_TemperatureRange *thermal_data)
4231e098bc96SEvan Quan {
4232064329c5SEvan Quan struct phm_ppt_v3_information *pptable_information =
4233064329c5SEvan Quan (struct phm_ppt_v3_information *)hwmgr->pptable;
4234e098bc96SEvan Quan struct vega20_hwmgr *data =
4235e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
4236e098bc96SEvan Quan PPTable_t *pp_table = &(data->smc_state_table.pp_table);
4237e098bc96SEvan Quan
4238e098bc96SEvan Quan memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4239e098bc96SEvan Quan
4240e098bc96SEvan Quan thermal_data->max = pp_table->TedgeLimit *
4241e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4242e098bc96SEvan Quan thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
4243e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4244e098bc96SEvan Quan thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
4245e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4246e098bc96SEvan Quan thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
4247e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4248e098bc96SEvan Quan thermal_data->mem_crit_max = pp_table->ThbmLimit *
4249e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4250e098bc96SEvan Quan thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
4251e098bc96SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4252064329c5SEvan Quan thermal_data->sw_ctf_threshold = pptable_information->us_software_shutdown_temp *
4253064329c5SEvan Quan PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4254e098bc96SEvan Quan
4255e098bc96SEvan Quan return 0;
4256e098bc96SEvan Quan }
4257e098bc96SEvan Quan
vega20_smu_i2c_bus_access(struct pp_hwmgr * hwmgr,bool acquire)4258e098bc96SEvan Quan static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
4259e098bc96SEvan Quan {
4260e098bc96SEvan Quan int res;
4261e098bc96SEvan Quan
4262e098bc96SEvan Quan /* I2C bus access can happen very early, when SMU not loaded yet */
4263e098bc96SEvan Quan if (!vega20_is_smc_ram_running(hwmgr))
4264e098bc96SEvan Quan return 0;
4265e098bc96SEvan Quan
4266e098bc96SEvan Quan res = smum_send_msg_to_smc_with_parameter(hwmgr,
4267e098bc96SEvan Quan (acquire ?
4268e098bc96SEvan Quan PPSMC_MSG_RequestI2CBus :
4269e098bc96SEvan Quan PPSMC_MSG_ReleaseI2CBus),
4270e098bc96SEvan Quan 0,
4271e098bc96SEvan Quan NULL);
4272e098bc96SEvan Quan
4273e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res);
4274e098bc96SEvan Quan return res;
4275e098bc96SEvan Quan }
4276e098bc96SEvan Quan
vega20_set_df_cstate(struct pp_hwmgr * hwmgr,enum pp_df_cstate state)4277e098bc96SEvan Quan static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
4278e098bc96SEvan Quan enum pp_df_cstate state)
4279e098bc96SEvan Quan {
4280e098bc96SEvan Quan int ret;
4281e098bc96SEvan Quan
4282e098bc96SEvan Quan /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
4283e098bc96SEvan Quan if (hwmgr->smu_version < 0x283200) {
4284e098bc96SEvan Quan pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
4285e098bc96SEvan Quan return -EINVAL;
4286e098bc96SEvan Quan }
4287e098bc96SEvan Quan
4288e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state,
4289e098bc96SEvan Quan NULL);
4290e098bc96SEvan Quan if (ret)
4291e098bc96SEvan Quan pr_err("SetDfCstate failed!\n");
4292e098bc96SEvan Quan
4293e098bc96SEvan Quan return ret;
4294e098bc96SEvan Quan }
4295e098bc96SEvan Quan
vega20_set_xgmi_pstate(struct pp_hwmgr * hwmgr,uint32_t pstate)4296e098bc96SEvan Quan static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
4297e098bc96SEvan Quan uint32_t pstate)
4298e098bc96SEvan Quan {
4299e098bc96SEvan Quan int ret;
4300e098bc96SEvan Quan
4301e098bc96SEvan Quan ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4302e098bc96SEvan Quan PPSMC_MSG_SetXgmiMode,
4303e098bc96SEvan Quan pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
4304e098bc96SEvan Quan NULL);
4305e098bc96SEvan Quan if (ret)
4306e098bc96SEvan Quan pr_err("SetXgmiPstate failed!\n");
4307e098bc96SEvan Quan
4308e098bc96SEvan Quan return ret;
4309e098bc96SEvan Quan }
4310e098bc96SEvan Quan
vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 * gpu_metrics)4311e098bc96SEvan Quan static void vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
4312e098bc96SEvan Quan {
4313e098bc96SEvan Quan memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
4314e098bc96SEvan Quan
4315e098bc96SEvan Quan gpu_metrics->common_header.structure_size =
4316e098bc96SEvan Quan sizeof(struct gpu_metrics_v1_0);
4317e098bc96SEvan Quan gpu_metrics->common_header.format_revision = 1;
4318e098bc96SEvan Quan gpu_metrics->common_header.content_revision = 0;
4319e098bc96SEvan Quan
4320e098bc96SEvan Quan gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4321e098bc96SEvan Quan }
4322e098bc96SEvan Quan
vega20_get_gpu_metrics(struct pp_hwmgr * hwmgr,void ** table)4323e098bc96SEvan Quan static ssize_t vega20_get_gpu_metrics(struct pp_hwmgr *hwmgr,
4324e098bc96SEvan Quan void **table)
4325e098bc96SEvan Quan {
4326e098bc96SEvan Quan struct vega20_hwmgr *data =
4327e098bc96SEvan Quan (struct vega20_hwmgr *)(hwmgr->backend);
4328e098bc96SEvan Quan struct gpu_metrics_v1_0 *gpu_metrics =
4329e098bc96SEvan Quan &data->gpu_metrics_table;
4330e098bc96SEvan Quan SmuMetrics_t metrics;
4331e098bc96SEvan Quan uint32_t fan_speed_rpm;
4332e098bc96SEvan Quan int ret;
4333e098bc96SEvan Quan
4334e098bc96SEvan Quan ret = vega20_get_metrics_table(hwmgr, &metrics, true);
4335e098bc96SEvan Quan if (ret)
4336e098bc96SEvan Quan return ret;
4337e098bc96SEvan Quan
4338e098bc96SEvan Quan vega20_init_gpu_metrics_v1_0(gpu_metrics);
4339e098bc96SEvan Quan
4340e098bc96SEvan Quan gpu_metrics->temperature_edge = metrics.TemperatureEdge;
4341e098bc96SEvan Quan gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
4342e098bc96SEvan Quan gpu_metrics->temperature_mem = metrics.TemperatureHBM;
4343e098bc96SEvan Quan gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
4344e098bc96SEvan Quan gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
4345e098bc96SEvan Quan gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
4346e098bc96SEvan Quan
4347e098bc96SEvan Quan gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
4348e098bc96SEvan Quan gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
4349e098bc96SEvan Quan
4350e098bc96SEvan Quan gpu_metrics->average_socket_power = metrics.AverageSocketPower;
4351e098bc96SEvan Quan
4352e098bc96SEvan Quan gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
4353e098bc96SEvan Quan gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
4354e098bc96SEvan Quan gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
4355e098bc96SEvan Quan
4356e098bc96SEvan Quan gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
4357e098bc96SEvan Quan gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
4358e098bc96SEvan Quan gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
4359e098bc96SEvan Quan gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
4360e098bc96SEvan Quan gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
4361e098bc96SEvan Quan
4362e098bc96SEvan Quan gpu_metrics->throttle_status = metrics.ThrottlerStatus;
4363e098bc96SEvan Quan
4364e098bc96SEvan Quan vega20_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
4365e098bc96SEvan Quan gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
4366e098bc96SEvan Quan
4367e098bc96SEvan Quan gpu_metrics->pcie_link_width =
4368e098bc96SEvan Quan vega20_get_current_pcie_link_width(hwmgr);
4369e098bc96SEvan Quan gpu_metrics->pcie_link_speed =
4370e098bc96SEvan Quan vega20_get_current_pcie_link_speed(hwmgr);
4371e098bc96SEvan Quan
4372e098bc96SEvan Quan *table = (void *)gpu_metrics;
4373e098bc96SEvan Quan
4374e098bc96SEvan Quan return sizeof(struct gpu_metrics_v1_0);
4375e098bc96SEvan Quan }
4376e098bc96SEvan Quan
4377e098bc96SEvan Quan static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
4378e098bc96SEvan Quan /* init/fini related */
4379e098bc96SEvan Quan .backend_init = vega20_hwmgr_backend_init,
4380e098bc96SEvan Quan .backend_fini = vega20_hwmgr_backend_fini,
4381e098bc96SEvan Quan .asic_setup = vega20_setup_asic_task,
4382e098bc96SEvan Quan .power_off_asic = vega20_power_off_asic,
4383e098bc96SEvan Quan .dynamic_state_management_enable = vega20_enable_dpm_tasks,
4384e098bc96SEvan Quan .dynamic_state_management_disable = vega20_disable_dpm_tasks,
4385e098bc96SEvan Quan /* power state related */
4386e098bc96SEvan Quan .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
4387e098bc96SEvan Quan .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
4388e098bc96SEvan Quan .display_config_changed = vega20_display_configuration_changed_task,
4389e098bc96SEvan Quan .check_smc_update_required_for_display_configuration =
4390e098bc96SEvan Quan vega20_check_smc_update_required_for_display_configuration,
4391e098bc96SEvan Quan .notify_smc_display_config_after_ps_adjustment =
4392e098bc96SEvan Quan vega20_notify_smc_display_config_after_ps_adjustment,
4393e098bc96SEvan Quan /* export to DAL */
4394e098bc96SEvan Quan .get_sclk = vega20_dpm_get_sclk,
4395e098bc96SEvan Quan .get_mclk = vega20_dpm_get_mclk,
4396e098bc96SEvan Quan .get_dal_power_level = vega20_get_dal_power_level,
4397e098bc96SEvan Quan .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
4398e098bc96SEvan Quan .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
4399e098bc96SEvan Quan .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
4400e098bc96SEvan Quan .display_clock_voltage_request = vega20_display_clock_voltage_request,
4401e098bc96SEvan Quan .get_performance_level = vega20_get_performance_level,
4402e098bc96SEvan Quan /* UMD pstate, profile related */
4403e098bc96SEvan Quan .force_dpm_level = vega20_dpm_force_dpm_level,
4404e098bc96SEvan Quan .get_power_profile_mode = vega20_get_power_profile_mode,
4405e098bc96SEvan Quan .set_power_profile_mode = vega20_set_power_profile_mode,
4406e098bc96SEvan Quan /* od related */
4407e098bc96SEvan Quan .set_power_limit = vega20_set_power_limit,
4408e098bc96SEvan Quan .get_sclk_od = vega20_get_sclk_od,
4409e098bc96SEvan Quan .set_sclk_od = vega20_set_sclk_od,
4410e098bc96SEvan Quan .get_mclk_od = vega20_get_mclk_od,
4411e098bc96SEvan Quan .set_mclk_od = vega20_set_mclk_od,
4412e098bc96SEvan Quan .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
4413e098bc96SEvan Quan /* for sysfs to retrive/set gfxclk/memclk */
4414e098bc96SEvan Quan .force_clock_level = vega20_force_clock_level,
4415e098bc96SEvan Quan .print_clock_levels = vega20_print_clock_levels,
4416e098bc96SEvan Quan .read_sensor = vega20_read_sensor,
4417e098bc96SEvan Quan .get_ppfeature_status = vega20_get_ppfeature_status,
4418e098bc96SEvan Quan .set_ppfeature_status = vega20_set_ppfeature_status,
4419e098bc96SEvan Quan /* powergate related */
4420e098bc96SEvan Quan .powergate_uvd = vega20_power_gate_uvd,
4421e098bc96SEvan Quan .powergate_vce = vega20_power_gate_vce,
4422e098bc96SEvan Quan /* thermal related */
4423e098bc96SEvan Quan .start_thermal_controller = vega20_start_thermal_controller,
4424e098bc96SEvan Quan .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
4425e098bc96SEvan Quan .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
4426e098bc96SEvan Quan .register_irq_handlers = smu9_register_irq_handlers,
4427e098bc96SEvan Quan .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
4428e098bc96SEvan Quan /* fan control related */
44290d8318e1SEvan Quan .get_fan_speed_pwm = vega20_fan_ctrl_get_fan_speed_pwm,
44300d8318e1SEvan Quan .set_fan_speed_pwm = vega20_fan_ctrl_set_fan_speed_pwm,
4431e098bc96SEvan Quan .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
4432e098bc96SEvan Quan .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
4433e098bc96SEvan Quan .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
4434e098bc96SEvan Quan .get_fan_control_mode = vega20_get_fan_control_mode,
4435e098bc96SEvan Quan .set_fan_control_mode = vega20_set_fan_control_mode,
4436e098bc96SEvan Quan /* smu memory related */
4437e098bc96SEvan Quan .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
4438e098bc96SEvan Quan .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
4439e098bc96SEvan Quan /* BACO related */
44401b199594SMa Jun .get_bamaco_support = vega20_get_bamaco_support,
4441e098bc96SEvan Quan .get_asic_baco_state = vega20_baco_get_state,
4442e098bc96SEvan Quan .set_asic_baco_state = vega20_baco_set_state,
4443e098bc96SEvan Quan .set_mp1_state = vega20_set_mp1_state,
4444e098bc96SEvan Quan .smu_i2c_bus_access = vega20_smu_i2c_bus_access,
4445e098bc96SEvan Quan .set_df_cstate = vega20_set_df_cstate,
4446e098bc96SEvan Quan .set_xgmi_pstate = vega20_set_xgmi_pstate,
4447e098bc96SEvan Quan .get_gpu_metrics = vega20_get_gpu_metrics,
4448e098bc96SEvan Quan };
4449e098bc96SEvan Quan
vega20_hwmgr_init(struct pp_hwmgr * hwmgr)4450e098bc96SEvan Quan int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
4451e098bc96SEvan Quan {
4452e098bc96SEvan Quan hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
4453e098bc96SEvan Quan hwmgr->pptable_func = &vega20_pptable_funcs;
4454e098bc96SEvan Quan
4455e098bc96SEvan Quan return 0;
4456e098bc96SEvan Quan }
4457