Lines Matching +full:mclk +full:- +full:calibrate
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
65 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
108 return __ast_mindwm(ast->regs, r);
113 __ast_moutdwm(ast->regs, r, v);
119 #define CBR_SIZE_AST2150 ((16 << 10) - 1)
173 #if 0 /* unused in DDX driver - here for completeness */
244 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
247 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
272 if (ast->chip == AST2100 || ast->chip == AST2200)
290 while (dram_reg_info->index != 0xffff) {
291 if (dram_reg_info->index == 0xff00) {/* delay fn */
293 udelay(dram_reg_info->data);
294 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
295 data = dram_reg_info->data;
296 if (ast->dram_type == AST_DRAM_1Gx16)
298 else if (ast->dram_type == AST_DRAM_1Gx32)
304 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
306 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
350 if (ast->tx_chip == AST_TX_ASTDP) {
356 if (ast->config_mode == ast_use_p2a) {
359 if (ast->tx_chip == AST_TX_SIL164) {
365 if (ast->config_mode == ast_use_p2a) {
369 if (ast->tx_chip == AST_TX_SIL164) {
375 if (ast->config_mode == ast_use_p2a) {
378 if (ast->tx_chip == AST_TX_SIL164) {
420 #define CBR_SIZE0 ((1 << 10) - 1)
421 #define CBR_SIZE1 ((4 << 10) - 1)
422 #define CBR_SIZE2 ((64 << 10) - 1)
642 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
660 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
663 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
668 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
672 dlli = (8 - dlli) & 0x7;
682 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
685 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
689 dlli = (dlli - 1) & 0x7;
692 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
697 dlli = (8 - dlli) & 0x7;
767 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
771 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
777 passcnt[1] = passcnt[0] - g_side;
837 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
840 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
865 param->reg_MADJ = 0x00034C4C;
866 param->reg_SADJ = 0x00001800;
867 param->reg_DRV = 0x000000F0;
868 param->reg_PERIOD = param->dram_freq;
869 param->rodt = 0;
871 switch (param->dram_freq) {
874 param->wodt = 0;
875 param->reg_AC1 = 0x22202725;
876 param->reg_AC2 = 0xAA007613 | trap_AC2;
877 param->reg_DQSIC = 0x000000BA;
878 param->reg_MRS = 0x04001400 | trap_MRS;
879 param->reg_EMRS = 0x00000000;
880 param->reg_IOZ = 0x00000023;
881 param->reg_DQIDLY = 0x00000074;
882 param->reg_FREQ = 0x00004DC0;
883 param->madj_max = 96;
884 param->dll2_finetune_step = 3;
885 switch (param->dram_chipid) {
889 param->reg_AC2 = 0xAA007613 | trap_AC2;
892 param->reg_AC2 = 0xAA00761C | trap_AC2;
895 param->reg_AC2 = 0xAA007636 | trap_AC2;
902 param->wodt = 1;
903 param->reg_AC1 = 0x33302825;
904 param->reg_AC2 = 0xCC009617 | trap_AC2;
905 param->reg_DQSIC = 0x000000E2;
906 param->reg_MRS = 0x04001600 | trap_MRS;
907 param->reg_EMRS = 0x00000000;
908 param->reg_IOZ = 0x00000034;
909 param->reg_DRV = 0x000000FA;
910 param->reg_DQIDLY = 0x00000089;
911 param->reg_FREQ = 0x00005040;
912 param->madj_max = 96;
913 param->dll2_finetune_step = 4;
915 switch (param->dram_chipid) {
919 param->reg_AC2 = 0xCC009617 | trap_AC2;
922 param->reg_AC2 = 0xCC009622 | trap_AC2;
925 param->reg_AC2 = 0xCC00963F | trap_AC2;
932 param->wodt = 1;
933 param->reg_AC1 = 0x33302825;
934 param->reg_AC2 = 0xCC009617 | trap_AC2;
935 param->reg_DQSIC = 0x000000E2;
936 param->reg_MRS = 0x04001600 | trap_MRS;
937 param->reg_EMRS = 0x00000000;
938 param->reg_IOZ = 0x00000023;
939 param->reg_DRV = 0x000000FA;
940 param->reg_DQIDLY = 0x00000089;
941 param->reg_FREQ = 0x000050C0;
942 param->madj_max = 96;
943 param->dll2_finetune_step = 4;
945 switch (param->dram_chipid) {
949 param->reg_AC2 = 0xCC009617 | trap_AC2;
952 param->reg_AC2 = 0xCC009622 | trap_AC2;
955 param->reg_AC2 = 0xCC00963F | trap_AC2;
962 param->wodt = 0;
963 param->reg_AC1 = 0x33302926;
964 param->reg_AC2 = 0xCD44961A;
965 param->reg_DQSIC = 0x000000FC;
966 param->reg_MRS = 0x00081830;
967 param->reg_EMRS = 0x00000000;
968 param->reg_IOZ = 0x00000045;
969 param->reg_DQIDLY = 0x00000097;
970 param->reg_FREQ = 0x000052C0;
971 param->madj_max = 88;
972 param->dll2_finetune_step = 4;
976 param->wodt = 1;
977 param->reg_AC1 = 0x33302926;
978 param->reg_AC2 = 0xDE44A61D;
979 param->reg_DQSIC = 0x00000117;
980 param->reg_MRS = 0x00081A30;
981 param->reg_EMRS = 0x00000000;
982 param->reg_IOZ = 0x070000BB;
983 param->reg_DQIDLY = 0x000000A0;
984 param->reg_FREQ = 0x000054C0;
985 param->madj_max = 79;
986 param->dll2_finetune_step = 4;
990 param->wodt = 1;
991 param->rodt = 1;
992 param->reg_AC1 = 0x33302926;
993 param->reg_AC2 = 0xEF44B61E;
994 param->reg_DQSIC = 0x00000125;
995 param->reg_MRS = 0x00081A30;
996 param->reg_EMRS = 0x00000040;
997 param->reg_DRV = 0x000000F5;
998 param->reg_IOZ = 0x00000023;
999 param->reg_DQIDLY = 0x00000088;
1000 param->reg_FREQ = 0x000055C0;
1001 param->madj_max = 76;
1002 param->dll2_finetune_step = 3;
1006 param->reg_MADJ = 0x00136868;
1007 param->reg_SADJ = 0x00004534;
1008 param->wodt = 1;
1009 param->rodt = 1;
1010 param->reg_AC1 = 0x33302A37;
1011 param->reg_AC2 = 0xEF56B61E;
1012 param->reg_DQSIC = 0x0000013F;
1013 param->reg_MRS = 0x00101A50;
1014 param->reg_EMRS = 0x00000040;
1015 param->reg_DRV = 0x000000FA;
1016 param->reg_IOZ = 0x00000023;
1017 param->reg_DQIDLY = 0x00000078;
1018 param->reg_FREQ = 0x000057C0;
1019 param->madj_max = 136;
1020 param->dll2_finetune_step = 3;
1024 param->reg_MADJ = 0x00136868;
1025 param->reg_SADJ = 0x00004534;
1026 param->wodt = 1;
1027 param->rodt = 1;
1028 param->reg_AC1 = 0x32302A37;
1029 param->reg_AC2 = 0xDF56B61F;
1030 param->reg_DQSIC = 0x0000014D;
1031 param->reg_MRS = 0x00101A50;
1032 param->reg_EMRS = 0x00000004;
1033 param->reg_DRV = 0x000000F5;
1034 param->reg_IOZ = 0x00000023;
1035 param->reg_DQIDLY = 0x00000078;
1036 param->reg_FREQ = 0x000058C0;
1037 param->madj_max = 132;
1038 param->dll2_finetune_step = 3;
1042 param->reg_MADJ = 0x00136868;
1043 param->reg_SADJ = 0x00004534;
1044 param->wodt = 1;
1045 param->rodt = 1;
1046 param->reg_AC1 = 0x32302A37;
1047 param->reg_AC2 = 0xEF56B621;
1048 param->reg_DQSIC = 0x0000015A;
1049 param->reg_MRS = 0x02101A50;
1050 param->reg_EMRS = 0x00000004;
1051 param->reg_DRV = 0x000000F5;
1052 param->reg_IOZ = 0x00000034;
1053 param->reg_DQIDLY = 0x00000078;
1054 param->reg_FREQ = 0x000059C0;
1055 param->madj_max = 128;
1056 param->dll2_finetune_step = 3;
1060 switch (param->dram_chipid) {
1062 param->dram_config = 0x130;
1066 param->dram_config = 0x131;
1069 param->dram_config = 0x132;
1072 param->dram_config = 0x133;
1076 switch (param->vram_size) {
1079 param->dram_config |= 0x00;
1082 param->dram_config |= 0x04;
1085 param->dram_config |= 0x08;
1088 param->dram_config |= 0x0c;
1104 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1105 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1107 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1110 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1112 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1113 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1114 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1117 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1128 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1129 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1134 /* Wait MCLK2X lock to MCLK */
1142 if ((data2 & 0xff) > param->madj_max) {
1177 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1178 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1183 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1189 if (param->wodt) {
1192 if (param->rodt) {
1193 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1197 /* Calibrate the DQSI delay */
1201 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1230 param->reg_MADJ = 0x00034C4C;
1231 param->reg_SADJ = 0x00001800;
1232 param->reg_DRV = 0x000000F0;
1233 param->reg_PERIOD = param->dram_freq;
1234 param->rodt = 0;
1236 switch (param->dram_freq) {
1239 param->wodt = 0;
1240 param->reg_AC1 = 0x11101513;
1241 param->reg_AC2 = 0x78117011;
1242 param->reg_DQSIC = 0x00000092;
1243 param->reg_MRS = 0x00000842;
1244 param->reg_EMRS = 0x00000000;
1245 param->reg_DRV = 0x000000F0;
1246 param->reg_IOZ = 0x00000034;
1247 param->reg_DQIDLY = 0x0000005A;
1248 param->reg_FREQ = 0x00004AC0;
1249 param->madj_max = 138;
1250 param->dll2_finetune_step = 3;
1254 param->wodt = 1;
1255 param->reg_AC1 = 0x22202613;
1256 param->reg_AC2 = 0xAA009016 | trap_AC2;
1257 param->reg_DQSIC = 0x000000BA;
1258 param->reg_MRS = 0x00000A02 | trap_MRS;
1259 param->reg_EMRS = 0x00000040;
1260 param->reg_DRV = 0x000000FA;
1261 param->reg_IOZ = 0x00000034;
1262 param->reg_DQIDLY = 0x00000074;
1263 param->reg_FREQ = 0x00004DC0;
1264 param->madj_max = 96;
1265 param->dll2_finetune_step = 3;
1266 switch (param->dram_chipid) {
1269 param->reg_AC2 = 0xAA009012 | trap_AC2;
1272 param->reg_AC2 = 0xAA009016 | trap_AC2;
1275 param->reg_AC2 = 0xAA009023 | trap_AC2;
1278 param->reg_AC2 = 0xAA00903B | trap_AC2;
1285 param->wodt = 1;
1286 param->rodt = 0;
1287 param->reg_AC1 = 0x33302714;
1288 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1289 param->reg_DQSIC = 0x000000E2;
1290 param->reg_MRS = 0x00000C02 | trap_MRS;
1291 param->reg_EMRS = 0x00000040;
1292 param->reg_DRV = 0x000000FA;
1293 param->reg_IOZ = 0x00000034;
1294 param->reg_DQIDLY = 0x00000089;
1295 param->reg_FREQ = 0x00005040;
1296 param->madj_max = 96;
1297 param->dll2_finetune_step = 4;
1299 switch (param->dram_chipid) {
1301 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1305 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1308 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1311 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1319 param->wodt = 1;
1320 param->rodt = 0;
1321 param->reg_AC1 = 0x33302714;
1322 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1323 param->reg_DQSIC = 0x000000E2;
1324 param->reg_MRS = 0x00000C02 | trap_MRS;
1325 param->reg_EMRS = 0x00000040;
1326 param->reg_DRV = 0x000000FA;
1327 param->reg_IOZ = 0x00000034;
1328 param->reg_DQIDLY = 0x00000089;
1329 param->reg_FREQ = 0x000050C0;
1330 param->madj_max = 96;
1331 param->dll2_finetune_step = 4;
1333 switch (param->dram_chipid) {
1335 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1339 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1342 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1345 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1352 param->wodt = 0;
1353 param->reg_AC1 = 0x33302815;
1354 param->reg_AC2 = 0xCD44B01E;
1355 param->reg_DQSIC = 0x000000FC;
1356 param->reg_MRS = 0x00000E72;
1357 param->reg_EMRS = 0x00000000;
1358 param->reg_DRV = 0x00000000;
1359 param->reg_IOZ = 0x00000034;
1360 param->reg_DQIDLY = 0x00000097;
1361 param->reg_FREQ = 0x000052C0;
1362 param->madj_max = 88;
1363 param->dll2_finetune_step = 3;
1367 param->wodt = 1;
1368 param->rodt = 1;
1369 param->reg_AC1 = 0x33302815;
1370 param->reg_AC2 = 0xDE44C022;
1371 param->reg_DQSIC = 0x00000117;
1372 param->reg_MRS = 0x00000E72;
1373 param->reg_EMRS = 0x00000040;
1374 param->reg_DRV = 0x0000000A;
1375 param->reg_IOZ = 0x00000045;
1376 param->reg_DQIDLY = 0x000000A0;
1377 param->reg_FREQ = 0x000054C0;
1378 param->madj_max = 79;
1379 param->dll2_finetune_step = 3;
1383 param->wodt = 1;
1384 param->rodt = 1;
1385 param->reg_AC1 = 0x33302815;
1386 param->reg_AC2 = 0xEF44D024;
1387 param->reg_DQSIC = 0x00000125;
1388 param->reg_MRS = 0x00000E72;
1389 param->reg_EMRS = 0x00000004;
1390 param->reg_DRV = 0x000000F9;
1391 param->reg_IOZ = 0x00000045;
1392 param->reg_DQIDLY = 0x000000A7;
1393 param->reg_FREQ = 0x000055C0;
1394 param->madj_max = 76;
1395 param->dll2_finetune_step = 3;
1399 param->wodt = 1;
1400 param->rodt = 1;
1401 param->reg_AC1 = 0x43402915;
1402 param->reg_AC2 = 0xFF44E025;
1403 param->reg_DQSIC = 0x00000132;
1404 param->reg_MRS = 0x00000E72;
1405 param->reg_EMRS = 0x00000040;
1406 param->reg_DRV = 0x0000000A;
1407 param->reg_IOZ = 0x00000045;
1408 param->reg_DQIDLY = 0x000000AD;
1409 param->reg_FREQ = 0x000056C0;
1410 param->madj_max = 76;
1411 param->dll2_finetune_step = 3;
1415 param->wodt = 1;
1416 param->rodt = 1;
1417 param->reg_AC1 = 0x43402915;
1418 param->reg_AC2 = 0xFF44E027;
1419 param->reg_DQSIC = 0x0000013F;
1420 param->reg_MRS = 0x00000E72;
1421 param->reg_EMRS = 0x00000004;
1422 param->reg_DRV = 0x000000F5;
1423 param->reg_IOZ = 0x00000045;
1424 param->reg_DQIDLY = 0x000000B3;
1425 param->reg_FREQ = 0x000057C0;
1426 param->madj_max = 76;
1427 param->dll2_finetune_step = 3;
1431 switch (param->dram_chipid) {
1433 param->dram_config = 0x100;
1437 param->dram_config = 0x121;
1440 param->dram_config = 0x122;
1443 param->dram_config = 0x123;
1447 switch (param->vram_size) {
1450 param->dram_config |= 0x00;
1453 param->dram_config |= 0x04;
1456 param->dram_config |= 0x08;
1459 param->dram_config |= 0x0c;
1472 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1473 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1475 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1478 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1480 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1481 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1482 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1485 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1496 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1497 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1503 /* Wait MCLK2X lock to MCLK */
1511 if ((data2 & 0xff) > param->madj_max) {
1546 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1547 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1554 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1556 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1558 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1563 if (param->wodt) {
1566 if (param->rodt) {
1567 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1570 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1572 /* Calibrate the DQSI delay */
1999 if (max_tries-- == 0)
2034 * If "Fast restet" is enabled for ARM-ICE debugger,
2060 struct drm_device *dev = &ast->base;
2067 ast_patch_ahb_2500(ast->regs);
2075 * SCU90 is Multi-function Pin Control #5
2078 * SCU94 is Multi-function Pin Control #6