Lines Matching +full:mclk +full:- +full:calibrate
1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8904.c -- WM8904 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
48 struct clk *mclk;
84 /* DC servo configuration - cached offset values */
89 { 4, 0x0018 }, /* R4 - Bias Control 0 */
90 { 5, 0x0000 }, /* R5 - VMID Control 0 */
91 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
92 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
93 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
94 { 9, 0x9696 }, /* R9 - mic Filter Control */
95 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
96 { 12, 0x0000 }, /* R12 - Power Management 0 */
97 { 14, 0x0000 }, /* R14 - Power Management 2 */
98 { 15, 0x0000 }, /* R15 - Power Management 3 */
99 { 18, 0x0000 }, /* R18 - Power Management 6 */
100 { 20, 0x945E }, /* R20 - Clock Rates 0 */
101 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
102 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
103 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
104 { 25, 0x000A }, /* R25 - Audio Interface 1 */
105 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
106 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
107 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
108 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
109 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
110 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
111 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
112 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
113 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
114 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
115 { 40, 0x01AF }, /* R40 - DRC 0 */
116 { 41, 0x3248 }, /* R41 - DRC 1 */
117 { 42, 0x0000 }, /* R42 - DRC 2 */
118 { 43, 0x0000 }, /* R43 - DRC 3 */
119 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
120 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
121 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
122 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
123 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
124 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
125 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
126 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
127 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
128 { 67, 0x0000 }, /* R67 - DC Servo 0 */
129 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
130 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
131 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
132 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
133 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
134 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
135 { 104, 0x0004 }, /* R104 - Class W 0 */
136 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
137 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
138 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
139 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
140 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
141 { 116, 0x0000 }, /* R116 - FLL Control 1 */
142 { 117, 0x0007 }, /* R117 - FLL Control 2 */
143 { 118, 0x0000 }, /* R118 - FLL Control 3 */
144 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
145 { 120, 0x0004 }, /* R120 - FLL Control 5 */
146 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
147 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
148 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
149 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
150 { 126, 0x0000 }, /* R126 - Digital Pulls */
151 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
152 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
153 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
154 { 134, 0x0000 }, /* R134 - EQ1 */
155 { 135, 0x000C }, /* R135 - EQ2 */
156 { 136, 0x000C }, /* R136 - EQ3 */
157 { 137, 0x000C }, /* R137 - EQ4 */
158 { 138, 0x000C }, /* R138 - EQ5 */
159 { 139, 0x000C }, /* R139 - EQ6 */
160 { 140, 0x0FCA }, /* R140 - EQ7 */
161 { 141, 0x0400 }, /* R141 - EQ8 */
162 { 142, 0x00D8 }, /* R142 - EQ9 */
163 { 143, 0x1EB5 }, /* R143 - EQ10 */
164 { 144, 0xF145 }, /* R144 - EQ11 */
165 { 145, 0x0B75 }, /* R145 - EQ12 */
166 { 146, 0x01C5 }, /* R146 - EQ13 */
167 { 147, 0x1C58 }, /* R147 - EQ14 */
168 { 148, 0xF373 }, /* R148 - EQ15 */
169 { 149, 0x0A54 }, /* R149 - EQ16 */
170 { 150, 0x0558 }, /* R150 - EQ17 */
171 { 151, 0x168E }, /* R151 - EQ18 */
172 { 152, 0xF829 }, /* R152 - EQ19 */
173 { 153, 0x07AD }, /* R153 - EQ20 */
174 { 154, 0x1103 }, /* R154 - EQ21 */
175 { 155, 0x0564 }, /* R155 - EQ22 */
176 { 156, 0x0559 }, /* R156 - EQ23 */
177 { 157, 0x4000 }, /* R157 - EQ24 */
178 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
179 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
180 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
181 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
325 switch (wm8904->sysclk_src) {
327 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
330 rate = wm8904->mclk_rate;
338 dev_dbg(component->dev, "Using %dHz FLL clock\n",
339 wm8904->fll_fout);
342 rate = wm8904->fll_fout;
346 dev_err(component->dev, "System clock not configured\n");
347 return -EINVAL;
353 wm8904->sysclk_rate = rate / 2;
356 wm8904->sysclk_rate = rate;
365 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
373 struct wm8904_pdata *pdata = wm8904->pdata;
381 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
393 struct wm8904_pdata *pdata = wm8904->pdata;
394 int value = ucontrol->value.enumerated.item[0];
396 if (value >= pdata->num_drc_cfgs)
397 return -EINVAL;
399 wm8904->drc_cfg = value;
412 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
420 struct wm8904_pdata *pdata = wm8904->pdata;
423 if (!pdata || !wm8904->num_retune_mobile_texts)
428 cfg = wm8904->retune_mobile_cfg;
431 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
432 if (strcmp(pdata->retune_mobile_cfgs[i].name,
433 wm8904->retune_mobile_texts[cfg]) == 0 &&
434 abs(pdata->retune_mobile_cfgs[i].rate
435 - wm8904->fs) < best_val) {
437 best_val = abs(pdata->retune_mobile_cfgs[i].rate
438 - wm8904->fs);
442 dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
443 pdata->retune_mobile_cfgs[best].name,
444 pdata->retune_mobile_cfgs[best].rate,
445 wm8904->fs);
454 pdata->retune_mobile_cfgs[best].regs[i]);
464 struct wm8904_pdata *pdata = wm8904->pdata;
465 int value = ucontrol->value.enumerated.item[0];
467 if (value >= pdata->num_retune_mobile_cfgs)
468 return -EINVAL;
470 wm8904->retune_mobile_cfg = value;
483 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
498 if (wm8904->deemph) {
501 if (abs(deemph_settings[i] - wm8904->fs) <
502 abs(deemph_settings[best] - wm8904->fs))
511 dev_dbg(component->dev, "Set deemphasis %d\n", val);
523 ucontrol->value.integer.value[0] = wm8904->deemph;
532 unsigned int deemph = ucontrol->value.integer.value[0];
535 return -EINVAL;
537 wm8904->deemph = deemph;
543 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
544 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
545 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
546 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
549 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
566 if (ucontrol->value.integer.value[0])
645 return -EINVAL;
656 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
666 switch (wm8904->sysclk_src) {
694 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
708 reg = w->shift;
731 return -EINVAL;
756 /* Either calibrate the DC servo or restore cached state
759 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
760 dev_dbg(component->dev, "Restoring DC servo state\n");
763 wm8904->dcs_state[dcs_l]);
765 wm8904->dcs_state[dcs_r]);
771 dev_dbg(component->dev, "Calibrating DC servo\n");
787 } while (--timeout);
790 dev_warn(component->dev, "DC servo timed out\n");
792 dev_dbg(component->dev, "DC servo ready\n");
824 wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg);
825 wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg);
868 "Single-Ended", "Differential Line", "Differential Mic"
1101 { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" },
1115 { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" },
1256 switch (wm8904->devtype) {
1359 struct snd_soc_component *component = dai->component;
1369 wm8904->fs = params_rate(params);
1370 if (wm8904->tdm_slots) {
1371 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
1372 wm8904->tdm_slots, wm8904->tdm_width);
1373 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1374 wm8904->tdm_width, 2,
1375 wm8904->tdm_slots);
1377 wm8904->bclk = snd_soc_params_to_bclk(params);
1393 return -EINVAL;
1397 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1405 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1406 - wm8904->fs);
1408 cur_val = abs((wm8904->sysclk_rate /
1409 clk_sys_rates[i].ratio) - wm8904->fs);
1415 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1422 best_val = abs(wm8904->fs - sample_rates[0].rate);
1425 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1431 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1437 if (wm8904->fs <= 24000)
1444 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1445 - wm8904->bclk;
1453 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1454 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1455 bclk_divs[best].div, wm8904->bclk);
1459 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1460 aif3 |= wm8904->bclk / wm8904->fs;
1484 struct snd_soc_component *component = dai->component;
1502 return -EINVAL;
1521 return -EINVAL;
1535 return -EINVAL;
1555 return -EINVAL;
1559 return -EINVAL;
1575 struct snd_soc_component *component = dai->component;
1583 /* Note that we allow configurations we can't handle ourselves -
1596 return -EINVAL;
1607 return -EINVAL;
1611 wm8904->tdm_width = slot_width;
1612 wm8904->tdm_slots = slots / 2;
1656 fll_div->fll_clk_ref_div = 0;
1659 fll_div->fll_clk_ref_div++;
1664 return -EINVAL;
1673 /* Fvco should be 90-100MHz; don't check the upper bound */
1680 return -EINVAL;
1684 fll_div->fll_outdiv = div - 1;
1691 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1698 return -EINVAL;
1704 fll_div->n = Ndiv;
1708 /* Calculate fractional part - scale up so we can round. */
1719 fll_div->k = K / 10;
1722 fll_div->n, fll_div->k,
1723 fll_div->fll_fratio, fll_div->fll_outdiv,
1724 fll_div->fll_clk_ref_div);
1732 struct snd_soc_component *component = dai->component;
1739 if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1740 Fout == wm8904->fll_fout)
1746 dev_dbg(component->dev, "FLL disabled\n");
1748 wm8904->fll_fref = 0;
1749 wm8904->fll_fout = 0;
1772 dev_dbg(component->dev, "Using free running FLL\n");
1782 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
1783 return -EINVAL;
1848 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1850 wm8904->fll_fref = Fref;
1851 wm8904->fll_fout = Fout;
1852 wm8904->fll_src = source;
1871 struct snd_soc_component *component = dai->component;
1884 mclk_freq = clk_get_rate(priv->mclk);
1887 priv->sysclk_src = WM8904_CLK_FLL;
1899 priv->sysclk_src = clk_id;
1900 priv->mclk_rate = freq;
1904 priv->sysclk_src = clk_id;
1908 return -EINVAL;
1911 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1920 struct snd_soc_component *component = codec_dai->component;
1956 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1957 wm8904->supplies);
1959 dev_err(component->dev,
1965 ret = clk_prepare_enable(wm8904->mclk);
1967 dev_err(component->dev,
1968 "Failed to enable MCLK: %d\n", ret);
1969 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1970 wm8904->supplies);
1974 regcache_cache_only(wm8904->regmap, false);
1975 regcache_sync(wm8904->regmap);
2012 regcache_cache_only(wm8904->regmap, true);
2013 regcache_mark_dirty(wm8904->regmap);
2015 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
2016 wm8904->supplies);
2017 clk_disable_unprepare(wm8904->mclk);
2039 .name = "wm8904-hifi",
2061 struct wm8904_pdata *pdata = wm8904->pdata;
2064 wm8904->retune_mobile_enum,
2074 wm8904->num_retune_mobile_texts = 0;
2075 wm8904->retune_mobile_texts = NULL;
2076 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2077 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
2078 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2079 wm8904->retune_mobile_texts[j]) == 0)
2083 if (j != wm8904->num_retune_mobile_texts)
2087 t = krealloc(wm8904->retune_mobile_texts,
2089 (wm8904->num_retune_mobile_texts + 1),
2095 t[wm8904->num_retune_mobile_texts] =
2096 pdata->retune_mobile_cfgs[i].name;
2099 wm8904->num_retune_mobile_texts++;
2100 wm8904->retune_mobile_texts = t;
2103 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
2104 wm8904->num_retune_mobile_texts);
2106 wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
2107 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2111 dev_err(component->dev,
2119 struct wm8904_pdata *pdata = wm8904->pdata;
2122 if (!pdata->in1l_as_dmicdat1 && !pdata->in1r_as_dmicdat2) {
2136 if (pdata->in1l_as_dmicdat1 && pdata->in1r_as_dmicdat2) {
2138 dev_dbg(component->dev, "DMICDAT1 and DMICDAT2 in use\n");
2147 if (pdata->in1l_as_dmicdat1) {
2156 dev_dbg(component->dev, "DMIC_SRC (0 or 1): %d\n", dmic_src);
2166 struct wm8904_pdata *pdata = wm8904->pdata;
2179 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2181 if (pdata->num_drc_cfgs) {
2183 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2187 wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs,
2190 if (!wm8904->drc_texts)
2193 for (i = 0; i < pdata->num_drc_cfgs; i++)
2194 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2196 wm8904->drc_enum.items = pdata->num_drc_cfgs;
2197 wm8904->drc_enum.texts = wm8904->drc_texts;
2201 dev_err(component->dev,
2207 dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
2208 pdata->num_retune_mobile_cfgs);
2210 if (pdata->num_retune_mobile_cfgs)
2222 switch (wm8904->devtype) {
2229 dev_err(component->dev, "Unknown device type %d\n",
2230 wm8904->devtype);
2231 return -EINVAL;
2246 kfree(wm8904->retune_mobile_texts);
2247 kfree(wm8904->drc_texts);
2287 * wm8904_read_cfg_reg_arr() - Reads a subarray from a DT u16 array
2295 * Helper to read a subarray from a DT uint16-array,
2322 return wm8904_read_cfg_reg_arr(np, "wlf,retune-mobile-cfg-regs",
2324 &pdata->retune_mobile_cfgs[cfg_idx].regs[0]);
2330 return wm8904_read_cfg_reg_arr(np, "wlf,drc-cfg-regs",
2332 &pdata->drc_cfgs[cfg_idx].regs[0]);
2338 const struct device_node *np = i2c->dev.of_node;
2341 n_cfgs = of_property_count_strings(np, "wlf,drc-cfg-names");
2342 if (n_cfgs == -EINVAL)
2346 dev_err(&i2c->dev, "Could not get wlf,drc-cfg-names length: %d",
2351 pdata->drc_cfgs = devm_kzalloc(&i2c->dev,
2354 if (!pdata->drc_cfgs)
2355 return -ENOMEM;
2359 dev_err(&i2c->dev,
2360 "Invalid 'wlf,drc-cfg-regs[%i,:]'\n", i);
2361 return -EINVAL;
2364 if (of_property_read_string_index(np, "wlf,drc-cfg-names", i,
2365 &pdata->drc_cfgs[i].name)) {
2366 dev_err(&i2c->dev,
2367 "Invalid 'wlf,drc-cfg-names[%i]'\n", i);
2368 return -EINVAL;
2372 pdata->num_drc_cfgs = n_cfgs;
2379 const struct device_node *np = i2c->dev.of_node;
2382 n_cfgs = of_property_count_strings(np, "wlf,retune-mobile-cfg-names");
2383 if (n_cfgs == -EINVAL)
2387 dev_err(&i2c->dev,
2388 "Could not get wlf,retune-mobile-cfg-names length: %d",
2393 pdata->retune_mobile_cfgs = devm_kzalloc(&i2c->dev,
2396 if (!pdata->retune_mobile_cfgs)
2397 return -ENOMEM;
2401 dev_err(&i2c->dev,
2402 "Invalid 'wlf,retune-mobile-cfg-regs[%i,:]'\n", i);
2403 return -EINVAL;
2406 if (of_property_read_u32_index(np, "wlf,retune-mobile-cfg-hz", i,
2407 &pdata->retune_mobile_cfgs[i].rate)) {
2408 dev_err(&i2c->dev,
2409 "Invalid 'wlf,retune-mobile-cfg-hz[%i]'\n", i);
2410 return -EINVAL;
2413 if (of_property_read_string_index(np, "wlf,retune-mobile-cfg-names", i,
2414 &pdata->retune_mobile_cfgs[i].name)) {
2415 dev_err(&i2c->dev,
2416 "Invalid 'wlf,retune-mobile-cfg-names[%i]'\n", i);
2417 return -EINVAL;
2421 pdata->num_retune_mobile_cfgs = n_cfgs;
2428 const struct device_node *np = i2c->dev.of_node;
2432 pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
2434 return -ENOMEM;
2436 pdata->in1l_as_dmicdat1 =
2437 of_property_read_bool(np, "wlf,in1l-as-dmicdat1");
2439 pdata->in1r_as_dmicdat2 =
2440 of_property_read_bool(np, "wlf,in1r-as-dmicdat2");
2444 pdata->gpio_cfg[i] = 0xFFFF;
2446 of_property_read_u32_array(np, "wlf,gpio-cfg", pdata->gpio_cfg,
2447 ARRAY_SIZE(pdata->gpio_cfg));
2449 of_property_read_u32_array(np, "wlf,micbias-cfg", pdata->mic_cfg,
2450 ARRAY_SIZE(pdata->mic_cfg));
2460 wm8904->pdata = pdata;
2472 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2475 return -ENOMEM;
2477 wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
2478 if (IS_ERR(wm8904->mclk)) {
2479 ret = PTR_ERR(wm8904->mclk);
2480 dev_err(&i2c->dev, "Failed to get MCLK\n");
2484 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
2485 if (IS_ERR(wm8904->regmap)) {
2486 ret = PTR_ERR(wm8904->regmap);
2487 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2492 wm8904->devtype = (uintptr_t)i2c_get_match_data(i2c);
2496 if (i2c->dev.of_node) {
2499 dev_err(&i2c->dev, "Failed to set platform data from of: %d\n", ret);
2503 wm8904->pdata = i2c->dev.platform_data;
2506 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2507 wm8904->supplies[i].supply = wm8904_supply_names[i];
2509 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
2510 wm8904->supplies);
2512 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2516 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2517 wm8904->supplies);
2519 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2523 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
2525 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2529 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
2530 ret = -EINVAL;
2534 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
2536 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2540 dev_info(&i2c->dev, "revision %c\n", val + 'A');
2542 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
2544 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2548 /* Change some default settings - latch VU and enable ZC */
2549 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2551 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2553 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2555 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2557 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2560 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2563 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2566 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2569 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2573 if (wm8904->pdata) {
2576 if (wm8904->pdata->gpio_cfg[i] == 0xffff)
2579 regmap_update_bits(wm8904->regmap,
2582 wm8904->pdata->gpio_cfg[i]);
2587 regmap_update_bits(wm8904->regmap,
2590 wm8904->pdata->mic_cfg[i]);
2593 /* Set Class W by default - this will be managed by the Class
2596 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2600 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2604 regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val);
2607 regcache_cache_only(wm8904->regmap, true);
2608 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2610 ret = devm_snd_soc_register_component(&i2c->dev,
2618 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);