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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Duniphier-pcie.txt1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
[all …]
H A Dxilinx-nwl-pcie.txt4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
13 "pcireg": PCIe controller registers
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
[all …]
H A Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pci
[all...]
H A Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
[all …]
H A Dpci-keystone.txt3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
21 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
22 interrupt-cells: should be set to 1
[all …]
H A Daardvark-pci.txt1 Aardvark PCIe controller
3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
5 The Device Tree node describing an Aardvark PCIe controller must
8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
[all …]
H A Dxilinx-versal-cpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
23 - description: CPM system level control and status registers.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dnvidia,tegra20-ictlr.txt1 NVIDIA Legacy Interrupt Controller
3 All Tegra SoCs contain a legacy interrupt controller that routes
7 The HW block exposes a number of interrupt controllers, each
12 - compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
13 subsequent SoCs remained backwards-compatible with Tegra30, so on
15 include "nvidia,tegra30-ictlr".
16 - reg : Specifies base physical address and size of the registers.
17 Each controller must be described separately (Tegra20 has 4 of them,
19 - interrupt-controller : Identifies the node as an interrupt controller.
20 - #interrupt-cells : Specifies the number of cells needed to encode an
[all …]
H A Daspeed,ast2400-vic.txt1 Aspeed Vectored Interrupt Controller
3 These bindings are for the Aspeed interrupt controller. The AST2400 and
4 AST2500 SoC families include a legacy register layout before a re-designed
9 - compatible : "aspeed,ast2400-vic"
10 "aspeed,ast2500-vic"
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt source. The value shall be 1.
18 vic: interrupt-controller@1e6c0080 {
19 compatible = "aspeed,ast2400-vic";
[all …]
H A Dmstar,mst-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MStar Interrupt Controller
10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
13 MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
14 interrupt controllers that routes interrupts to the GIC.
16 The HW block exposes a number of interrupt controllers, each
21 const: mstar,mst-intc
[all …]
H A Dintel,ce4100-lapic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
10 - Rahul Tanwar <rtanwar@maxlinear.com>
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
17 (lapic) receives interrupts from the processor's interrupt pins,
26 This schema defines bindings for local APIC interrupt controller.
[all …]
H A Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dti,omap-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dcurrituck.dts11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
[all …]
H A Dredwood.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
26 #address-cells = <1>;
27 #size-cells = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <32>;
36 d-cache-line-size = <32>;
[all …]
H A Dakebono.dts12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dmakalu.dts11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dkatmai.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <32>;
42 d-cache-line-size = <32>;
[all …]
H A Dkilauea.dts4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_iofic.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
38 * @defgroup group_interrupts Common I/O Fabric Interrupt Controller
39 * This HAL provides the API for programming the Common I/O Fabric Interrupt
40 * Controller (IOFIC) found in most of the units attached to the I/O Fabric of
45 * @brief Header file for the interrupt controller that's embedded in various units
54 /* *INDENT-OFF* */
58 /* *INDENT-ON* */
67 * Configure the interrupt controller registers, actual interrupts are still
70 * @param regs_base regs pointer to interrupt controller registers
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dtc3589x.txt1 * Toshiba TC3589x multi-purpose expander
3 The Toshiba TC3589x series are I2C-based MFD devices which may expose the
4 following built-in devices: gpio, keypad, rotator (vibrator), PWM (for
7 - TC35890
8 - TC35892
9 - TC35893
10 - TC35894
11 - TC35895
12 - TC35896
15 - compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM654 MMC Controller
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
[all …]

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