Lines Matching +full:legacy +full:- +full:interrupt +full:- +full:controller
12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
49 clock-frequency = <1600000000>; // 1.6 GHz
50 timebase-frequency = <100000000>; // 100Mhz
51 i-cache-line-size = <32>;
52 d-cache-line-size = <32>;
53 i-cache-size = <32768>;
54 d-cache-size = <32768>;
55 dcr-controller;
56 dcr-access-method = "native";
58 enable-method = "spin-table";
59 cpu-release-addr = <0x0 0x01f00000>;
68 MPIC: interrupt-controller {
69 compatible = "chrp,open-pic";
70 interrupt-controller;
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
74 #interrupt-cells = <2>;
75 single-cpu-affinity;
80 #address-cells = <2>;
81 #size-cells = <2>;
83 clock-frequency = <200000000>; // 200Mhz
86 compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
88 interrupt-parent = <&MPIC>;
108 compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
109 dcr-reg = <0xc0000000 0x062>;
110 num-tx-chans = <1>;
111 num-rx-chans = <1>;
112 #address-cells = <0>;
113 #size-cells = <0>;
114 interrupt-parent = <&MPIC>;
123 compatible = "ibm,476gtr-ahci";
125 interrupt-parent = <&MPIC>;
130 compatible = "ibm,476gtr-ehci", "generic-ehci";
132 interrupt-parent = <&MPIC>;
137 compatible = "ibm,476gtr-sdhci", "generic-sdhci";
140 interrupt-parent = <&MPIC>;
144 compatible = "ibm,476gtr-ohci", "generic-ohci";
146 interrupt-parent = <&MPIC>;
151 compatible = "ibm,476gtr-ohci", "generic-ohci";
153 interrupt-parent = <&MPIC>;
158 compatible = "ibm,opb-4xx", "ibm,opb";
159 #address-cells = <1>;
160 #size-cells = <1>;
162 * 32-bit range
166 clock-frequency = <100000000>;
168 RGMII0: emac-rgmii-wol@50004 {
169 compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
171 has-mdio;
176 compatible = "ibm,emac-476gtr", "ibm,emac4sync";
177 interrupt-parent = <&EMAC0>;
179 #interrupt-cells = <1>;
180 #address-cells = <0>;
181 #size-cells = <0>;
182 interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
186 /* local-mac-address will normally be added by
189 * local-mac-addr=<hwaddr>) then you will need
191 //local-mac-address = [000000000000];
193 mal-device = <&MAL0>;
194 mal-tx-channel = <0>;
195 mal-rx-channel = <0>;
196 cell-index = <0>;
197 max-frame-size = <9000>;
198 rx-fifo-size = <4096>;
199 tx-fifo-size = <2048>;
200 rx-fifo-size-gige = <16384>;
201 phy-mode = "rgmii";
202 phy-map = <0x00000000>;
203 rgmii-wol-device = <&RGMII0>;
204 has-inverted-stacr-oc;
205 has-new-stacr-staopc;
212 virtual-reg = <0xe8010000>;
213 clock-frequency = <1851851>;
214 current-speed = <38400>;
215 interrupt-parent = <&MPIC>;
220 compatible = "ibm,iic-476gtr", "ibm,iic";
222 interrupt-parent = <&MPIC>;
224 #address-cells = <1>;
225 #size-cells = <0>;
233 compatible = "ibm,iic-476gtr", "ibm,iic";
235 interrupt-parent = <&MPIC>;
237 #address-cells = <1>;
238 #size-cells = <0>;
240 compatible = "ibm,akebono-avr";
246 compatible = "ibm,akebono-fpga";
253 #interrupt-cells = <1>;
254 #size-cells = <2>;
255 #address-cells = <3>;
256 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
261 dcr-reg = <0xc0 0x20>;
270 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
273 bus-range = <0x0 0xf>;
275 /* Legacy interrupts (note the weird polarity, the bridge seems
276 * to invert PCIe legacy interrupts).
277 * We are de-swizzling here because the numbers are actually for
280 * below are basically de-swizzled numbers.
283 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
284 interrupt-map = <
293 #interrupt-cells = <1>;
294 #size-cells = <2>;
295 #address-cells = <3>;
296 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
301 dcr-reg = <0x100 0x20>;
310 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
313 bus-range = <0x0 0xf>;
315 /* Legacy interrupts (note the weird polarity, the bridge seems
316 * to invert PCIe legacy interrupts).
317 * We are de-swizzling here because the numbers are actually for
320 * below are basically de-swizzled numbers.
323 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
324 interrupt-map = <
333 #interrupt-cells = <1>;
334 #size-cells = <2>;
335 #address-cells = <3>;
336 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
341 dcr-reg = <0xe0 0x20>;
350 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
353 bus-range = <0x0 0xf>;
355 /* Legacy interrupts (note the weird polarity, the bridge seems
356 * to invert PCIe legacy interrupts).
357 * We are de-swizzling here because the numbers are actually for
360 * below are basically de-swizzled numbers.
363 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
364 interrupt-map = <
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
381 dcr-reg = <0x120 0x20>;
390 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
393 bus-range = <0x0 0xf>;
395 /* Legacy interrupts (note the weird polarity, the bridge seems
396 * to invert PCIe legacy interrupts).
397 * We are de-swizzling here because the numbers are actually for
400 * below are basically de-swizzled numbers.
403 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
404 interrupt-map = <
413 stdout-path = &UART0;