Lines Matching +full:legacy +full:- +full:interrupt +full:- +full:controller
15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <32>;
42 d-cache-line-size = <32>;
43 i-cache-size = <32768>;
44 d-cache-size = <32768>;
45 dcr-controller;
46 dcr-access-method = "native";
47 reset-type = <2>; /* Use chip-reset */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
56 UIC0: interrupt-controller0 {
57 compatible = "ibm,uic-440spe","ibm,uic";
58 interrupt-controller;
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
62 #size-cells = <0>;
63 #interrupt-cells = <2>;
66 UIC1: interrupt-controller1 {
67 compatible = "ibm,uic-440spe","ibm,uic";
68 interrupt-controller;
69 cell-index = <1>;
70 dcr-reg = <0x0d0 0x009>;
71 #address-cells = <0>;
72 #size-cells = <0>;
73 #interrupt-cells = <2>;
75 interrupt-parent = <&UIC0>;
78 UIC2: interrupt-controller2 {
79 compatible = "ibm,uic-440spe","ibm,uic";
80 interrupt-controller;
81 cell-index = <2>;
82 dcr-reg = <0x0e0 0x009>;
83 #address-cells = <0>;
84 #size-cells = <0>;
85 #interrupt-cells = <2>;
87 interrupt-parent = <&UIC0>;
90 UIC3: interrupt-controller3 {
91 compatible = "ibm,uic-440spe","ibm,uic";
92 interrupt-controller;
93 cell-index = <3>;
94 dcr-reg = <0x0f0 0x009>;
95 #address-cells = <0>;
96 #size-cells = <0>;
97 #interrupt-cells = <2>;
99 interrupt-parent = <&UIC0>;
103 compatible = "ibm,sdr-440spe";
104 dcr-reg = <0x00e 0x002>;
108 compatible = "ibm,cpr-440spe";
109 dcr-reg = <0x00c 0x002>;
113 compatible = "ibm,mq-440spe";
114 dcr-reg = <0x040 0x020>;
118 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
119 #address-cells = <2>;
120 #size-cells = <1>;
121 /* addr-child addr-parent size */
132 clock-frequency = <0>; /* Filled in by zImage */
135 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
136 dcr-reg = <0x010 0x002>;
140 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
141 dcr-reg = <0x180 0x062>;
142 num-tx-chans = <2>;
143 num-rx-chans = <1>;
144 interrupt-parent = <&MAL0>;
146 #interrupt-cells = <1>;
147 #address-cells = <0>;
148 #size-cells = <0>;
149 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
157 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
158 #address-cells = <1>;
159 #size-cells = <1>;
161 clock-frequency = <0>; /* Filled in by zImage */
164 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
165 dcr-reg = <0x012 0x002>;
166 #address-cells = <2>;
167 #size-cells = <1>;
168 clock-frequency = <0>; /* Filled in by zImage */
169 /* ranges property is supplied by U-Boot */
171 interrupt-parent = <&UIC1>;
174 compatible = "cfi-flash";
175 bank-width = <2>;
177 #address-cells = <1>;
178 #size-cells = <1>;
200 label = "u-boot";
210 virtual-reg = <0xa0000200>;
211 clock-frequency = <0>; /* Filled in by zImage */
212 current-speed = <115200>;
213 interrupt-parent = <&UIC0>;
221 virtual-reg = <0xa0000300>;
222 clock-frequency = <0>;
223 current-speed = <0>;
224 interrupt-parent = <&UIC0>;
233 virtual-reg = <0xa0000600>;
234 clock-frequency = <0>;
235 current-speed = <0>;
236 interrupt-parent = <&UIC1>;
241 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
243 interrupt-parent = <&UIC0>;
248 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
250 interrupt-parent = <&UIC0>;
255 linux,network-index = <0x0>;
257 compatible = "ibm,emac-440spe", "ibm,emac4";
258 interrupt-parent = <&UIC1>;
261 local-mac-address = [000000000000];
262 mal-device = <&MAL0>;
263 mal-tx-channel = <0>;
264 mal-rx-channel = <0>;
265 cell-index = <0>;
266 max-frame-size = <9000>;
267 rx-fifo-size = <4096>;
268 tx-fifo-size = <2048>;
269 phy-mode = "gmii";
270 phy-map = <0x00000000>;
271 has-inverted-stacr-oc;
272 has-new-stacr-staopc;
278 #interrupt-cells = <1>;
279 #size-cells = <2>;
280 #address-cells = <3>;
281 compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
283 large-inbound-windows;
284 enable-msi-hole;
298 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
301 bus-range = <0x0 0xf>;
304 * On Katmai, the following PCI-X interrupts signals
308 * INTB: J3: 1-2
309 * INTC: J2: 1-2
310 * INTD: J1: 1-2
312 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
313 interrupt-map = <
324 #interrupt-cells = <1>;
325 #size-cells = <2>;
326 #address-cells = <3>;
327 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
332 dcr-reg = <0x100 0x020>;
333 sdr-base = <0x300>;
342 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
345 bus-range = <0x10 0x1f>;
347 /* Legacy interrupts (note the weird polarity, the bridge seems
348 * to invert PCIe legacy interrupts).
349 * We are de-swizzling here because the numbers are actually for
352 * below are basically de-swizzled numbers.
355 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
356 interrupt-map = <
365 #interrupt-cells = <1>;
366 #size-cells = <2>;
367 #address-cells = <3>;
368 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
373 dcr-reg = <0x120 0x020>;
374 sdr-base = <0x340>;
383 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
386 bus-range = <0x20 0x2f>;
388 /* Legacy interrupts (note the weird polarity, the bridge seems
389 * to invert PCIe legacy interrupts).
390 * We are de-swizzling here because the numbers are actually for
393 * below are basically de-swizzled numbers.
396 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
397 interrupt-map = <
406 #interrupt-cells = <1>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
414 dcr-reg = <0x140 0x020>;
415 sdr-base = <0x370>;
424 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
427 bus-range = <0x30 0x3f>;
429 /* Legacy interrupts (note the weird polarity, the bridge seems
430 * to invert PCIe legacy interrupts).
431 * We are de-swizzling here because the numbers are actually for
434 * below are basically de-swizzled numbers.
437 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
438 interrupt-map = <
446 compatible = "ibm,i2o-440spe";
448 dcr-reg = <0x060 0x020>;
452 compatible = "ibm,dma-440spe";
453 cell-index = <0>;
455 dcr-reg = <0x060 0x020>;
456 interrupt-parent = <&DMA0>;
458 #interrupt-cells = <1>;
459 #address-cells = <0>;
460 #size-cells = <0>;
461 interrupt-map = <
467 compatible = "ibm,dma-440spe";
468 cell-index = <1>;
470 dcr-reg = <0x060 0x020>;
471 interrupt-parent = <&DMA1>;
473 #interrupt-cells = <1>;
474 #address-cells = <0>;
475 #size-cells = <0>;
476 interrupt-map = <
481 xor-accel@400200000 {
482 compatible = "amcc,xor-accelerator";
484 interrupt-parent = <&UIC1>;
490 stdout-path = "/plb/opb/serial@f0000200";