Lines Matching +full:legacy +full:- +full:interrupt +full:- +full:controller

1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 	According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16     "dbi"    - controller configuration registers
17     "link"   - SoC-specific glue layer registers
18     "config" - PCIe configuration space
19     "atu"    - iATU registers for DWC version 4.80 or later
20 - clocks: A phandle to the clock gate for PCIe glue layer including
21 	the host controller.
22 - resets: A phandle to the reset line for PCIe glue layer including
23 	the host controller.
24 - interrupts: A list of interrupt specifiers. According to the
25 	interrupt-names, appropriate interrupts are required.
26 - interrupt-names: Must include the following entries:
27     "dma" - DMA interrupt
28     "msi" - MSI interrupt
31 - phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
33 - phy-names: Must be "pcie-phy".
35 Required sub-node:
36 - legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
39 Required properties for legacy-interrupt-controller:
40 - interrupt-controller: identifies the node as an interrupt controller.
41 - #interrupt-cells: specifies the number of cells needed to encode an
42 	interrupt source. The value must be 1.
43 - interrupt-parent: Phandle to the parent interrupt controller.
44 - interrupts: An interrupt specifier for legacy interrupt.
49 		compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
51 		reg-names = "dbi", "link", "config";
54 		#address-cells = <3>;
55 		#size-cells = <2>;
58 		num-lanes = <1>;
59 		num-viewport = <1>;
60 		bus-range = <0x0 0xff>;
65 		/* non-prefetchable memory */
67 		#interrupt-cells = <1>;
68 		interrupt-names = "dma", "msi";
70 		interrupt-map-mask = <0 0 0  7>;
71 		interrupt-map = <0 0 0  1  &pcie_intc 0>,	/* INTA */
76 		pcie_intc: legacy-interrupt-controller {
77 			interrupt-controller;
78 			#interrupt-cells = <1>;
79 			interrupt-parent = <&gic>;