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/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dsocfpga-eccmgr.txt1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
[all …]
H A Daltr,socfpga-ecc-manager.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera SoCFPGA ECC Manager
11 - Matthew Gerlach <matthew.gerlach@altera.com>
15 ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
22 - items:
23 - const: altr,socfpga-s10-ecc-manager
24 - const: altr,socfpga-a10-ecc-manager
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/freebsd/sys/contrib/device-tree/Bindings/arm/calxeda/
H A Dl2ecc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
734 L2: cache-controller@fffef000 { global() label
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
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/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
[all …]
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
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/freebsd/sys/arm/include/
H A Dpte.h1 /*-
53 #define NMRR_WT 2 /* Write Through, Non-Write Allocate */
54 #define NMRR_WB 3 /* Write Back, Non-Write Allocate */
64 * 64K Large Pages (L2 table)
66 * 4K Small Pages (L2 table)
76 * via an L2 Table.
84 /* ARMv6 super-sections. */
86 #define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
91 #define L1_S_OFFSET (L1_S_SIZE - 1)
96 #define L2_L_OFFSET (L2_L_SIZE - 1)
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H A Darmreg.h3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
7 * Copyright (c) 1994-1996 Mark Brinicombe.
69 /* The high-order byte is always the implementor */
88 /* On recent ARMs this byte holds the architecture and variant (sub-model) */
145 /* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */
165 #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-V
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-db-xc3-24g4xg.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-XC3-24G4XG board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx3336.dtsi"
23 model = "DB-XC3-24G4XG";
24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
36 &L2 {
37 arm,parity-enable;
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H A Darmada-xp-crs328-4c-20s-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS328-4C-20S-4S+ board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS328-4C-20S-4S+";
25 compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
37 &L2 {
38 arm,parity-enable;
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H A Darmada-xp-crs326-24g-2s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS326-24G-2S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS326-24G-2S+";
25 compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
37 &L2 {
38 arm,parity-enable;
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H A Darmada-xp-crs305-1g-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS305-1G-4S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS305-1G-4S+";
25 compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
37 &L2 {
38 arm,parity-enable;
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/freebsd/lib/libpmc/
H A Dpmc.amd.31 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
54 .Bl -column "PMC_CAP_INTERRUPT" "Support"
71 .Bl -tag -width indent
77 Configure the counter to only count negated-to-asserted transitions
93 These additional qualifiers are event-specific and are documented
109 .Bl -tag -width indent
110 .It Li k8-b
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq9574-rdp-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
22 stdout-path = "serial0:115200n8";
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
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H A Dsdx75-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 compatible = "qcom,sdx75-idp", "qcom,sdx75";
22 vph_pwr: vph-pwr-regulator {
23 compatible = "regulator-fixed";
24 regulator-name = "vph_pwr";
25 regulator-min-microvolt = <3700000>;
26 regulator-max-microvolt = <3700000>;
29 vph_ext: vph-ext-regulator {
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
478 /* Disable L1 data cache and L2 snoop tag RAMs automatic invalidate on reset functionality */
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
[all …]
H A Dqcom-sdx55-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
7 /dts-v1/;
9 #include "qcom-sdx55.dtsi"
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 compatible = "qcom,sdx55-mt
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H A Dqcom-sdx55-telit-fn980-tlb.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-teli
[all...]
H A Dqcom-sdx55-t55.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-t5
[all...]
H A Dqcom-sdx65-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 /dts-v1/;
11 #include "qcom-sdx65.dtsi"
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
19 compatible = "qcom,sdx65-mtp", "qcom,sdx65";
20 qcom,board-i
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A Dmarked.json35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp…
45 …Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This imp…
80 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c…
115 … "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
140 … Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction…
155 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
170 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
215 …efDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2"
230 …Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is …
240 …data cache was reloaded either shared or modified data from another core's L2/L3 on a different ch…
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